From a930fec033a80bc92f5a11cc334ff4fc44cbe0ca Mon Sep 17 00:00:00 2001 From: paperchalice Date: Wed, 13 Dec 2023 12:46:22 +0800 Subject: [PATCH] [CodeGen] Port `InterleavedLoadCombine` to new pass manager (#75164) --- .../include/llvm/CodeGen/CodeGenPassBuilder.h | 1 + .../llvm/CodeGen/InterleavedLoadCombine.h | 29 +++++++++++++++++++ .../llvm/CodeGen/MachinePassRegistry.def | 1 + .../CodeGen/InterleavedLoadCombinePass.cpp | 12 +++++++- llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassRegistry.def | 1 + .../AArch64/aarch64-interleaved-ld-combine.ll | 1 + .../new-load-requires-renaming-in-mssa.ll | 1 + 8 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 llvm/include/llvm/CodeGen/InterleavedLoadCombine.h diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index fe604818886e..2a8aa7b158ed 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -27,6 +27,7 @@ #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandReductions.h" #include "llvm/CodeGen/InterleavedAccess.h" +#include "llvm/CodeGen/InterleavedLoadCombine.h" #include "llvm/CodeGen/JMCInstrumenter.h" #include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" diff --git a/llvm/include/llvm/CodeGen/InterleavedLoadCombine.h b/llvm/include/llvm/CodeGen/InterleavedLoadCombine.h new file mode 100644 index 000000000000..fa99aa316c2a --- /dev/null +++ b/llvm/include/llvm/CodeGen/InterleavedLoadCombine.h @@ -0,0 +1,29 @@ +//===- llvm/CodeGen/InterleavedLoadCombine.h --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_INTERLEAVEDLOADCOMBINE_H +#define LLVM_CODEGEN_INTERLEAVEDLOADCOMBINE_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class TargetMachine; + +class InterleavedLoadCombinePass + : public PassInfoMixin { + const TargetMachine *TM; + +public: + explicit InterleavedLoadCombinePass(const TargetMachine *TM) : TM(TM) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + +} // namespace llvm + +#endif // InterleavedLoadCombine diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index 283fb14fee31..4e2bee49a71c 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -47,6 +47,7 @@ FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, ()) FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ()) FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ()) FUNCTION_PASS("interleaved-access", InterleavedAccessPass, (TM)) +FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass, (TM)) FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) FUNCTION_PASS("lowerinvoke", LowerInvokePass, ()) FUNCTION_PASS("mergeicmps", MergeICmpsPass, ()) diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp index 3b1d26cfed79..f2d5c3c867c2 100644 --- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp +++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp @@ -23,6 +23,7 @@ #include "llvm/Analysis/MemorySSAUpdater.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/InterleavedLoadCombine.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetPassConfig.h" @@ -63,7 +64,7 @@ struct VectorInfo; struct InterleavedLoadCombineImpl { public: InterleavedLoadCombineImpl(Function &F, DominatorTree &DT, MemorySSA &MSSA, - TargetMachine &TM) + const TargetMachine &TM) : F(F), DT(DT), MSSA(MSSA), TLI(*TM.getSubtargetImpl(F)->getTargetLowering()), TTI(TM.getTargetTransformInfo(F)) {} @@ -1339,6 +1340,15 @@ private: }; } // anonymous namespace +PreservedAnalyses +InterleavedLoadCombinePass::run(Function &F, FunctionAnalysisManager &FAM) { + + auto &DT = FAM.getResult(F); + auto &MemSSA = FAM.getResult(F).getMSSA(); + bool Changed = InterleavedLoadCombineImpl(F, DT, MemSSA, *TM).run(); + return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all(); +} + char InterleavedLoadCombine::ID = 0; INITIALIZE_PASS_BEGIN( diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index f0417d6aa839..302fac68782c 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -78,6 +78,7 @@ #include "llvm/CodeGen/ExpandLargeFpConvert.h" #include "llvm/CodeGen/HardwareLoops.h" #include "llvm/CodeGen/InterleavedAccess.h" +#include "llvm/CodeGen/InterleavedLoadCombine.h" #include "llvm/CodeGen/JMCInstrumenter.h" #include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/SelectOptimize.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 1a9a34859332..746446d61325 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -320,6 +320,7 @@ FUNCTION_PASS("instcount", InstCountPass()) FUNCTION_PASS("instnamer", InstructionNamerPass()) FUNCTION_PASS("instsimplify", InstSimplifyPass()) FUNCTION_PASS("interleaved-access", InterleavedAccessPass(TM)) +FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass(TM)) FUNCTION_PASS("invalidate", InvalidateAllAnalysesPass()) FUNCTION_PASS("irce", IRCEPass()) FUNCTION_PASS("jump-threading", JumpThreadingPass()) diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll index a5d94c13ef01..35a140cb4bd4 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s | FileCheck --check-prefix AS %s ; RUN: opt -S -interleaved-load-combine < %s | FileCheck %s +; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s ; ModuleID = 'aarch64_interleaved-ld-combine.bc' target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/new-load-requires-renaming-in-mssa.ll b/llvm/test/CodeGen/AArch64/new-load-requires-renaming-in-mssa.ll index 6ba29a664be1..d45c06a6811c 100644 --- a/llvm/test/CodeGen/AArch64/new-load-requires-renaming-in-mssa.ll +++ b/llvm/test/CodeGen/AArch64/new-load-requires-renaming-in-mssa.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -interleaved-load-combine -S -verify-memoryssa %s | FileCheck %s +; RUN: opt -passes=interleaved-load-combine -S -verify-memoryssa %s | FileCheck %s target triple = "arm64-apple-darwin"