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[DAG] Reland: Enable bitcast STLF for Constant/Undef (#178890)

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This is a reland of #172523.

The original patch caused an assertion failure on RISC-V because it
attempted to create a bitcast from an illegal type (i32 on RV64) during
the post-type-legalization DAGCombine stage.

Added a `TLI.isTypeLegal(Val.getValueType())` check to ensure we only
proceed with the bitcast STLF optimization when the source value's type
is legal for the target.
This commit is contained in:
陈子昂 2026-01-31 01:21:32 +08:00 committed by GitHub
parent 4ea1791890
commit a994198906
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
42 changed files with 242 additions and 172 deletions
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29
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -20747,9 +20747,32 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
if (!isTypeLegal(LDMemType))
break;
if (STMemType != LDMemType) {
// TODO: Support vectors? This requires extract_subvector/bitcast.
if (!STMemType.isVector() && !LDMemType.isVector() &&
STMemType.isInteger() && LDMemType.isInteger())
if (LdMemSize == StMemSize) {
if (TLI.isOperationLegal(ISD::BITCAST, LDMemType) &&
isTypeLegal(LDMemType) &&
TLI.isOperationLegal(ISD::BITCAST, STMemType) &&
isTypeLegal(STMemType) &&
TLI.isLoadBitCastBeneficial(LDMemType, STMemType, DAG,
*LD->getMemOperand()))
Val = DAG.getBitcast(LDMemType, Val);
else
break;
} else if (LDMemType.isVector() && isTypeLegal(STMemType)) {
EVT EltVT = LDMemType.getVectorElementType();
TypeSize EltSize = EltVT.getSizeInBits();
if (!StMemSize.isKnownMultipleOf(EltSize))
break;
EVT InterVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
StMemSize.divideCoefficientBy(EltSize));
if (!TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, InterVT))
break;
Val = DAG.getExtractSubvector(SDLoc(LD), LDMemType,
DAG.getBitcast(InterVT, Val), 0);
} else if (!STMemType.isVector() && !LDMemType.isVector() &&
STMemType.isInteger() && LDMemType.isInteger())
Val = DAG.getNode(ISD::TRUNCATE, SDLoc(LD), LDMemType, Val);
else
break;

2
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
View File

@ -508,8 +508,8 @@ define <4 x i8> @small_vector(<4 x i8> %0) {
; CHECK-NEXT: add x29, sp, #176
; CHECK-NEXT: .seh_add_fp 176
; CHECK-NEXT: .seh_endprologue
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: str w0, [sp, #12]
; CHECK-NEXT: ldr s0, [sp, #12]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: blr x9

2
llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
View File

@ -477,8 +477,8 @@ declare <4 x i8> @small_vector(<4 x i8> %0) nounwind;
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: stur s0, [x29, #-4]
; CHECK-NEXT: blr x16
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: stur w8, [x29, #-8]
; CHECK-NEXT: ldur s0, [x29, #-8]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: .seh_startepilogue

3
llvm/test/CodeGen/AArch64/pr161013.ll
View File

@ -6,8 +6,7 @@ define <16 x i4> @avir_v2i4_v16i4(<2 x i4> %arg) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-NEXT: str d0, [sp, #8]
; CHECK-NEXT: ldr x8, [sp, #8]
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and w10, w8, #0xf
; CHECK-NEXT: ubfx w9, w8, #4, #4
; CHECK-NEXT: fmov s0, w10

1
llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
View File

@ -62,7 +62,6 @@ define <vscale x 4 x i32> @sti64ldi32(ptr nocapture %P, <vscale x 2 x i64> %v) {
; CHECK-LABEL: sti64ldi32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str z0, [x0, #1, mul vl]
; CHECK-NEXT: ldr z0, [x0, #1, mul vl]
; CHECK-NEXT: ret
entry:
%0 = bitcast ptr %P to ptr

12
llvm/test/CodeGen/AArch64/sve-stlf.ll Normal file
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@ -0,0 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s
define <vscale x 4 x i32> @test_stlf_scalable(ptr %p, <vscale x 4 x i32> %v) {
; CHECK-LABEL: test_stlf_scalable:
; CHECK: // %bb.0:
; CHECK-NEXT: str z0, [x0]
; CHECK-NEXT: ret
store <vscale x 4 x i32> %v, ptr %p
%res = load <vscale x 4 x i32>, ptr %p
ret <vscale x 4 x i32> %res
}

9
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
View File

@ -639,8 +639,7 @@ define <1 x i64> @ctlz_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: clz x8, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %op)
@ -2309,8 +2308,7 @@ define <1 x i64> @ctpop_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: and x9, x9, #0xf0f0f0f0f0f0f0f
; NONEON-NOSVE-NEXT: mul x8, x9, x8
; NONEON-NOSVE-NEXT: lsr x8, x8, #56
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %op)
@ -3189,8 +3187,7 @@ define <1 x i64> @cttz_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: rbit x8, x8
; NONEON-NOSVE-NEXT: clz x8, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %op)

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
View File

@ -451,8 +451,7 @@ define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcmp d0, d1
; NONEON-NOSVE-NEXT: csetm x8, eq
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%cmp = fcmp oeq <1 x double> %op1, %op2

2
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
View File

@ -415,8 +415,6 @@ define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldr h0, [x0]
; NONEON-NOSVE-NEXT: fcvt d0, h0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: str d0, [x1]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret

2
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
View File

@ -591,8 +591,6 @@ define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmadd d0, d0, d1, d2
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%mul = fmul contract <1 x double> %op1, %op2

8
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
View File

@ -392,8 +392,6 @@ define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmaxnm d0, d0, d1
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.maxnum.v1f64(<1 x double> %op1, <1 x double> %op2)
@ -853,8 +851,6 @@ define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fminnm d0, d0, d1
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.minnum.v1f64(<1 x double> %op1, <1 x double> %op2)
@ -1314,8 +1310,6 @@ define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmax d0, d0, d1
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2)
@ -1775,8 +1769,6 @@ define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmin d0, d0, d1
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2)

14
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
View File

@ -355,8 +355,6 @@ define <1 x double> @frintp_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintp d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.ceil.v1f64(<1 x double> %op)
@ -771,8 +769,6 @@ define <1 x double> @frintm_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintm d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.floor.v1f64(<1 x double> %op)
@ -1187,8 +1183,6 @@ define <1 x double> @frinti_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frinti d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> %op)
@ -1603,8 +1597,6 @@ define <1 x double> @frintx_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintx d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.rint.v1f64(<1 x double> %op)
@ -2019,8 +2011,6 @@ define <1 x double> @frinta_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frinta d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.round.v1f64(<1 x double> %op)
@ -2435,8 +2425,6 @@ define <1 x double> @frintn_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintn d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %op)
@ -2851,8 +2839,6 @@ define <1 x double> @frintz_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintz d0, d0
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.trunc.v1f64(<1 x double> %op)

2
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
View File

@ -379,8 +379,6 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: fcsel d0, d0, d1, ne
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2

12
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
View File

@ -433,8 +433,7 @@ define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvt s0, h0
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptoui <1 x half> %op1 to <1 x i64>
@ -1639,8 +1638,7 @@ define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvtzu x8, d0
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptoui <1 x double> %op1 to <1 x i64>
@ -2133,8 +2131,7 @@ define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvt s0, h0
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptosi <1 x half> %op1 to <1 x i64>
@ -3342,8 +3339,7 @@ define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvtzs x8, d0
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptosi <1 x double> %op1 to <1 x i64>

2
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
View File

@ -482,8 +482,6 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1>
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: fcsel d0, d0, d1, ne
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2

7
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
View File

@ -426,8 +426,7 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%r = insertelement <1 x i64> %op1, i64 5, i64 0
@ -760,9 +759,7 @@ define <1 x double> @insertelement_v1f64(<1 x double> %op1) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: mov x8, #4617315517961601024 // =0x4014000000000000
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, #5.00000000
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%r = insertelement <1 x double> %op1, double 5.0, i64 0

12
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
View File

@ -658,8 +658,7 @@ define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: add x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = add <1 x i64> %op1, %op2
@ -1462,8 +1461,7 @@ define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: mul x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = mul <1 x i64> %op1, %op2
@ -2203,8 +2201,7 @@ define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: sub x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = sub <1 x i64> %op1, %op2
@ -2925,8 +2922,7 @@ define <1 x i64> @abs_v1i64(<1 x i64> %op1) {
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: cmp x8, #0
; NONEON-NOSVE-NEXT: cneg x8, x8, mi
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.abs.v1i64(<1 x i64> %op1, i1 false)

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
View File

@ -723,8 +723,7 @@ define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: cmp x9, x8
; NONEON-NOSVE-NEXT: csetm x8, eq
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <1 x i64> %op1, %op2

6
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
View File

@ -816,8 +816,7 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: sdiv x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = sdiv <1 x i64> %op1, %op2
@ -1698,8 +1697,7 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: udiv x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = udiv <1 x i64> %op1, %op2

9
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
View File

@ -599,8 +599,7 @@ define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: and x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = and <1 x i64> %op1, %op2
@ -1268,8 +1267,7 @@ define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: orr x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = or <1 x i64> %op1, %op2
@ -1937,8 +1935,7 @@ define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: eor x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = xor <1 x i64> %op1, %op2

12
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
View File

@ -702,8 +702,7 @@ define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: cmp x9, x8
; NONEON-NOSVE-NEXT: csel x8, x9, x8, gt
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %op1, <1 x i64> %op2)
@ -1480,8 +1479,7 @@ define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: cmp x9, x8
; NONEON-NOSVE-NEXT: csel x8, x9, x8, lt
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %op1, <1 x i64> %op2)
@ -2258,8 +2256,7 @@ define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: cmp x9, x8
; NONEON-NOSVE-NEXT: csel x8, x9, x8, hi
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %op1, <1 x i64> %op2)
@ -3036,8 +3033,7 @@ define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: cmp x9, x8
; NONEON-NOSVE-NEXT: csel x8, x9, x8, lo
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %op1, <1 x i64> %op2)

30
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
View File

@ -1043,8 +1043,7 @@ define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: fmov x9, d1
; NONEON-NOSVE-NEXT: smulh x8, x8, x9
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%1 = sext <1 x i64> %op1 to <1 x i128>
@ -1075,9 +1074,7 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #16]
; NONEON-NOSVE-NEXT: smulh x8, x8, x10
; NONEON-NOSVE-NEXT: smulh x9, x9, x11
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #32]
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #48]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
@ -1125,12 +1122,8 @@ define void @smulh_v4i64(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: smulh x11, x11, x13
; NONEON-NOSVE-NEXT: smulh x8, x8, x12
; NONEON-NOSVE-NEXT: smulh x9, x9, x14
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #64]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #80]
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #80]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112]
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #64]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96]
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #96]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #112]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #128
@ -2178,8 +2171,7 @@ define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: fmov x9, d1
; NONEON-NOSVE-NEXT: umulh x8, x8, x9
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%1 = zext <1 x i64> %op1 to <1 x i128>
@ -2210,9 +2202,7 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #16]
; NONEON-NOSVE-NEXT: umulh x8, x8, x10
; NONEON-NOSVE-NEXT: umulh x9, x9, x11
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #32]
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #48]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
@ -2260,12 +2250,8 @@ define void @umulh_v4i64(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: umulh x11, x11, x13
; NONEON-NOSVE-NEXT: umulh x8, x8, x12
; NONEON-NOSVE-NEXT: umulh x9, x9, x14
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #64]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #80]
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #80]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112]
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #64]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96]
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #96]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #112]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #128

6
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
View File

@ -937,8 +937,7 @@ define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: sdiv x10, x9, x8
; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = srem <1 x i64> %op1, %op2
@ -1958,8 +1957,7 @@ define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: udiv x10, x9, x8
; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = urem <1 x i64> %op1, %op2

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
View File

@ -718,8 +718,7 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csel x8, x9, x8, ne
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2

9
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
View File

@ -667,8 +667,7 @@ define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: asr x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = ashr <1 x i64> %op1, %op2
@ -1403,8 +1402,7 @@ define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: lsr x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = lshr <1 x i64> %op1, %op2
@ -2137,8 +2135,7 @@ define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: lsl x8, x9, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = shl <1 x i64> %op1, %op2

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
View File

@ -404,8 +404,7 @@ define <1 x double> @ucvtf_v1i16_v1f64(<1 x i16> %op1) {
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #8]
; NONEON-NOSVE-NEXT: ucvtf d0, w8
; NONEON-NOSVE-NEXT: str d0, [sp]
; NONEON-NOSVE-NEXT: ldr d0, [sp], #16
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = uitofp <1 x i16> %op1 to <1 x double>
ret <1 x double> %res

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
View File

@ -950,8 +950,7 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) {
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csel x8, x9, x8, ne
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2

4
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
View File

@ -81,9 +81,7 @@ define void @alloc_v6i8(ptr %st_ptr) nounwind {
; NONEON-NOSVE-NEXT: mov x19, x0
; NONEON-NOSVE-NEXT: add x0, sp, #24
; NONEON-NOSVE-NEXT: bl def
; NONEON-NOSVE-NEXT: ldr x8, [sp, #24]
; NONEON-NOSVE-NEXT: str x8, [sp]
; NONEON-NOSVE-NEXT: ldr d0, [sp]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #11]
; NONEON-NOSVE-NEXT: strb w8, [sp, #21]

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
View File

@ -638,8 +638,7 @@ define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: rbit x8, x8
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %op)

3
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
View File

@ -847,8 +847,7 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) {
; NONEON-NOSVE-NEXT: asr x9, x8, #63
; NONEON-NOSVE-NEXT: add x8, x8, x9, lsr #59
; NONEON-NOSVE-NEXT: asr x8, x8, #5
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x8
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = sdiv <1 x i64> %op1, shufflevector (<1 x i64> insertelement (<1 x i64> poison, i64 32, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)

5
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
View File

@ -302,8 +302,7 @@ define <1 x i64> @splat_v1i64(i64 %a) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: str x0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: fmov d0, x0
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%insert = insertelement <1 x i64> poison, i64 %a, i64 0
@ -532,8 +531,6 @@ define <1 x double> @splat_v1f64(double %a, <1 x double> %op2) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%insert = insertelement <1 x double> poison, double %a, i64 0

8
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
View File

@ -314,9 +314,7 @@ define void @store_v1i64(ptr %a) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: str xzr, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: str xzr, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
store <1 x i64> zeroinitializer, ptr %a
@ -334,9 +332,7 @@ define void @store_v1f64(ptr %a) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: str xzr, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: str xzr, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
store <1 x double> zeroinitializer, ptr %a

9
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
View File

@ -138,12 +138,11 @@ define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) {
;
; NONEON-NOSVE-LABEL: store_trunc_v2i256i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr x8, [x0, #32]
; NONEON-NOSVE-NEXT: ldr x9, [x0]
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #-32]!
; NONEON-NOSVE-NEXT: sub sp, sp, #32
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
; NONEON-NOSVE-NEXT: ldr d0, [x0, #32]
; NONEON-NOSVE-NEXT: ldr d1, [x0]
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #16]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
; NONEON-NOSVE-NEXT: str q0, [x1]
; NONEON-NOSVE-NEXT: add sp, sp, #32

5
llvm/test/CodeGen/AArch64/v3f-to-int.ll
View File

@ -6,11 +6,8 @@ define void @convert_v3f32() {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: str wzr, [sp, #12]
; CHECK-NEXT: ldr s0, [sp, #12]
; CHECK-NEXT: strb wzr, [x8]
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: str h0, [x8]
; CHECK-NEXT: strh wzr, [x8]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
entry:

4
llvm/test/CodeGen/PowerPC/vsx-p9.ll
View File

@ -137,8 +137,8 @@ entry:
tail call void (...) @sink(<2 x double> %add.i12)
; CHECK: lxv 0, 0(3)
; CHECK: lxv 1, 0(3)
; CHECK: xvadddp 0, 0, 1
; CHECK: stxv 0,
; CHECK: xvadddp {{[0-9]+}}, 0, 1
; CHECK: stxv {{[0-9]+}},
; CHECK: bl sink
ret void
}

67
llvm/test/CodeGen/RISCV/rvv/stlf.ll Normal file
View File

@ -0,0 +1,67 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
define <vscale x 4 x i32> @test_stlf_riscv_scalable(ptr %p, <vscale x 4 x i32> %v) {
; CHECK-LABEL: test_stlf_riscv_scalable:
; CHECK: # %bb.0:
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
store <vscale x 4 x i32> %v, ptr %p
%res = load <vscale x 4 x i32>, ptr %p
ret <vscale x 4 x i32> %res
}
define void @test_stlf_i32_to_v2i8_assertion(ptr %arg, ptr %arg1) {
; CHECK-LABEL: test_stlf_i32_to_v2i8_assertion:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sw zero, 0(zero)
; CHECK-NEXT: lbu a2, 5(a0)
; CHECK-NEXT: lbu a3, 4(a0)
; CHECK-NEXT: slli a2, a2, 8
; CHECK-NEXT: or a2, a2, a3
; CHECK-NEXT: lbu a3, 1(a0)
; CHECK-NEXT: lbu a4, 0(a0)
; CHECK-NEXT: lbu a5, 2(a0)
; CHECK-NEXT: lbu a6, 3(a0)
; CHECK-NEXT: slli a3, a3, 8
; CHECK-NEXT: or a3, a3, a4
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: slli a5, a5, 16
; CHECK-NEXT: slli a6, a6, 24
; CHECK-NEXT: or a4, a6, a5
; CHECK-NEXT: addi a5, sp, 12
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: addi a1, a1, 2
; CHECK-NEXT: or a3, a4, a3
; CHECK-NEXT: addi a4, a0, 2
; CHECK-NEXT: sw a3, 8(sp)
; CHECK-NEXT: sh a2, 12(sp)
; CHECK-NEXT: addi a2, sp, 10
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a4)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v9, (a5)
; CHECK-NEXT: addi a3, sp, 8
; CHECK-NEXT: vle8.v v10, (a2)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a3)
; CHECK-NEXT: addi a1, a0, 4
; CHECK-NEXT: vse8.v v9, (a1)
; CHECK-NEXT: vse8.v v10, (a4)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
bb:
%alloca = alloca { i8, i8, i16, i16 }, align 1
store volatile i32 0, ptr null, align 4
call void @llvm.memcpy.p0.p0.i64(ptr %alloca, ptr %arg, i64 6, i1 false)
call void @llvm.memcpy.p0.p0.i64(ptr %arg1, ptr %arg, i64 6, i1 false)
call void @llvm.memcpy.p0.p0.i64(ptr %arg, ptr %alloca, i64 6, i1 false)
ret void
}

2
llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
View File

@ -55,8 +55,6 @@ define fp128 @load_fp128(ptr %fptr) {
; X64-AVX-LABEL: load_fp128:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
; X64-AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; X64-AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; X64-AVX-NEXT: retq
%v = load atomic fp128, ptr %fptr unordered, align 16
ret fp128 %v

5
llvm/test/CodeGen/X86/avx512-shuffles/shuffle-chained-bf16.ll
View File

@ -37,11 +37,8 @@ define <2 x bfloat> @shuffle_chained_v16bf16(<16 x bfloat> %a) {
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-32, %rsp
; CHECK-NEXT: subq $96, %rsp
; CHECK-NEXT: vmovaps %ymm0, (%rsp)
; CHECK-NEXT: vmovdqa (%rsp), %xmm0
; CHECK-NEXT: vmovdqa %ymm0, (%rsp)
; CHECK-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: movq %rbp, %rsp
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: .cfi_def_cfa %rsp, 8

71
llvm/test/CodeGen/X86/dag-stlf-mismatch.ll Normal file
View File

@ -0,0 +1,71 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
%struct.Data = type { float }
define float @test_stlf_integer(ptr %p, float %v) {
; CHECK-LABEL: test_stlf_integer:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $0, (%rdi)
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: mulss %xmm1, %xmm0
; CHECK-NEXT: retq
store i32 0, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
ret float %r
}
define float @test_stlf_vector(ptr %p, float %v) {
; CHECK-LABEL: test_stlf_vector:
; CHECK: # %bb.0:
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movups %xmm1, (%rdi)
; CHECK-NEXT: mulss (%rdi), %xmm0
; CHECK-NEXT: retq
store <4 x float> zeroinitializer, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
ret float %r
}
define float @test_stlf_bitcast(ptr %p, float %v) {
; CHECK-LABEL: test_stlf_bitcast:
; CHECK: # %bb.0:
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movups %xmm1, (%rdi)
; CHECK-NEXT: mulss (%rdi), %xmm0
; CHECK-NEXT: retq
store <2 x i64> zeroinitializer, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
ret float %r
}
declare void @ext_func(ptr byval(%struct.Data) align 4 %p)
define void @test_stlf_late_byval(ptr %ptr) nounwind {
; CHECK-LABEL: test_stlf_late_byval:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $0, (%rdi)
; CHECK-NEXT: movl $0, (%rsp)
; CHECK-NEXT: callq ext_func@PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
store i32 0, ptr %ptr, align 4
call void @ext_func(ptr byval(%struct.Data) align 4 %ptr)
ret void
}
define float @test_stlf_variable(ptr %p, i32 %val, float %v) {
; CHECK-LABEL: test_stlf_variable:
; CHECK: # %bb.0:
; CHECK-NEXT: movd %esi, %xmm1
; CHECK-NEXT: movl %esi, (%rdi)
; CHECK-NEXT: mulss %xmm1, %xmm0
; CHECK-NEXT: retq
store i32 %val, ptr %p, align 4
%f = load float, ptr %p, align 4
%r = fmul float %f, %v
ret float %r
}

5
llvm/test/CodeGen/X86/pr30290.ll
View File

@ -23,9 +23,8 @@ define void @foo(ptr byval(%struct.face) nocapture align 8) local_unnamed_addr {
; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,1,1]
; CHECK-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movl $1, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: vmovups %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %xmm1
; CHECK-NEXT: vmovups %xmm1, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovups %xmm0, (%rsp)
; CHECK-NEXT: callq bar@PLT
; CHECK-NEXT: addq $40, %rsp

9
llvm/test/CodeGen/X86/pr38533.ll
View File

@ -7,23 +7,20 @@
define void @constant_fold_vector_to_half() {
; SSE2-LABEL: constant_fold_vector_to_half:
; SSE2: # %bb.0:
; SSE2-NEXT: movw $16384, -{{[0-9]+}}(%rsp) # imm = 0x4000
; SSE2-NEXT: pinsrw $0, -{{[0-9]+}}(%rsp), %xmm0
; SSE2-NEXT: pinsrw $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pextrw $0, %xmm0, %eax
; SSE2-NEXT: movw %ax, (%rax)
; SSE2-NEXT: retq
;
; AVX512-LABEL: constant_fold_vector_to_half:
; AVX512: # %bb.0:
; AVX512-NEXT: movw $16384, -{{[0-9]+}}(%rsp) # imm = 0x4000
; AVX512-NEXT: vpinsrw $0, -{{[0-9]+}}(%rsp), %xmm0, %xmm0
; AVX512-NEXT: vpinsrw $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpextrw $0, %xmm0, (%rax)
; AVX512-NEXT: retq
;
; AVX512FP16-LABEL: constant_fold_vector_to_half:
; AVX512FP16: # %bb.0:
; AVX512FP16-NEXT: movw $16384, -{{[0-9]+}}(%rsp) # imm = 0x4000
; AVX512FP16-NEXT: vmovsh -{{[0-9]+}}(%rsp), %xmm0
; AVX512FP16-NEXT: vmovsh {{.*#+}} xmm0 = [2.0E+0,0.0E+0,0.0E+0,0.0E+0,0.0E+0,0.0E+0,0.0E+0,0.0E+0]
; AVX512FP16-NEXT: vmovsh %xmm0, (%rax)
; AVX512FP16-NEXT: retq
store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), ptr undef

8
llvm/test/CodeGen/X86/vectorcall.ll
View File

@ -152,10 +152,10 @@ entry:
define x86_vectorcallcc %struct.HVA4 @test_mixed_6(%struct.HVA4 inreg %a, ptr %b) {
; CHECK-LABEL: test_mixed_6
; CHECK: movaps (%{{[re]}}sp), %xmm0
; CHECK: movaps 16(%{{[re]}}sp), %xmm1
; CHECK: movaps 32(%{{[re]}}sp), %xmm2
; CHECK: movaps 48(%{{[re]}}sp), %xmm3
; CHECK-DAG: movaps (%{{.*}}), %xmm0
; CHECK-DAG: movaps 16(%{{.*}}), %xmm1
; CHECK-DAG: movaps 32(%{{.*}}), %xmm2
; CHECK-DAG: movaps 48(%{{.*}}), %xmm3
; CHECK: ret{{[ql]}}
entry:
%retval = alloca %struct.HVA4, align 16