From a996f2a8db5c19cf9f22de787089cf08772a6391 Mon Sep 17 00:00:00 2001
From: Kewen Meng <Kewen.Meng@amd.com>
Date: Fri, 27 Mar 2026 11:33:01 -0700
Subject: [PATCH] Revert "AMDGPU: Fold frame indexes into disjoint s_or_b32"
 (#189074)

Reverts llvm/llvm-project#102345

unblock bot: https://lab.llvm.org/buildbot/#/builders/10/builds/25403
---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp     |   8 +-
 .../eliminate-frame-index-scalar-bit-ops.mir  | 161 -------------
 .../AMDGPU/frame-index-disjoint-s-or-b32.ll   | 220 ------------------
 3 files changed, 2 insertions(+), 387 deletions(-)
 delete mode 100644 llvm/test/CodeGen/AMDGPU/frame-index-disjoint-s-or-b32.ll

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 3d5b7da2a738..e00ce4f167c3 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2807,12 +2807,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       return true;
     }
     case AMDGPU::S_ADD_I32:
-    case AMDGPU::S_ADD_U32:
-    case AMDGPU::S_OR_B32: {
-      if (MI->getOpcode() == AMDGPU::S_OR_B32 &&
-          !MI->getFlag(MachineInstr::Disjoint))
-        break;
-
+    case AMDGPU::S_ADD_U32: {
+      // TODO: Handle s_or_b32, s_and_b32.
       unsigned OtherOpIdx = FIOperandNum == 1 ? 2 : 1;
       MachineOperand &OtherOp = MI->getOperand(OtherOpIdx);
 
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
index cde131fdfe67..aecff1b13171 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
@@ -174,167 +174,6 @@ body:             |
 
 ...
 
----
-name: s_or_b32_disjoint__inline_imm__fi_offset0
-tracksRegLiveness: true
-stack:
-  - { id: 0, size: 32, alignment: 16 }
-machineFunctionInfo:
-  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
-  frameOffsetReg:  '$sgpr33'
-  stackPtrOffsetReg: '$sgpr32'
-body:             |
-  bb.0:
-    ; MUBUFW64-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
-    ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
-    ; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr4, implicit-def $scc
-    ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; MUBUFW32-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
-    ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
-    ; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr4, implicit-def $scc
-    ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW64-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
-    ; FLATSCRW64: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr32, implicit-def $scc
-    ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW32-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
-    ; FLATSCRW32: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr32, implicit-def $scc
-    ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    renamable $sgpr7 = disjoint S_OR_B32 12, %stack.0, implicit-def $scc
-    SI_RETURN implicit $sgpr7, implicit $scc
-
-...
-
----
-name: s_or_b32_disjoint__literal__fi_offset96
-tracksRegLiveness: true
-stack:
-  - { id: 0, size: 96, alignment: 16 }
-  - { id: 1, size: 24, alignment: 4 }
-machineFunctionInfo:
-  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
-  frameOffsetReg:  '$sgpr33'
-  stackPtrOffsetReg: '$sgpr32'
-body:             |
-  bb.0:
-    ; MUBUFW64-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
-    ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
-    ; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr4, implicit-def $scc
-    ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; MUBUFW32-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
-    ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
-    ; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr4, implicit-def $scc
-    ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW64-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
-    ; FLATSCRW64: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr32, implicit-def $scc
-    ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW32-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
-    ; FLATSCRW32: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr32, implicit-def $scc
-    ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    renamable $sgpr7 = disjoint S_OR_B32 68, %stack.1, implicit-def $scc
-    SI_RETURN implicit $sgpr7, implicit $scc
-
-...
-
----
-name: s_or_b32_disjoint__sgpr__fi_literal_offset
-tracksRegLiveness: true
-stack:
-  - { id: 0, size: 80, alignment: 16 }
-  - { id: 1, size: 48, alignment: 4 }
-machineFunctionInfo:
-  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
-  frameOffsetReg:  '$sgpr33'
-  stackPtrOffsetReg: '$sgpr32'
-body:             |
-  bb.0:
-    liveins: $sgpr8
-    ; MUBUFW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
-    ; MUBUFW64: liveins: $sgpr8
-    ; MUBUFW64-NEXT: {{  $}}
-    ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
-    ; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
-    ; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
-    ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; MUBUFW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
-    ; MUBUFW32: liveins: $sgpr8
-    ; MUBUFW32-NEXT: {{  $}}
-    ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
-    ; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
-    ; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
-    ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
-    ; FLATSCRW64: liveins: $sgpr8
-    ; FLATSCRW64-NEXT: {{  $}}
-    ; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
-    ; FLATSCRW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
-    ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
-    ; FLATSCRW32: liveins: $sgpr8
-    ; FLATSCRW32-NEXT: {{  $}}
-    ; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
-    ; FLATSCRW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
-    ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    renamable $sgpr7 = disjoint S_OR_B32 $sgpr8, %stack.1, implicit-def $scc
-    SI_RETURN implicit $sgpr7, implicit $scc
-
-...
-
----
-name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
-tracksRegLiveness: true
-stack:
-  - { id: 0, size: 32, alignment: 16 }
-  - { id: 1, size: 48, alignment: 4 }
-machineFunctionInfo:
-  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
-  frameOffsetReg:  '$sgpr33'
-  stackPtrOffsetReg: '$sgpr32'
-body:             |
-  bb.0:
-    liveins: $sgpr8
-    ; MUBUFW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
-    ; MUBUFW64: liveins: $sgpr8
-    ; MUBUFW64-NEXT: {{  $}}
-    ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
-    ; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
-    ; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
-    ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; MUBUFW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
-    ; MUBUFW32: liveins: $sgpr8
-    ; MUBUFW32-NEXT: {{  $}}
-    ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
-    ; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
-    ; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
-    ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
-    ; FLATSCRW64: liveins: $sgpr8
-    ; FLATSCRW64-NEXT: {{  $}}
-    ; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
-    ; FLATSCRW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
-    ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    ;
-    ; FLATSCRW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
-    ; FLATSCRW32: liveins: $sgpr8
-    ; FLATSCRW32-NEXT: {{  $}}
-    ; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
-    ; FLATSCRW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
-    ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
-    renamable $sgpr7 = disjoint S_OR_B32 $sgpr8, %stack.1, implicit-def $scc
-    SI_RETURN implicit $sgpr7, implicit $scc
-
-...
-
 ---
 name: s_and_b32__sgpr__fi_literal_offset
 tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-disjoint-s-or-b32.ll b/llvm/test/CodeGen/AMDGPU/frame-index-disjoint-s-or-b32.ll
deleted file mode 100644
index 39b1485959a3..000000000000
--- a/llvm/test/CodeGen/AMDGPU/frame-index-disjoint-s-or-b32.ll
+++ /dev/null
@@ -1,220 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX940 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
-
-
-define void @s_add_use_fi_sgpr_offset(i32 inreg %soffset) #0 {
-; GFX7-LABEL: s_add_use_fi_sgpr_offset:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    s_mov_b32 s7, s33
-; GFX7-NEXT:    s_add_i32 s33, s32, 0x7c0
-; GFX7-NEXT:    s_and_b32 s33, s33, 0xfffff800
-; GFX7-NEXT:    s_mov_b32 s8, s34
-; GFX7-NEXT:    s_mov_b32 s34, s32
-; GFX7-NEXT:    s_add_i32 s32, s32, 0x45000
-; GFX7-NEXT:    s_and_b32 s4, s16, 31
-; GFX7-NEXT:    s_lshr_b32 s5, s33, 6
-; GFX7-NEXT:    s_addk_i32 s5, 0x120
-; GFX7-NEXT:    s_lshr_b32 s6, s33, 6
-; GFX7-NEXT:    s_add_i32 s6, s6, 16
-; GFX7-NEXT:    ;;#ASMSTART
-; GFX7-NEXT:    ; use s5
-; GFX7-NEXT:    ;;#ASMEND
-; GFX7-NEXT:    s_lshr_b32 s5, s33, 6
-; GFX7-NEXT:    s_or_b32 s4, s5, s4
-; GFX7-NEXT:    s_addk_i32 s4, 0x120
-; GFX7-NEXT:    ;;#ASMSTART
-; GFX7-NEXT:    ; use s4
-; GFX7-NEXT:    ;;#ASMEND
-; GFX7-NEXT:    s_mov_b32 s32, s34
-; GFX7-NEXT:    s_mov_b32 s34, s8
-; GFX7-NEXT:    s_mov_b32 s33, s7
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: s_add_use_fi_sgpr_offset:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s7, s33
-; GFX8-NEXT:    s_add_i32 s33, s32, 0x7c0
-; GFX8-NEXT:    s_and_b32 s33, s33, 0xfffff800
-; GFX8-NEXT:    s_mov_b32 s8, s34
-; GFX8-NEXT:    s_mov_b32 s34, s32
-; GFX8-NEXT:    s_add_i32 s32, s32, 0x45000
-; GFX8-NEXT:    s_and_b32 s4, s16, 31
-; GFX8-NEXT:    s_lshr_b32 s5, s33, 6
-; GFX8-NEXT:    s_addk_i32 s5, 0x120
-; GFX8-NEXT:    s_lshr_b32 s6, s33, 6
-; GFX8-NEXT:    s_add_i32 s6, s6, 16
-; GFX8-NEXT:    ;;#ASMSTART
-; GFX8-NEXT:    ; use s5
-; GFX8-NEXT:    ;;#ASMEND
-; GFX8-NEXT:    s_lshr_b32 s5, s33, 6
-; GFX8-NEXT:    s_or_b32 s4, s5, s4
-; GFX8-NEXT:    s_addk_i32 s4, 0x120
-; GFX8-NEXT:    ;;#ASMSTART
-; GFX8-NEXT:    ; use s4
-; GFX8-NEXT:    ;;#ASMEND
-; GFX8-NEXT:    s_mov_b32 s32, s34
-; GFX8-NEXT:    s_mov_b32 s34, s8
-; GFX8-NEXT:    s_mov_b32 s33, s7
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX900-LABEL: s_add_use_fi_sgpr_offset:
-; GFX900:       ; %bb.0:
-; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT:    s_mov_b32 s7, s33
-; GFX900-NEXT:    s_add_i32 s33, s32, 0x7c0
-; GFX900-NEXT:    s_and_b32 s33, s33, 0xfffff800
-; GFX900-NEXT:    s_mov_b32 s8, s34
-; GFX900-NEXT:    s_mov_b32 s34, s32
-; GFX900-NEXT:    s_add_i32 s32, s32, 0x45000
-; GFX900-NEXT:    s_and_b32 s4, s16, 31
-; GFX900-NEXT:    s_lshr_b32 s5, s33, 6
-; GFX900-NEXT:    s_addk_i32 s5, 0x120
-; GFX900-NEXT:    s_lshr_b32 s6, s33, 6
-; GFX900-NEXT:    s_add_i32 s6, s6, 16
-; GFX900-NEXT:    ;;#ASMSTART
-; GFX900-NEXT:    ; use s5
-; GFX900-NEXT:    ;;#ASMEND
-; GFX900-NEXT:    s_lshr_b32 s5, s33, 6
-; GFX900-NEXT:    s_or_b32 s4, s5, s4
-; GFX900-NEXT:    s_addk_i32 s4, 0x120
-; GFX900-NEXT:    ;;#ASMSTART
-; GFX900-NEXT:    ; use s4
-; GFX900-NEXT:    ;;#ASMEND
-; GFX900-NEXT:    s_mov_b32 s32, s34
-; GFX900-NEXT:    s_mov_b32 s34, s8
-; GFX900-NEXT:    s_mov_b32 s33, s7
-; GFX900-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: s_add_use_fi_sgpr_offset:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_mov_b32 s7, s33
-; GFX10-NEXT:    s_add_i32 s33, s32, 0x3e0
-; GFX10-NEXT:    s_mov_b32 s8, s34
-; GFX10-NEXT:    s_and_b32 s33, s33, 0xfffffc00
-; GFX10-NEXT:    s_mov_b32 s34, s32
-; GFX10-NEXT:    s_add_i32 s32, s32, 0x22800
-; GFX10-NEXT:    s_and_b32 s4, s16, 31
-; GFX10-NEXT:    s_lshr_b32 s5, s33, 5
-; GFX10-NEXT:    s_mov_b32 s32, s34
-; GFX10-NEXT:    s_addk_i32 s5, 0x120
-; GFX10-NEXT:    s_lshr_b32 s6, s33, 5
-; GFX10-NEXT:    s_mov_b32 s34, s8
-; GFX10-NEXT:    s_add_i32 s6, s6, 16
-; GFX10-NEXT:    s_lshr_b32 s9, s33, 5
-; GFX10-NEXT:    ;;#ASMSTART
-; GFX10-NEXT:    ; use s5
-; GFX10-NEXT:    ;;#ASMEND
-; GFX10-NEXT:    s_or_b32 s4, s9, s4
-; GFX10-NEXT:    s_mov_b32 s33, s7
-; GFX10-NEXT:    s_addk_i32 s4, 0x120
-; GFX10-NEXT:    ;;#ASMSTART
-; GFX10-NEXT:    ; use s4
-; GFX10-NEXT:    ;;#ASMEND
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX940-LABEL: s_add_use_fi_sgpr_offset:
-; GFX940:       ; %bb.0:
-; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX940-NEXT:    s_mov_b32 s3, s33
-; GFX940-NEXT:    s_add_i32 s33, s32, 31
-; GFX940-NEXT:    s_andn2_b32 s33, s33, 31
-; GFX940-NEXT:    s_mov_b32 s4, s34
-; GFX940-NEXT:    s_mov_b32 s34, s32
-; GFX940-NEXT:    s_addk_i32 s32, 0x1140
-; GFX940-NEXT:    s_and_b32 s0, s0, 31
-; GFX940-NEXT:    s_add_i32 s2, s33, 0x120
-; GFX940-NEXT:    s_mov_b32 s1, s2
-; GFX940-NEXT:    s_add_i32 s5, s33, 16
-; GFX940-NEXT:    s_mov_b32 s2, s5
-; GFX940-NEXT:    ;;#ASMSTART
-; GFX940-NEXT:    ; use s1
-; GFX940-NEXT:    ;;#ASMEND
-; GFX940-NEXT:    s_or_b32 s1, s33, s0
-; GFX940-NEXT:    s_or_b32 s0, s1, 0x120
-; GFX940-NEXT:    ;;#ASMSTART
-; GFX940-NEXT:    ; use s0
-; GFX940-NEXT:    ;;#ASMEND
-; GFX940-NEXT:    s_mov_b32 s32, s34
-; GFX940-NEXT:    s_mov_b32 s34, s4
-; GFX940-NEXT:    s_mov_b32 s33, s3
-; GFX940-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: s_add_use_fi_sgpr_offset:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s3, s33
-; GFX11-NEXT:    s_add_i32 s33, s32, 31
-; GFX11-NEXT:    s_mov_b32 s4, s34
-; GFX11-NEXT:    s_and_not1_b32 s33, s33, 31
-; GFX11-NEXT:    s_mov_b32 s34, s32
-; GFX11-NEXT:    s_addk_i32 s32, 0x1140
-; GFX11-NEXT:    s_and_b32 s0, s0, 31
-; GFX11-NEXT:    s_add_i32 s2, s33, 0x120
-; GFX11-NEXT:    s_add_i32 s5, s33, 16
-; GFX11-NEXT:    s_mov_b32 s1, s2
-; GFX11-NEXT:    s_mov_b32 s2, s5
-; GFX11-NEXT:    s_or_b32 s5, s33, s0
-; GFX11-NEXT:    ;;#ASMSTART
-; GFX11-NEXT:    ; use s1
-; GFX11-NEXT:    ;;#ASMEND
-; GFX11-NEXT:    s_or_b32 s0, s5, 0x120
-; GFX11-NEXT:    ;;#ASMSTART
-; GFX11-NEXT:    ; use s0
-; GFX11-NEXT:    ;;#ASMEND
-; GFX11-NEXT:    s_mov_b32 s32, s34
-; GFX11-NEXT:    s_mov_b32 s34, s4
-; GFX11-NEXT:    s_mov_b32 s33, s3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: s_add_use_fi_sgpr_offset:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s3, s33
-; GFX12-NEXT:    s_add_co_i32 s33, s32, 31
-; GFX12-NEXT:    s_mov_b32 s4, s34
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_and_not1_b32 s33, s33, 31
-; GFX12-NEXT:    s_mov_b32 s34, s32
-; GFX12-NEXT:    s_addk_co_i32 s32, 0x1140
-; GFX12-NEXT:    s_and_b32 s0, s0, 31
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_add_co_i32 s2, s33, 0x100
-; GFX12-NEXT:    s_or_b32 s5, s33, s0
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_mov_b32 s1, s2
-; GFX12-NEXT:    s_mov_b32 s2, s33
-; GFX12-NEXT:    s_or_b32 s0, s5, 0x100
-; GFX12-NEXT:    ;;#ASMSTART
-; GFX12-NEXT:    ; use s1
-; GFX12-NEXT:    ;;#ASMEND
-; GFX12-NEXT:    ;;#ASMSTART
-; GFX12-NEXT:    ; use s0
-; GFX12-NEXT:    ;;#ASMEND
-; GFX12-NEXT:    s_mov_b32 s32, s34
-; GFX12-NEXT:    s_mov_b32 s34, s4
-; GFX12-NEXT:    s_mov_b32 s33, s3
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
-  %filler = alloca [256 x i8], align 16, addrspace(5)
-  %alloca = alloca [4096 x i8], align 32, addrspace(5)
-
-  %soffset.and = and i32 %soffset, 31
-
-  call void asm sideeffect "; use $0", "s,s"(ptr addrspace(5) %alloca, ptr addrspace(5) %filler)
-  %gep = getelementptr inbounds nuw [4096 x i8], ptr addrspace(5) %alloca, i32 0, i32 %soffset.and
-  call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %gep)
-  ret void
-}