shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

[ARM] [AArch32] Add support for Arm China STAR-MC3 CPU (#163709)

Browse Source 
STAR-MC3 is an Armv8.1m CPU.
Technical specificationa available at:
https://www.armchina.com/download/Documents/TRM?infoId=240
This commit is contained in:
Albert Huang 2025-10-27 16:55:28 +08:00 committed by GitHub
parent e86a42940a
commit aa550cdc5f
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
7 changed files with 28 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
clang/test/CodeGen/arm-target-features.c
View File

@ -116,6 +116,9 @@
// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
// CHECK-ARMV81M-CORTEX-M52-LINUX: "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu star-mc3 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-STAR-MC3-LINUX
// CHECK-ARMV81M-STAR-MC3-LINUX: "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
// RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARCH93
// CHECK-ARCH93: "target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"

3
clang/test/Driver/arm-cortex-cpus-2.c
View File

@ -585,6 +585,9 @@
// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M52 %s
// CHECK-CORTEX-M52: "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} "-target-cpu" "cortex-m52"
// RUN: %clang -target arm -mcpu=star-mc3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-STAR-MC3 %s
// CHECK-STAR-MC3: "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} "-target-cpu" "star-mc3"
// RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NEOVERSE-N2 %s
// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv9a-{{.*}}" "-target-cpu" "neoverse-n2"

1
clang/test/Misc/target-invalid-cpu-note/arm.c
View File

@ -70,6 +70,7 @@
// CHECK-SAME: {{^}}, cortex-m55
// CHECK-SAME: {{^}}, cortex-m85
// CHECK-SAME: {{^}}, cortex-m52
// CHECK-SAME: {{^}}, star-mc3
// CHECK-SAME: {{^}}, cortex-a32
// CHECK-SAME: {{^}}, cortex-a35
// CHECK-SAME: {{^}}, cortex-a53

3
llvm/include/llvm/TargetParser/ARMTargetParser.def
View File

@ -357,6 +357,9 @@ ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("star-mc3", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)

11
llvm/lib/Target/ARM/ARMProcessors.td
View File

@ -421,6 +421,17 @@ def : ProcessorModel<"cortex-m52", CortexM55Model, [ARMv81mMainline,
FeatureMVEVectorCostFactor1,
HasMVEFloatOps]>;
def : ProcessorModel<"star-mc3", CortexM55Model, [ARMv81mMainline,
FeatureDSP,
FeatureFPARMv8_D16,
FeatureHasNoBranchPredictor,
FeaturePACBTI,
FeatureUseMISched,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureMVEVectorCostFactor1,
HasMVEFloatOps]>;
def : ProcNoItin<"cortex-a32", [ARMv8a,
FeatureHWDivThumb,
FeatureHWDivARM,

1
llvm/lib/TargetParser/Host.cpp
View File

@ -369,6 +369,7 @@ getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware,
if (Implementer == "0x63") { // Arm China.
return StringSwitch<const char *>(Part)
.Case("0x132", "star-mc1")
.Case("0xd25", "star-mc3")
.Default("generic");
}

7
llvm/unittests/TargetParser/TargetParserTest.cpp
View File

@ -518,6 +518,11 @@ INSTANTIATE_TEST_SUITE_P(
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP |
ARM::AEK_RAS | ARM::AEK_LOB | ARM::AEK_FP16 | ARM::AEK_PACBTI,
"8.1-M.Mainline"),
ARMCPUTestParams<uint64_t>(
"star-mc3", "armv8.1-m.main", "fp-armv8-fullfp16-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP |
ARM::AEK_RAS | ARM::AEK_LOB | ARM::AEK_FP16 | ARM::AEK_PACBTI,
"8.1-M.Mainline"),
ARMCPUTestParams<uint64_t>("iwmmxt", "iwmmxt", "none", ARM::AEK_NONE,
"iwmmxt"),
ARMCPUTestParams<uint64_t>("xscale", "xscale", "none", ARM::AEK_NONE,
@ -528,7 +533,7 @@ INSTANTIATE_TEST_SUITE_P(
"7-S")),
ARMCPUTestParams<uint64_t>::PrintToStringParamName);
static constexpr unsigned NumARMCPUArchs = 94;
static constexpr unsigned NumARMCPUArchs = 95;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;