diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index 2649339e54a6..a259eac08a19 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -607,6 +607,21 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}); + addRulesForGOpcs({G_BSWAP}, Standard) + .Uni(S16, {{UniInVgprS16}, {Vgpr16}}) + .Div(S16, {{Vgpr16}, {Vgpr16}}) + .Uni(S32, {{UniInVgprS32}, {Vgpr32}}) + .Div(S32, {{Vgpr32}, {Vgpr32}}) + .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16}}) + .Div(V2S16, {{VgprV2S16}, {VgprV2S16}}); + + addRulesForGOpcs({G_AMDGPU_CVT_F32_UBYTE0, G_AMDGPU_CVT_F32_UBYTE1, + G_AMDGPU_CVT_F32_UBYTE2, G_AMDGPU_CVT_F32_UBYTE3, + G_AMDGPU_RCP_IFLAG}, + Standard) + .Uni(S32, {{UniInVgprS32}, {Vgpr32}}) + .Div(S32, {{Vgpr32}, {Vgpr32}}); + addRulesForGOpcs({G_FRAME_INDEX}).Any({{UniP5, _}, {{SgprP5}, {None}}}); addRulesForGOpcs({G_UBFX, G_SBFX}, Standard) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll index 57755c685685..32df44cb2f84 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -o - %s | FileCheck -check-prefix=GFX7 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -o - %s | FileCheck -check-prefix=GFX7 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX10 %s define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) { ; GFX7-LABEL: s_bswap_i32: @@ -449,15 +449,15 @@ define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_lshr_b32 s1, s0, 16 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-NEXT: v_alignbit_b32 v0, s1, v0, 24 ; GFX7-NEXT: s_lshl_b32 s2, s0, 8 ; GFX7-NEXT: s_bfe_u32 s3, s0, 0x80008 -; GFX7-NEXT: v_alignbit_b32 v0, s1, v0, 24 -; GFX7-NEXT: s_or_b32 s2, s3, s2 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: s_and_b32 s0, 0xffff, s2 -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX7-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: s_or_b32 s2, s3, s2 +; GFX7-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX7-NEXT: s_and_b32 s1, 0xffff, s2 +; GFX7-NEXT: s_lshl_b32 s0, s0, 16 +; GFX7-NEXT: s_or_b32 s0, s1, s0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_bswap_v2i16: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll index 94b956ef254a..92fd4466cf8a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI %s -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone @@ -1434,32 +1434,34 @@ define float @v_test_sitofp_i64_byte_to_f32(i64 %arg0) { ; SI-LABEL: v_test_sitofp_i64_byte_to_f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_ffbh_i32_e32 v2, 0 -; SI-NEXT: v_add_i32_e32 v2, vcc, -1, v2 -; SI-NEXT: v_and_b32_e32 v0, 0xff, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: v_min_u32_e32 v2, 32, v2 -; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v2 +; SI-NEXT: v_mov_b32_e32 v1, 0xff +; SI-NEXT: v_mov_b32_e32 v2, 0 +; SI-NEXT: v_and_b32_e32 v1, 0xff, v0 +; SI-NEXT: v_ffbh_i32_e32 v0, 0 +; SI-NEXT: v_add_i32_e32 v0, vcc, -1, v0 +; SI-NEXT: v_min_u32_e32 v3, 32, v0 +; SI-NEXT: v_lshl_b64 v[0:1], v[1:2], v3 ; SI-NEXT: v_min_u32_e32 v0, 1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_cvt_f32_i32_e32 v0, v0 -; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v2 +; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v3 ; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: v_test_sitofp_i64_byte_to_f32: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_ffbh_i32_e32 v2, 0 -; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v2 -; VI-NEXT: v_and_b32_e32 v0, 0xff, v0 -; VI-NEXT: v_mov_b32_e32 v1, 0 -; VI-NEXT: v_min_u32_e32 v2, 32, v2 -; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1] +; VI-NEXT: v_mov_b32_e32 v1, 0xff +; VI-NEXT: v_mov_b32_e32 v2, 0 +; VI-NEXT: v_and_b32_e32 v1, 0xff, v0 +; VI-NEXT: v_ffbh_i32_e32 v0, 0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0 +; VI-NEXT: v_min_u32_e32 v3, 32, v0 +; VI-NEXT: v_lshlrev_b64 v[0:1], v3, v[1:2] ; VI-NEXT: v_min_u32_e32 v0, 1, v0 ; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_cvt_f32_i32_e32 v0, v0 -; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v2 +; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v3 ; VI-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-NEXT: s_setpc_b64 s[30:31] %masked = and i64 %arg0, 255 @@ -1471,30 +1473,32 @@ define float @v_test_uitofp_i64_byte_to_f32(i64 %arg0) { ; SI-LABEL: v_test_uitofp_i64_byte_to_f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_ffbh_u32_e32 v2, 0 -; SI-NEXT: v_and_b32_e32 v0, 0xff, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: v_min_u32_e32 v2, 32, v2 -; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v2 +; SI-NEXT: v_mov_b32_e32 v1, 0xff +; SI-NEXT: v_mov_b32_e32 v2, 0 +; SI-NEXT: v_and_b32_e32 v1, 0xff, v0 +; SI-NEXT: v_ffbh_u32_e32 v0, 0 +; SI-NEXT: v_min_u32_e32 v3, 32, v0 +; SI-NEXT: v_lshl_b64 v[0:1], v[1:2], v3 ; SI-NEXT: v_min_u32_e32 v0, 1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_cvt_f32_u32_e32 v0, v0 -; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v2 +; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v3 ; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: v_test_uitofp_i64_byte_to_f32: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_ffbh_u32_e32 v2, 0 -; VI-NEXT: v_and_b32_e32 v0, 0xff, v0 -; VI-NEXT: v_mov_b32_e32 v1, 0 -; VI-NEXT: v_min_u32_e32 v2, 32, v2 -; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1] +; VI-NEXT: v_mov_b32_e32 v1, 0xff +; VI-NEXT: v_mov_b32_e32 v2, 0 +; VI-NEXT: v_and_b32_e32 v1, 0xff, v0 +; VI-NEXT: v_ffbh_u32_e32 v0, 0 +; VI-NEXT: v_min_u32_e32 v3, 32, v0 +; VI-NEXT: v_lshlrev_b64 v[0:1], v3, v[1:2] ; VI-NEXT: v_min_u32_e32 v0, 1, v0 ; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_cvt_f32_u32_e32 v0, v0 -; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v2 +; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v3 ; VI-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-NEXT: s_setpc_b64 s[30:31] %masked = and i64 %arg0, 255 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll index bc6a2e7c4325..6b8fc8675e8a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11 %s define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) { ; GFX6-LABEL: s_fshr_i7: @@ -11,29 +11,34 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) { ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 7 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: s_and_b32 s2, s2, 0x7f -; GFX6-NEXT: s_lshl_b32 s0, s0, 1 -; GFX6-NEXT: s_and_b32 s1, s1, 0x7f ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: v_mul_lo_u32 v1, v0, -7 -; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_mul_i32 s4, s3, -7 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s4 +; GFX6-NEXT: v_readfirstlane_b32 s4, v0 +; GFX6-NEXT: s_add_i32 s3, s3, s4 +; GFX6-NEXT: v_mov_b32_e32 v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX6-NEXT: v_mul_lo_u32 v0, v0, 7 -; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, -7, v0 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v0 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX6-NEXT: v_add_i32_e32 v1, vcc, -7, v0 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v0 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 6, v0 -; GFX6-NEXT: v_and_b32_e32 v0, 0x7f, v0 -; GFX6-NEXT: v_and_b32_e32 v1, 0x7f, v1 -; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1 -; GFX6-NEXT: v_lshr_b32_e32 v0, s1, v0 -; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX6-NEXT: v_readfirstlane_b32 s0, v0 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_mul_i32 s3, s3, 7 +; GFX6-NEXT: s_sub_i32 s2, s2, s3 +; GFX6-NEXT: s_cmp_ge_u32 s2, 7 +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_add_i32 s4, s2, -7 +; GFX6-NEXT: s_cmp_lg_u32 s3, 0 +; GFX6-NEXT: s_cselect_b32 s2, s4, s2 +; GFX6-NEXT: s_cmp_ge_u32 s2, 7 +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_add_i32 s4, s2, -7 +; GFX6-NEXT: s_cmp_lg_u32 s3, 0 +; GFX6-NEXT: s_cselect_b32 s2, s4, s2 +; GFX6-NEXT: s_lshl_b32 s0, s0, 1 +; GFX6-NEXT: s_and_b32 s1, s1, 0x7f +; GFX6-NEXT: s_sub_i32 s3, 6, s2 +; GFX6-NEXT: s_lshl_b32 s0, s0, s3 +; GFX6-NEXT: s_lshr_b32 s1, s1, s2 +; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_fshr_i7: @@ -41,29 +46,37 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) { ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 7 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_and_b32 s2, s2, 0x7f -; GFX8-NEXT: s_lshl_b32 s0, s0, 1 -; GFX8-NEXT: s_and_b32 s1, s1, 0x7f ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX8-NEXT: v_mul_lo_u32 v1, v0, -7 -; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_readfirstlane_b32 s3, v0 +; GFX8-NEXT: s_mul_i32 s4, s3, -7 +; GFX8-NEXT: v_mul_hi_u32 v0, v0, s4 +; GFX8-NEXT: v_readfirstlane_b32 s4, v0 +; GFX8-NEXT: s_add_i32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 ; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX8-NEXT: v_mul_lo_u32 v0, v0, 7 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 -; GFX8-NEXT: v_add_u32_e32 v1, vcc, -7, v0 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_add_u32_e32 v1, vcc, -7, v0 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_sub_u16_e32 v1, 6, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0 -; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1 -; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0 -; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s1 -; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s3, v0 +; GFX8-NEXT: s_mul_i32 s3, s3, 7 +; GFX8-NEXT: s_sub_i32 s2, s2, s3 +; GFX8-NEXT: s_cmp_ge_u32 s2, 7 +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_add_i32 s4, s2, -7 +; GFX8-NEXT: s_cmp_lg_u32 s3, 0 +; GFX8-NEXT: s_cselect_b32 s2, s4, s2 +; GFX8-NEXT: s_cmp_ge_u32 s2, 7 +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_add_i32 s4, s2, -7 +; GFX8-NEXT: s_cmp_lg_u32 s3, 0 +; GFX8-NEXT: s_cselect_b32 s2, s4, s2 +; GFX8-NEXT: s_and_b32 s1, s1, 0x7f +; GFX8-NEXT: s_sub_i32 s3, 6, s2 +; GFX8-NEXT: s_lshl_b32 s0, s0, 1 +; GFX8-NEXT: s_and_b32 s2, s2, 0x7f +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX8-NEXT: s_and_b32 s3, s3, 0x7f +; GFX8-NEXT: s_lshl_b32 s0, s0, s3 +; GFX8-NEXT: s_lshr_b32 s1, s1, s2 +; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_fshr_i7: @@ -71,99 +84,111 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) { ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_and_b32 s2, s2, 0x7f -; GFX9-NEXT: s_lshl_b32 s0, s0, 1 -; GFX9-NEXT: s_and_b32 s1, s1, 0x7f ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_mul_lo_u32 v1, v0, -7 -; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 -; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX9-NEXT: v_mul_lo_u32 v0, v0, 7 -; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 -; GFX9-NEXT: v_add_u32_e32 v1, -7, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_add_u32_e32 v1, -7, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_sub_u16_e32 v1, 6, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0 -; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1 -; GFX9-NEXT: v_lshlrev_b16_e64 v1, v1, s0 -; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s1 -; GFX9-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s3, v0 +; GFX9-NEXT: s_mul_i32 s4, s3, -7 +; GFX9-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX9-NEXT: s_add_i32 s3, s3, s4 +; GFX9-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX9-NEXT: s_mul_i32 s3, s3, 7 +; GFX9-NEXT: s_sub_i32 s2, s2, s3 +; GFX9-NEXT: s_cmp_ge_u32 s2, 7 +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_add_i32 s4, s2, -7 +; GFX9-NEXT: s_cmp_lg_u32 s3, 0 +; GFX9-NEXT: s_cselect_b32 s2, s4, s2 +; GFX9-NEXT: s_cmp_ge_u32 s2, 7 +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_add_i32 s4, s2, -7 +; GFX9-NEXT: s_cmp_lg_u32 s3, 0 +; GFX9-NEXT: s_cselect_b32 s2, s4, s2 +; GFX9-NEXT: s_sub_i32 s3, 6, s2 +; GFX9-NEXT: s_and_b32 s1, s1, 0x7f +; GFX9-NEXT: s_lshl_b32 s0, s0, 1 +; GFX9-NEXT: s_and_b32 s3, s3, 0x7f +; GFX9-NEXT: s_and_b32 s2, s2, 0x7f +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX9-NEXT: s_lshl_b32 s0, s0, s3 +; GFX9-NEXT: s_lshr_b32 s1, s1, s2 +; GFX9-NEXT: s_or_b32 s0, s0, s1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_fshr_i7: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 7 ; GFX10-NEXT: s_and_b32 s2, s2, 0x7f -; GFX10-NEXT: s_lshl_b32 s0, s0, 1 -; GFX10-NEXT: s_and_b32 s1, s1, 0x7f ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_lo_u32 v1, v0, -7 -; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 -; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX10-NEXT: v_mul_lo_u32 v0, v0, 7 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v1, -7, v0 -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_add_nc_u32_e32 v1, -7, v0 -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_sub_nc_u16 v1, 6, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 0x7f, v0 -; GFX10-NEXT: v_and_b32_e32 v1, 0x7f, v1 -; GFX10-NEXT: v_lshrrev_b16 v0, v0, s1 -; GFX10-NEXT: v_lshlrev_b16 v1, v1, s0 -; GFX10-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s3, v0 +; GFX10-NEXT: s_mul_i32 s4, s3, -7 +; GFX10-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX10-NEXT: s_add_i32 s3, s3, s4 +; GFX10-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX10-NEXT: s_mul_i32 s3, s3, 7 +; GFX10-NEXT: s_sub_i32 s2, s2, s3 +; GFX10-NEXT: s_cmp_ge_u32 s2, 7 +; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_add_i32 s4, s2, -7 +; GFX10-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10-NEXT: s_cselect_b32 s2, s4, s2 +; GFX10-NEXT: s_cmp_ge_u32 s2, 7 +; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_add_i32 s4, s2, -7 +; GFX10-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10-NEXT: s_cselect_b32 s2, s4, s2 +; GFX10-NEXT: s_and_b32 s1, s1, 0x7f +; GFX10-NEXT: s_sub_i32 s3, 6, s2 +; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_and_b32 s2, s2, 0x7f +; GFX10-NEXT: s_and_b32 s3, s3, 0x7f +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX10-NEXT: s_lshl_b32 s0, s0, s3 +; GFX10-NEXT: s_lshr_b32 s1, s1, s2 +; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: s_fshr_i7: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 7 ; GFX11-NEXT: s_and_b32 s2, s2, 0x7f -; GFX11-NEXT: s_lshl_b32 s0, s0, 1 -; GFX11-NEXT: s_and_b32 s1, s1, 0x7f ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_lo_u32 v1, v0, -7 -; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1 -; GFX11-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_lo_u32 v0, v0, 7 -; GFX11-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_nc_u32_e32 v1, -7, v0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_nc_u32_e32 v1, -7, v0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_sub_nc_u16 v1, 6, v0 -; GFX11-NEXT: v_and_b32_e32 v0, 0x7f, v0 -; GFX11-NEXT: v_and_b32_e32 v1, 0x7f, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_lshrrev_b16 v0, v0, s1 -; GFX11-NEXT: v_lshlrev_b16 v1, v1, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s3, v0 +; GFX11-NEXT: s_mul_i32 s4, s3, -7 +; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s3, s3, s4 +; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_i32 s3, s3, 7 +; GFX11-NEXT: s_sub_i32 s2, s2, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_ge_u32 s2, 7 +; GFX11-NEXT: s_cselect_b32 s3, 1, 0 +; GFX11-NEXT: s_add_i32 s4, s2, -7 +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: s_cselect_b32 s2, s4, s2 +; GFX11-NEXT: s_cmp_ge_u32 s2, 7 +; GFX11-NEXT: s_cselect_b32 s3, 1, 0 +; GFX11-NEXT: s_add_i32 s4, s2, -7 +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: s_cselect_b32 s2, s4, s2 +; GFX11-NEXT: s_and_b32 s1, s1, 0x7f +; GFX11-NEXT: s_sub_i32 s3, 6, s2 +; GFX11-NEXT: s_lshl_b32 s0, s0, 1 +; GFX11-NEXT: s_and_b32 s2, s2, 0x7f +; GFX11-NEXT: s_and_b32 s3, s3, 0x7f +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s3 +; GFX11-NEXT: s_lshr_b32 s1, s1, s2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt) ret i7 %result @@ -180,10 +205,12 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX6-NEXT: v_and_b32_e32 v1, 0x7f, v1 ; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX6-NEXT: v_mul_lo_u32 v4, v3, -7 -; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX6-NEXT: v_readfirstlane_b32 s4, v3 +; GFX6-NEXT: s_mul_i32 s5, s4, -7 +; GFX6-NEXT: v_mul_hi_u32 v3, v3, s5 +; GFX6-NEXT: v_readfirstlane_b32 s5, v3 +; GFX6-NEXT: s_add_i32 s4, s4, s5 +; GFX6-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, 7 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, -7, v2 @@ -210,10 +237,12 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1 ; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX8-NEXT: v_mul_lo_u32 v4, v3, -7 -; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4 -; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v3 +; GFX8-NEXT: s_mul_i32 s5, s4, -7 +; GFX8-NEXT: v_mul_hi_u32 v3, v3, s5 +; GFX8-NEXT: v_readfirstlane_b32 s5, v3 +; GFX8-NEXT: s_add_i32 s4, s4, s5 +; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX8-NEXT: v_mul_lo_u32 v3, v3, 7 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, -7, v2 @@ -240,10 +269,11 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1 ; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX9-NEXT: v_mul_lo_u32 v4, v3, -7 -; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v3 +; GFX9-NEXT: s_mul_i32 s5, s4, -7 +; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX9-NEXT: s_add_i32 s4, s4, s5 +; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, 7 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v3, -7, v2 @@ -270,10 +300,11 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX10-NEXT: v_mul_lo_u32 v4, v3, -7 -; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4 -; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v3 +; GFX10-NEXT: s_mul_i32 s5, s4, -7 +; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX10-NEXT: s_add_i32 s4, s4, s5 +; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX10-NEXT: v_mul_lo_u32 v3, v3, 7 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, -7, v2 @@ -302,12 +333,13 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) ; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_lo_u32 v4, v3, -7 -; GFX11-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4 -; GFX11-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s0, v3 +; GFX11-NEXT: s_mul_i32 s1, s0, -7 +; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s0, s0, s1 +; GFX11-NEXT: v_mul_hi_u32 v3, v2, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_lo_u32 v3, v3, 7 ; GFX11-NEXT: v_sub_nc_u32_e32 v2, v2, v3 @@ -347,10 +379,11 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) { ; ; GFX8-LABEL: s_fshr_i8: ; GFX8: ; %bb.0: +; GFX8-NEXT: s_and_b32 s1, s1, 0xff ; GFX8-NEXT: s_lshl_b32 s0, s0, 1 ; GFX8-NEXT: s_andn2_b32 s3, 7, s2 ; GFX8-NEXT: s_and_b32 s2, s2, 7 -; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_lshl_b32 s0, s0, s3 ; GFX8-NEXT: s_lshr_b32 s1, s1, s2 ; GFX8-NEXT: s_or_b32 s0, s0, s1 @@ -358,10 +391,11 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) { ; ; GFX9-LABEL: s_fshr_i8: ; GFX9: ; %bb.0: +; GFX9-NEXT: s_and_b32 s1, s1, 0xff ; GFX9-NEXT: s_lshl_b32 s0, s0, 1 ; GFX9-NEXT: s_andn2_b32 s3, 7, s2 ; GFX9-NEXT: s_and_b32 s2, s2, 7 -; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX9-NEXT: s_lshl_b32 s0, s0, s3 ; GFX9-NEXT: s_lshr_b32 s1, s1, s2 ; GFX9-NEXT: s_or_b32 s0, s0, s1 @@ -369,10 +403,11 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) { ; ; GFX10-LABEL: s_fshr_i8: ; GFX10: ; %bb.0: +; GFX10-NEXT: s_and_b32 s1, s1, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, 1 ; GFX10-NEXT: s_andn2_b32 s3, 7, s2 ; GFX10-NEXT: s_and_b32 s2, s2, 7 -; GFX10-NEXT: s_and_b32 s1, s1, 0xff +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX10-NEXT: s_lshl_b32 s0, s0, s3 ; GFX10-NEXT: s_lshr_b32 s1, s1, s2 ; GFX10-NEXT: s_or_b32 s0, s0, s1 @@ -380,10 +415,11 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) { ; ; GFX11-LABEL: s_fshr_i8: ; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_and_not1_b32 s3, 7, s2 ; GFX11-NEXT: s_and_b32 s2, s2, 7 -; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX11-NEXT: s_lshl_b32 s0, s0, s3 ; GFX11-NEXT: s_lshr_b32 s1, s1, s2 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -472,6 +508,7 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) { ; GFX8-LABEL: s_fshr_i8_4: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_lshl_b32 s0, s0, 4 ; GFX8-NEXT: s_lshr_b32 s1, s1, 4 ; GFX8-NEXT: s_or_b32 s0, s0, s1 @@ -480,6 +517,7 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) { ; GFX9-LABEL: s_fshr_i8_4: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX9-NEXT: s_lshl_b32 s0, s0, 4 ; GFX9-NEXT: s_lshr_b32 s1, s1, 4 ; GFX9-NEXT: s_or_b32 s0, s0, s1 @@ -489,6 +527,7 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_and_b32 s1, s1, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, 4 +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX10-NEXT: s_lshr_b32 s1, s1, 4 ; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: ; return to shader part epilog @@ -497,8 +536,9 @@ define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) { ; GFX11: ; %bb.0: ; GFX11-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_lshr_b32 s1, s1, 4 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4) @@ -565,6 +605,7 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) { ; GFX8-LABEL: s_fshr_i8_5: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_lshl_b32 s0, s0, 3 ; GFX8-NEXT: s_lshr_b32 s1, s1, 5 ; GFX8-NEXT: s_or_b32 s0, s0, s1 @@ -573,6 +614,7 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) { ; GFX9-LABEL: s_fshr_i8_5: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX9-NEXT: s_lshl_b32 s0, s0, 3 ; GFX9-NEXT: s_lshr_b32 s1, s1, 5 ; GFX9-NEXT: s_or_b32 s0, s0, s1 @@ -582,6 +624,7 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_and_b32 s1, s1, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, 3 +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX10-NEXT: s_lshr_b32 s1, s1, 5 ; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: ; return to shader part epilog @@ -590,8 +633,9 @@ define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) { ; GFX11: ; %bb.0: ; GFX11-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_lshr_b32 s1, s1, 5 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5) @@ -674,21 +718,23 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; ; GFX8-LABEL: s_fshr_v2i8: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_lshr_b32 s3, s0, 8 ; GFX8-NEXT: s_lshr_b32 s4, s1, 8 +; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_lshr_b32 s3, s0, 8 ; GFX8-NEXT: s_lshr_b32 s5, s2, 8 ; GFX8-NEXT: s_lshl_b32 s0, s0, 1 ; GFX8-NEXT: s_andn2_b32 s6, 7, s2 ; GFX8-NEXT: s_and_b32 s2, s2, 7 -; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_lshl_b32 s0, s0, s6 ; GFX8-NEXT: s_lshr_b32 s1, s1, s2 ; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_lshl_b32 s1, s3, 1 ; GFX8-NEXT: s_andn2_b32 s2, 7, s5 +; GFX8-NEXT: s_and_b32 s3, s4, 0xff ; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s2, s5, 7 -; GFX8-NEXT: s_and_b32 s3, s4, 0xff +; GFX8-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX8-NEXT: s_lshr_b32 s2, s3, s2 ; GFX8-NEXT: s_or_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s1, s1, 0xff @@ -699,21 +745,23 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; ; GFX9-LABEL: s_fshr_v2i8: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_lshr_b32 s3, s0, 8 ; GFX9-NEXT: s_lshr_b32 s4, s1, 8 +; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_lshr_b32 s3, s0, 8 ; GFX9-NEXT: s_lshr_b32 s5, s2, 8 ; GFX9-NEXT: s_lshl_b32 s0, s0, 1 ; GFX9-NEXT: s_andn2_b32 s6, 7, s2 ; GFX9-NEXT: s_and_b32 s2, s2, 7 -; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX9-NEXT: s_lshl_b32 s0, s0, s6 ; GFX9-NEXT: s_lshr_b32 s1, s1, s2 ; GFX9-NEXT: s_or_b32 s0, s0, s1 ; GFX9-NEXT: s_lshl_b32 s1, s3, 1 ; GFX9-NEXT: s_andn2_b32 s2, 7, s5 +; GFX9-NEXT: s_and_b32 s3, s4, 0xff ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 ; GFX9-NEXT: s_and_b32 s2, s5, 7 -; GFX9-NEXT: s_and_b32 s3, s4, 0xff +; GFX9-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX9-NEXT: s_lshr_b32 s2, s3, s2 ; GFX9-NEXT: s_or_b32 s1, s1, s2 ; GFX9-NEXT: s_and_b32 s1, s1, 0xff @@ -724,18 +772,20 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; ; GFX10-LABEL: s_fshr_v2i8: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_lshr_b32 s3, s0, 8 ; GFX10-NEXT: s_lshr_b32 s4, s1, 8 +; GFX10-NEXT: s_lshr_b32 s3, s0, 8 ; GFX10-NEXT: s_lshl_b32 s0, s0, 1 ; GFX10-NEXT: s_andn2_b32 s5, 7, s2 ; GFX10-NEXT: s_lshr_b32 s6, s2, 8 +; GFX10-NEXT: s_and_b32 s4, s4, 0xff ; GFX10-NEXT: s_lshl_b32 s0, s0, s5 +; GFX10-NEXT: s_and_b32 s1, s1, 0xff ; GFX10-NEXT: s_lshl_b32 s3, s3, 1 ; GFX10-NEXT: s_andn2_b32 s5, 7, s6 ; GFX10-NEXT: s_and_b32 s6, s6, 7 -; GFX10-NEXT: s_and_b32 s4, s4, 0xff +; GFX10-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX10-NEXT: s_and_b32 s2, s2, 7 -; GFX10-NEXT: s_and_b32 s1, s1, 0xff +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX10-NEXT: s_lshl_b32 s3, s3, s5 ; GFX10-NEXT: s_lshr_b32 s4, s4, s6 ; GFX10-NEXT: s_lshr_b32 s1, s1, s2 @@ -749,18 +799,20 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; ; GFX11-LABEL: s_fshr_v2i8: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_lshr_b32 s3, s0, 8 ; GFX11-NEXT: s_lshr_b32 s4, s1, 8 +; GFX11-NEXT: s_lshr_b32 s3, s0, 8 ; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_and_not1_b32 s5, 7, s2 ; GFX11-NEXT: s_lshr_b32 s6, s2, 8 +; GFX11-NEXT: s_and_b32 s4, s4, 0xff ; GFX11-NEXT: s_lshl_b32 s0, s0, s5 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-NEXT: s_lshl_b32 s3, s3, 1 ; GFX11-NEXT: s_and_not1_b32 s5, 7, s6 ; GFX11-NEXT: s_and_b32 s6, s6, 7 -; GFX11-NEXT: s_and_b32 s4, s4, 0xff +; GFX11-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX11-NEXT: s_and_b32 s2, s2, 7 -; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX11-NEXT: s_lshl_b32 s3, s3, s5 ; GFX11-NEXT: s_lshr_b32 s4, s4, s6 ; GFX11-NEXT: s_lshr_b32 s1, s1, s2 @@ -974,34 +1026,37 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; ; GFX8-LABEL: s_fshr_v4i8: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_lshr_b32 s3, s0, 8 -; GFX8-NEXT: s_lshr_b32 s4, s0, 16 -; GFX8-NEXT: s_lshr_b32 s5, s0, 24 ; GFX8-NEXT: s_lshr_b32 s6, s1, 8 ; GFX8-NEXT: s_lshr_b32 s7, s1, 16 ; GFX8-NEXT: s_lshr_b32 s8, s1, 24 +; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_lshr_b32 s3, s0, 8 +; GFX8-NEXT: s_lshr_b32 s4, s0, 16 +; GFX8-NEXT: s_lshr_b32 s5, s0, 24 ; GFX8-NEXT: s_lshr_b32 s9, s2, 8 ; GFX8-NEXT: s_lshr_b32 s10, s2, 16 ; GFX8-NEXT: s_lshr_b32 s11, s2, 24 ; GFX8-NEXT: s_lshl_b32 s0, s0, 1 ; GFX8-NEXT: s_andn2_b32 s12, 7, s2 ; GFX8-NEXT: s_and_b32 s2, s2, 7 -; GFX8-NEXT: s_and_b32 s1, s1, 0xff +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_lshl_b32 s0, s0, s12 ; GFX8-NEXT: s_lshr_b32 s1, s1, s2 ; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_lshl_b32 s1, s3, 1 ; GFX8-NEXT: s_andn2_b32 s2, 7, s9 +; GFX8-NEXT: s_and_b32 s3, s6, 0xff ; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s2, s9, 7 -; GFX8-NEXT: s_and_b32 s3, s6, 0xff +; GFX8-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX8-NEXT: s_lshr_b32 s2, s3, s2 ; GFX8-NEXT: s_or_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s2, s4, 1 ; GFX8-NEXT: s_andn2_b32 s3, 7, s10 +; GFX8-NEXT: s_and_b32 s4, s7, 0xff ; GFX8-NEXT: s_lshl_b32 s2, s2, s3 ; GFX8-NEXT: s_and_b32 s3, s10, 7 -; GFX8-NEXT: s_and_b32 s4, s7, 0xff +; GFX8-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX8-NEXT: s_lshr_b32 s3, s4, s3 ; GFX8-NEXT: s_or_b32 s2, s2, s3 ; GFX8-NEXT: s_lshl_b32 s3, s5, 1 @@ -1024,34 +1079,37 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; ; GFX9-LABEL: s_fshr_v4i8: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_lshr_b32 s3, s0, 8 -; GFX9-NEXT: s_lshr_b32 s4, s0, 16 -; GFX9-NEXT: s_lshr_b32 s5, s0, 24 ; GFX9-NEXT: s_lshr_b32 s6, s1, 8 ; GFX9-NEXT: s_lshr_b32 s7, s1, 16 ; GFX9-NEXT: s_lshr_b32 s8, s1, 24 +; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_lshr_b32 s3, s0, 8 +; GFX9-NEXT: s_lshr_b32 s4, s0, 16 +; GFX9-NEXT: s_lshr_b32 s5, s0, 24 ; GFX9-NEXT: s_lshr_b32 s9, s2, 8 ; GFX9-NEXT: s_lshr_b32 s10, s2, 16 ; GFX9-NEXT: s_lshr_b32 s11, s2, 24 ; GFX9-NEXT: s_lshl_b32 s0, s0, 1 ; GFX9-NEXT: s_andn2_b32 s12, 7, s2 ; GFX9-NEXT: s_and_b32 s2, s2, 7 -; GFX9-NEXT: s_and_b32 s1, s1, 0xff +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX9-NEXT: s_lshl_b32 s0, s0, s12 ; GFX9-NEXT: s_lshr_b32 s1, s1, s2 ; GFX9-NEXT: s_or_b32 s0, s0, s1 ; GFX9-NEXT: s_lshl_b32 s1, s3, 1 ; GFX9-NEXT: s_andn2_b32 s2, 7, s9 +; GFX9-NEXT: s_and_b32 s3, s6, 0xff ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 ; GFX9-NEXT: s_and_b32 s2, s9, 7 -; GFX9-NEXT: s_and_b32 s3, s6, 0xff +; GFX9-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX9-NEXT: s_lshr_b32 s2, s3, s2 ; GFX9-NEXT: s_or_b32 s1, s1, s2 ; GFX9-NEXT: s_lshl_b32 s2, s4, 1 ; GFX9-NEXT: s_andn2_b32 s3, 7, s10 +; GFX9-NEXT: s_and_b32 s4, s7, 0xff ; GFX9-NEXT: s_lshl_b32 s2, s2, s3 ; GFX9-NEXT: s_and_b32 s3, s10, 7 -; GFX9-NEXT: s_and_b32 s4, s7, 0xff +; GFX9-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX9-NEXT: s_lshr_b32 s3, s4, s3 ; GFX9-NEXT: s_or_b32 s2, s2, s3 ; GFX9-NEXT: s_lshl_b32 s3, s5, 1 @@ -1074,16 +1132,18 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; ; GFX10-LABEL: s_fshr_v4i8: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_lshr_b32 s3, s0, 8 ; GFX10-NEXT: s_lshr_b32 s6, s1, 8 ; GFX10-NEXT: s_lshr_b32 s7, s1, 16 ; GFX10-NEXT: s_lshr_b32 s8, s1, 24 +; GFX10-NEXT: s_and_b32 s1, s1, 0xff +; GFX10-NEXT: s_lshr_b32 s3, s0, 8 ; GFX10-NEXT: s_lshr_b32 s9, s2, 8 ; GFX10-NEXT: s_lshr_b32 s10, s2, 16 ; GFX10-NEXT: s_lshr_b32 s11, s2, 24 ; GFX10-NEXT: s_andn2_b32 s12, 7, s2 ; GFX10-NEXT: s_and_b32 s2, s2, 7 -; GFX10-NEXT: s_and_b32 s1, s1, 0xff +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX10-NEXT: s_and_b32 s6, s6, 0xff ; GFX10-NEXT: s_lshr_b32 s4, s0, 16 ; GFX10-NEXT: s_lshr_b32 s5, s0, 24 ; GFX10-NEXT: s_lshl_b32 s0, s0, 1 @@ -1091,18 +1151,19 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; GFX10-NEXT: s_lshl_b32 s2, s3, 1 ; GFX10-NEXT: s_andn2_b32 s3, 7, s9 ; GFX10-NEXT: s_and_b32 s9, s9, 7 -; GFX10-NEXT: s_and_b32 s6, s6, 0xff +; GFX10-NEXT: s_and_b32 s6, 0xffff, s6 ; GFX10-NEXT: s_lshl_b32 s0, s0, s12 ; GFX10-NEXT: s_lshl_b32 s2, s2, s3 ; GFX10-NEXT: s_lshr_b32 s3, s6, s9 ; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: s_or_b32 s1, s2, s3 ; GFX10-NEXT: s_lshl_b32 s2, s4, 1 +; GFX10-NEXT: s_and_b32 s4, s7, 0xff ; GFX10-NEXT: s_andn2_b32 s3, 7, s10 -; GFX10-NEXT: s_and_b32 s4, s10, 7 -; GFX10-NEXT: s_and_b32 s6, s7, 0xff +; GFX10-NEXT: s_and_b32 s6, s10, 7 +; GFX10-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX10-NEXT: s_lshl_b32 s2, s2, s3 -; GFX10-NEXT: s_lshr_b32 s3, s6, s4 +; GFX10-NEXT: s_lshr_b32 s3, s4, s6 ; GFX10-NEXT: s_lshl_b32 s4, s5, 1 ; GFX10-NEXT: s_andn2_b32 s5, 7, s11 ; GFX10-NEXT: s_and_b32 s6, s11, 7 @@ -1124,16 +1185,18 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; ; GFX11-LABEL: s_fshr_v4i8: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_lshr_b32 s3, s0, 8 ; GFX11-NEXT: s_lshr_b32 s6, s1, 8 ; GFX11-NEXT: s_lshr_b32 s7, s1, 16 ; GFX11-NEXT: s_lshr_b32 s8, s1, 24 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_lshr_b32 s3, s0, 8 ; GFX11-NEXT: s_lshr_b32 s9, s2, 8 ; GFX11-NEXT: s_lshr_b32 s10, s2, 16 ; GFX11-NEXT: s_lshr_b32 s11, s2, 24 ; GFX11-NEXT: s_and_not1_b32 s12, 7, s2 ; GFX11-NEXT: s_and_b32 s2, s2, 7 -; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX11-NEXT: s_and_b32 s6, s6, 0xff ; GFX11-NEXT: s_lshr_b32 s4, s0, 16 ; GFX11-NEXT: s_lshr_b32 s5, s0, 24 ; GFX11-NEXT: s_lshl_b32 s0, s0, 1 @@ -1141,18 +1204,19 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; GFX11-NEXT: s_lshl_b32 s2, s3, 1 ; GFX11-NEXT: s_and_not1_b32 s3, 7, s9 ; GFX11-NEXT: s_and_b32 s9, s9, 7 -; GFX11-NEXT: s_and_b32 s6, s6, 0xff +; GFX11-NEXT: s_and_b32 s6, 0xffff, s6 ; GFX11-NEXT: s_lshl_b32 s0, s0, s12 ; GFX11-NEXT: s_lshl_b32 s2, s2, s3 ; GFX11-NEXT: s_lshr_b32 s3, s6, s9 ; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: s_or_b32 s1, s2, s3 ; GFX11-NEXT: s_lshl_b32 s2, s4, 1 +; GFX11-NEXT: s_and_b32 s4, s7, 0xff ; GFX11-NEXT: s_and_not1_b32 s3, 7, s10 -; GFX11-NEXT: s_and_b32 s4, s10, 7 -; GFX11-NEXT: s_and_b32 s6, s7, 0xff +; GFX11-NEXT: s_and_b32 s6, s10, 7 +; GFX11-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX11-NEXT: s_lshl_b32 s2, s2, s3 -; GFX11-NEXT: s_lshr_b32 s3, s6, s4 +; GFX11-NEXT: s_lshr_b32 s3, s4, s6 ; GFX11-NEXT: s_lshl_b32 s4, s5, 1 ; GFX11-NEXT: s_and_not1_b32 s5, 7, s11 ; GFX11-NEXT: s_and_b32 s6, s11, 7 @@ -1451,160 +1515,173 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) ; GFX6: ; %bb.0: ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX6-NEXT: v_not_b32_e32 v1, 23 ; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX6-NEXT: s_lshl_b32 s0, s0, 1 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_and_b32 s1, s1, 0xffffff -; GFX6-NEXT: v_mul_lo_u32 v2, v0, v1 -; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_mul_i32 s4, s3, 0xffffffe8 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s4 +; GFX6-NEXT: v_readfirstlane_b32 s4, v0 +; GFX6-NEXT: s_add_i32 s3, s3, s4 +; GFX6-NEXT: v_mov_b32_e32 v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v0, v1 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v1 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 23, v0 -; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1 -; GFX6-NEXT: v_lshr_b32_e32 v0, s1, v0 -; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX6-NEXT: v_readfirstlane_b32 s0, v0 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_mul_i32 s3, s3, 24 +; GFX6-NEXT: s_sub_i32 s2, s2, s3 +; GFX6-NEXT: s_cmp_ge_u32 s2, 24 +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_sub_i32 s4, s2, 24 +; GFX6-NEXT: s_cmp_lg_u32 s3, 0 +; GFX6-NEXT: s_cselect_b32 s2, s4, s2 +; GFX6-NEXT: s_cmp_ge_u32 s2, 24 +; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_sub_i32 s4, s2, 24 +; GFX6-NEXT: s_cmp_lg_u32 s3, 0 +; GFX6-NEXT: s_cselect_b32 s2, s4, s2 +; GFX6-NEXT: s_lshl_b32 s0, s0, 1 +; GFX6-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX6-NEXT: s_sub_i32 s3, 23, s2 +; GFX6-NEXT: s_lshl_b32 s0, s0, s3 +; GFX6-NEXT: s_lshr_b32 s1, s1, s2 +; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_fshr_i24: ; GFX8: ; %bb.0: ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX8-NEXT: v_not_b32_e32 v1, 23 ; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX8-NEXT: s_lshl_b32 s0, s0, 1 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff -; GFX8-NEXT: v_mul_lo_u32 v2, v0, v1 -; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v0 +; GFX8-NEXT: s_mul_i32 s4, s3, 0xffffffe8 +; GFX8-NEXT: v_mul_hi_u32 v0, v0, s4 +; GFX8-NEXT: v_readfirstlane_b32 s4, v0 +; GFX8-NEXT: s_add_i32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 ; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v1 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 23, v0 -; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0 -; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s1 -; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s3, v0 +; GFX8-NEXT: s_mul_i32 s3, s3, 24 +; GFX8-NEXT: s_sub_i32 s2, s2, s3 +; GFX8-NEXT: s_cmp_ge_u32 s2, 24 +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_sub_i32 s4, s2, 24 +; GFX8-NEXT: s_cmp_lg_u32 s3, 0 +; GFX8-NEXT: s_cselect_b32 s2, s4, s2 +; GFX8-NEXT: s_cmp_ge_u32 s2, 24 +; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_sub_i32 s4, s2, 24 +; GFX8-NEXT: s_cmp_lg_u32 s3, 0 +; GFX8-NEXT: s_cselect_b32 s2, s4, s2 +; GFX8-NEXT: s_lshl_b32 s0, s0, 1 +; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX8-NEXT: s_sub_i32 s3, 23, s2 +; GFX8-NEXT: s_lshl_b32 s0, s0, s3 +; GFX8-NEXT: s_lshr_b32 s1, s1, s2 +; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_fshr_i24: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX9-NEXT: v_not_b32_e32 v1, 23 ; GFX9-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX9-NEXT: s_and_b32 s1, s1, 0xffffff ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s3, v0 +; GFX9-NEXT: s_mul_i32 s4, s3, 0xffffffe8 +; GFX9-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX9-NEXT: s_add_i32 s3, s3, s4 +; GFX9-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX9-NEXT: s_mul_i32 s3, s3, 24 +; GFX9-NEXT: s_sub_i32 s2, s2, s3 +; GFX9-NEXT: s_cmp_ge_u32 s2, 24 +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_sub_i32 s4, s2, 24 +; GFX9-NEXT: s_cmp_lg_u32 s3, 0 +; GFX9-NEXT: s_cselect_b32 s2, s4, s2 +; GFX9-NEXT: s_cmp_ge_u32 s2, 24 +; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_sub_i32 s4, s2, 24 +; GFX9-NEXT: s_cmp_lg_u32 s3, 0 +; GFX9-NEXT: s_cselect_b32 s2, s4, s2 +; GFX9-NEXT: s_sub_i32 s3, 23, s2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 1 -; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1 -; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 -; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 -; GFX9-NEXT: v_add_u32_e32 v1, 0xffffffe8, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_add_u32_e32 v1, 0xffffffe8, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_sub_u32_e32 v1, 23, v0 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s1 -; GFX9-NEXT: v_lshl_or_b32 v0, s0, v1, v0 -; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX9-NEXT: s_lshl_b32 s0, s0, s3 +; GFX9-NEXT: s_lshr_b32 s1, s1, s2 +; GFX9-NEXT: s_or_b32 s0, s0, s1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_fshr_i24: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX10-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX10-NEXT: s_and_b32 s1, s1, 0xffffff -; GFX10-NEXT: s_lshl_b32 s0, s0, 1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0 -; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 -; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v1, 0xffffffe8, v0 -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_add_nc_u32_e32 v1, 0xffffffe8, v0 -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_sub_nc_u32_e32 v1, 23, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s1 -; GFX10-NEXT: v_lshl_or_b32 v0, s0, v1, v0 -; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s3, v0 +; GFX10-NEXT: s_mul_i32 s4, s3, 0xffffffe8 +; GFX10-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX10-NEXT: s_add_i32 s3, s3, s4 +; GFX10-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX10-NEXT: s_mul_i32 s3, s3, 24 +; GFX10-NEXT: s_sub_i32 s2, s2, s3 +; GFX10-NEXT: s_cmp_ge_u32 s2, 24 +; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_sub_i32 s4, s2, 24 +; GFX10-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10-NEXT: s_cselect_b32 s2, s4, s2 +; GFX10-NEXT: s_cmp_ge_u32 s2, 24 +; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_sub_i32 s4, s2, 24 +; GFX10-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10-NEXT: s_cselect_b32 s2, s4, s2 +; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_sub_i32 s3, 23, s2 +; GFX10-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX10-NEXT: s_lshl_b32 s0, s0, s3 +; GFX10-NEXT: s_lshr_b32 s1, s1, s2 +; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: s_fshr_i24: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX11-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX11-NEXT: s_and_b32 s1, s1, 0xffffff -; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0 -; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1 -; GFX11-NEXT: v_mul_hi_u32 v0, s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX11-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_nc_u32_e32 v1, 0xffffffe8, v0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_nc_u32_e32 v1, 0xffffffe8, v0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_sub_nc_u32_e32 v1, 23, v0 -; GFX11-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e64 v0, v0, s1 -; GFX11-NEXT: v_lshl_or_b32 v0, s0, v1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s3, v0 +; GFX11-NEXT: s_mul_i32 s4, s3, 0xffffffe8 +; GFX11-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s3, s3, s4 +; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_i32 s3, s3, 24 +; GFX11-NEXT: s_sub_i32 s2, s2, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_ge_u32 s2, 24 +; GFX11-NEXT: s_cselect_b32 s3, 1, 0 +; GFX11-NEXT: s_sub_i32 s4, s2, 24 +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: s_cselect_b32 s2, s4, s2 +; GFX11-NEXT: s_cmp_ge_u32 s2, 24 +; GFX11-NEXT: s_cselect_b32 s3, 1, 0 +; GFX11-NEXT: s_sub_i32 s4, s2, 24 +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: s_cselect_b32 s2, s4, s2 +; GFX11-NEXT: s_lshl_b32 s0, s0, 1 +; GFX11-NEXT: s_sub_i32 s3, 23, s2 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX11-NEXT: s_lshl_b32 s0, s0, s3 +; GFX11-NEXT: s_lshr_b32 s1, s1, s2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt) ret i24 %result @@ -1616,16 +1693,18 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 24 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3 -; GFX6-NEXT: v_not_b32_e32 v4, 23 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2 +; GFX6-NEXT: v_not_b32_e32 v4, 23 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX6-NEXT: v_mul_lo_u32 v5, v3, v4 -; GFX6-NEXT: v_mul_hi_u32 v5, v3, v5 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX6-NEXT: v_readfirstlane_b32 s4, v3 +; GFX6-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX6-NEXT: v_mul_hi_u32 v3, v3, s5 +; GFX6-NEXT: v_readfirstlane_b32 s5, v3 +; GFX6-NEXT: s_add_i32 s4, s4, s5 +; GFX6-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v4 @@ -1647,16 +1726,18 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 24 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3 -; GFX8-NEXT: v_not_b32_e32 v4, 23 ; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2 +; GFX8-NEXT: v_not_b32_e32 v4, 23 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX8-NEXT: v_mul_lo_u32 v5, v3, v4 -; GFX8-NEXT: v_mul_hi_u32 v5, v3, v5 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 -; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v3 +; GFX8-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX8-NEXT: v_mul_hi_u32 v3, v3, s5 +; GFX8-NEXT: v_readfirstlane_b32 s5, v3 +; GFX8-NEXT: s_add_i32 s4, s4, s5 +; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX8-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v4 @@ -1678,16 +1759,16 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3 -; GFX9-NEXT: v_not_b32_e32 v4, 23 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: v_mul_lo_u32 v4, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v3 +; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX9-NEXT: s_add_i32 s4, s4, s5 +; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2 @@ -1713,10 +1794,11 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v3 -; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4 -; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v3 +; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX10-NEXT: s_add_i32 s4, s4, s5 +; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4 ; GFX10-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2 @@ -1744,12 +1826,13 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) ; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v3 -; GFX11-NEXT: v_mul_hi_u32 v4, v3, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4 -; GFX11-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s0, v3 +; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8 +; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s0, s0, s1 +; GFX11-NEXT: v_mul_hi_u32 v3, v2, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX11-NEXT: v_sub_nc_u32_e32 v2, v2, v3 @@ -1776,129 +1859,141 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) { define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) { ; GFX6-LABEL: s_fshr_v2i24: ; GFX6: ; %bb.0: -; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24 -; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2 -; GFX6-NEXT: s_bfe_u32 s9, s0, 0x80008 -; GFX6-NEXT: v_not_b32_e32 v3, 23 ; GFX6-NEXT: s_lshr_b32 s7, s1, 8 -; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 -; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX6-NEXT: s_and_b32 s8, s0, 0xff -; GFX6-NEXT: s_lshl_b32 s9, s9, 8 +; GFX6-NEXT: s_bfe_u32 s9, s0, 0x80008 ; GFX6-NEXT: s_and_b32 s1, s1, 0xff ; GFX6-NEXT: v_mov_b32_e32 v0, s0 -; GFX6-NEXT: s_bfe_u32 s10, s2, 0x80008 -; GFX6-NEXT: v_mul_lo_u32 v4, v2, v3 -; GFX6-NEXT: s_or_b32 s8, s8, s9 -; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24 -; GFX6-NEXT: s_lshr_b32 s1, s2, 16 -; GFX6-NEXT: s_and_b32 s9, s2, 0xff -; GFX6-NEXT: s_lshl_b32 s10, s10, 8 -; GFX6-NEXT: s_lshr_b32 s6, s0, 16 -; GFX6-NEXT: s_and_b32 s0, s7, 0xff -; GFX6-NEXT: s_lshr_b32 s7, s3, 8 -; GFX6-NEXT: s_or_b32 s9, s9, s10 -; GFX6-NEXT: s_and_b32 s1, s1, 0xff -; GFX6-NEXT: s_and_b32 s3, s3, 0xff -; GFX6-NEXT: v_mov_b32_e32 v1, s2 -; GFX6-NEXT: s_and_b32 s9, 0xffff, s9 -; GFX6-NEXT: s_lshl_b32 s1, s1, 16 -; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 24 -; GFX6-NEXT: s_and_b32 s2, s7, 0xff -; GFX6-NEXT: s_or_b32 s1, s9, s1 -; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX6-NEXT: s_lshl_b32 s2, s2, 16 -; GFX6-NEXT: s_bfe_u32 s9, s4, 0x80008 -; GFX6-NEXT: v_mul_hi_u32 v4, v2, v4 -; GFX6-NEXT: v_or_b32_e32 v1, s2, v1 -; GFX6-NEXT: s_lshr_b32 s2, s4, 16 -; GFX6-NEXT: s_and_b32 s7, s4, 0xff +; GFX6-NEXT: s_and_b32 s8, s0, 0xff ; GFX6-NEXT: s_lshl_b32 s9, s9, 8 -; GFX6-NEXT: s_or_b32 s7, s7, s9 -; GFX6-NEXT: s_and_b32 s2, s2, 0xff -; GFX6-NEXT: s_and_b32 s7, 0xffff, s7 -; GFX6-NEXT: s_lshl_b32 s2, s2, 16 -; GFX6-NEXT: s_or_b32 s2, s7, s2 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v4, s2, v2 -; GFX6-NEXT: s_lshr_b32 s3, s5, 8 -; GFX6-NEXT: s_and_b32 s5, s5, 0xff -; GFX6-NEXT: v_mov_b32_e32 v5, s4 -; GFX6-NEXT: v_alignbit_b32 v5, s5, v5, 24 +; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24 +; GFX6-NEXT: s_lshr_b32 s6, s0, 16 +; GFX6-NEXT: s_or_b32 s8, s8, s9 +; GFX6-NEXT: v_readfirstlane_b32 s0, v0 +; GFX6-NEXT: s_lshr_b32 s9, s3, 8 ; GFX6-NEXT: s_and_b32 s3, s3, 0xff -; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5 -; GFX6-NEXT: v_mul_lo_u32 v4, v4, 24 +; GFX6-NEXT: v_mov_b32_e32 v0, s2 +; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 24 +; GFX6-NEXT: s_and_b32 s1, s7, 0xff +; GFX6-NEXT: s_lshr_b32 s7, s2, 16 +; GFX6-NEXT: s_and_b32 s10, s2, 0xff +; GFX6-NEXT: s_bfe_u32 s11, s2, 0x80008 +; GFX6-NEXT: v_readfirstlane_b32 s2, v0 +; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 +; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX6-NEXT: s_lshl_b32 s11, s11, 8 +; GFX6-NEXT: s_and_b32 s7, s7, 0xff +; GFX6-NEXT: s_and_b32 s3, s9, 0xff +; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX6-NEXT: s_or_b32 s10, s10, s11 +; GFX6-NEXT: s_and_b32 s7, 0xffff, s7 +; GFX6-NEXT: s_and_b32 s3, 0xffff, s3 +; GFX6-NEXT: s_and_b32 s10, 0xffff, s10 +; GFX6-NEXT: s_lshl_b32 s7, s7, 16 +; GFX6-NEXT: s_and_b32 s2, 0xffff, s2 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16 -; GFX6-NEXT: v_or_b32_e32 v5, s3, v5 -; GFX6-NEXT: v_mul_hi_u32 v2, v5, v2 -; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s2, v4 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v4, v3 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX6-NEXT: v_mul_lo_u32 v2, v2, 24 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v4, v3 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v2 -; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v2, v3 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX6-NEXT: s_and_b32 s6, s6, 0xff -; GFX6-NEXT: s_and_b32 s8, 0xffff, s8 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v3 -; GFX6-NEXT: s_lshl_b32 s2, s6, 17 -; GFX6-NEXT: s_lshl_b32 s3, s8, 1 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 -; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX6-NEXT: s_or_b32 s7, s10, s7 ; GFX6-NEXT: s_or_b32 s2, s2, s3 -; GFX6-NEXT: v_and_b32_e32 v6, 0xffffff, v6 -; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX6-NEXT: v_lshl_b32_e32 v6, s2, v6 -; GFX6-NEXT: v_lshr_b32_e32 v4, s1, v4 -; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2 -; GFX6-NEXT: s_lshl_b32 s0, s0, 17 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX6-NEXT: v_or_b32_e32 v4, v6, v4 -; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 -; GFX6-NEXT: v_bfe_u32 v2, v4, 8, 8 -; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v4 -; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 -; GFX6-NEXT: v_bfe_u32 v2, v4, 16, 8 -; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 -; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v0 -; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2 -; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 -; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8 -; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0 -; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 -; GFX6-NEXT: v_readfirstlane_b32 s0, v1 -; GFX6-NEXT: v_readfirstlane_b32 s1, v0 +; GFX6-NEXT: s_lshr_b32 s3, s4, 16 +; GFX6-NEXT: s_lshr_b32 s9, s5, 8 +; GFX6-NEXT: s_and_b32 s10, s4, 0xff +; GFX6-NEXT: s_bfe_u32 s11, s4, 0x80008 +; GFX6-NEXT: s_and_b32 s5, s5, 0xff +; GFX6-NEXT: v_mov_b32_e32 v1, s4 +; GFX6-NEXT: v_readfirstlane_b32 s4, v0 +; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 24 +; GFX6-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s5 +; GFX6-NEXT: s_lshl_b32 s11, s11, 8 +; GFX6-NEXT: s_and_b32 s3, s3, 0xff +; GFX6-NEXT: s_or_b32 s10, s10, s11 +; GFX6-NEXT: s_and_b32 s3, 0xffff, s3 +; GFX6-NEXT: s_and_b32 s10, 0xffff, s10 +; GFX6-NEXT: s_lshl_b32 s3, s3, 16 +; GFX6-NEXT: s_or_b32 s3, s10, s3 +; GFX6-NEXT: v_readfirstlane_b32 s10, v0 +; GFX6-NEXT: s_add_i32 s4, s4, s10 +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0 +; GFX6-NEXT: s_and_b32 s9, s9, 0xff +; GFX6-NEXT: v_readfirstlane_b32 s5, v1 +; GFX6-NEXT: s_and_b32 s9, 0xffff, s9 +; GFX6-NEXT: s_and_b32 s5, 0xffff, s5 +; GFX6-NEXT: s_lshl_b32 s9, s9, 16 +; GFX6-NEXT: s_or_b32 s5, s5, s9 +; GFX6-NEXT: v_readfirstlane_b32 s9, v0 +; GFX6-NEXT: s_and_b32 s6, s6, 0xff +; GFX6-NEXT: s_mul_i32 s9, s9, 24 +; GFX6-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX6-NEXT: s_and_b32 s6, 0xffff, s6 +; GFX6-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX6-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX6-NEXT: s_sub_i32 s3, s3, s9 +; GFX6-NEXT: s_cmp_ge_u32 s3, 24 +; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_sub_i32 s10, s3, 24 +; GFX6-NEXT: s_cmp_lg_u32 s9, 0 +; GFX6-NEXT: s_cselect_b32 s3, s10, s3 +; GFX6-NEXT: s_cmp_ge_u32 s3, 24 +; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_sub_i32 s10, s3, 24 +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: s_cmp_lg_u32 s9, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0 +; GFX6-NEXT: s_cselect_b32 s3, s10, s3 +; GFX6-NEXT: s_lshl_b32 s6, s6, 17 +; GFX6-NEXT: s_lshl_b32 s8, s8, 1 +; GFX6-NEXT: s_sub_i32 s9, 23, s3 +; GFX6-NEXT: s_or_b32 s6, s6, s8 +; GFX6-NEXT: s_lshl_b32 s4, s6, s9 +; GFX6-NEXT: s_lshr_b32 s3, s7, s3 +; GFX6-NEXT: s_or_b32 s4, s4, s3 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_mul_i32 s3, s3, 24 +; GFX6-NEXT: s_sub_i32 s3, s5, s3 +; GFX6-NEXT: s_cmp_ge_u32 s3, 24 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_sub_i32 s6, s3, 24 +; GFX6-NEXT: s_cmp_lg_u32 s5, 0 +; GFX6-NEXT: s_cselect_b32 s3, s6, s3 +; GFX6-NEXT: s_cmp_ge_u32 s3, 24 +; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_sub_i32 s6, s3, 24 +; GFX6-NEXT: s_cmp_lg_u32 s5, 0 +; GFX6-NEXT: s_cselect_b32 s3, s6, s3 +; GFX6-NEXT: s_lshl_b32 s1, s1, 17 +; GFX6-NEXT: s_lshl_b32 s0, s0, 1 +; GFX6-NEXT: s_sub_i32 s5, 23, s3 +; GFX6-NEXT: s_or_b32 s0, s1, s0 +; GFX6-NEXT: s_lshl_b32 s0, s0, s5 +; GFX6-NEXT: s_lshr_b32 s1, s2, s3 +; GFX6-NEXT: s_bfe_u32 s2, s4, 0x80008 +; GFX6-NEXT: s_or_b32 s1, s0, s1 +; GFX6-NEXT: s_and_b32 s0, s4, 0xff +; GFX6-NEXT: s_lshl_b32 s2, s2, 8 +; GFX6-NEXT: s_or_b32 s0, s0, s2 +; GFX6-NEXT: s_bfe_u32 s2, s4, 0x80010 +; GFX6-NEXT: s_lshl_b32 s2, s2, 16 +; GFX6-NEXT: s_or_b32 s0, s0, s2 +; GFX6-NEXT: s_and_b32 s2, s1, 0xff +; GFX6-NEXT: s_lshl_b32 s2, s2, 24 +; GFX6-NEXT: s_or_b32 s0, s0, s2 +; GFX6-NEXT: s_bfe_u32 s2, s1, 0x80008 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x80010 +; GFX6-NEXT: s_lshl_b32 s1, s1, 8 +; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_fshr_v2i24: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 -; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_lshr_b32 s9, s1, 8 ; GFX8-NEXT: s_and_b32 s1, s1, 0xff ; GFX8-NEXT: s_lshr_b32 s6, s0, 8 ; GFX8-NEXT: s_lshr_b32 s8, s0, 24 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8 -; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: s_and_b32 s6, s6, 0xff ; GFX8-NEXT: s_or_b32 s1, s8, s1 ; GFX8-NEXT: s_lshr_b32 s8, s2, 8 -; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: s_lshr_b32 s7, s0, 16 ; GFX8-NEXT: s_and_b32 s0, s0, 0xff ; GFX8-NEXT: s_lshl_b32 s6, s6, 8 @@ -1912,101 +2007,123 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i ; GFX8-NEXT: s_lshl_b32 s8, s8, 8 ; GFX8-NEXT: s_or_b32 s2, s2, s8 ; GFX8-NEXT: s_and_b32 s8, s9, 0xff -; GFX8-NEXT: v_not_b32_e32 v1, 23 +; GFX8-NEXT: s_and_b32 s8, 0xffff, s8 ; GFX8-NEXT: s_lshr_b32 s11, s3, 8 +; GFX8-NEXT: s_and_b32 s2, 0xffff, s2 ; GFX8-NEXT: s_lshl_b32 s8, s8, 16 ; GFX8-NEXT: s_and_b32 s3, s3, 0xff -; GFX8-NEXT: v_mul_lo_u32 v2, v0, v1 +; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX8-NEXT: s_or_b32 s2, s2, s8 ; GFX8-NEXT: s_lshl_b32 s3, s3, 8 ; GFX8-NEXT: s_and_b32 s8, s11, 0xff +; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_or_b32 s3, s10, s3 +; GFX8-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX8-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX8-NEXT: s_lshl_b32 s8, s8, 16 ; GFX8-NEXT: s_or_b32 s3, s3, s8 ; GFX8-NEXT: s_lshr_b32 s8, s4, 8 ; GFX8-NEXT: s_and_b32 s8, s8, 0xff -; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2 +; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: s_lshr_b32 s9, s4, 16 ; GFX8-NEXT: s_lshr_b32 s10, s4, 24 ; GFX8-NEXT: s_and_b32 s4, s4, 0xff ; GFX8-NEXT: s_lshl_b32 s8, s8, 8 +; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: s_or_b32 s4, s4, s8 ; GFX8-NEXT: s_and_b32 s8, s9, 0xff +; GFX8-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX8-NEXT: s_and_b32 s4, 0xffff, s4 ; GFX8-NEXT: s_lshl_b32 s8, s8, 16 ; GFX8-NEXT: s_or_b32 s4, s4, s8 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 -; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 +; GFX8-NEXT: v_readfirstlane_b32 s8, v0 +; GFX8-NEXT: s_mul_i32 s9, s8, 0xffffffe8 +; GFX8-NEXT: v_mul_hi_u32 v0, v0, s9 ; GFX8-NEXT: s_lshr_b32 s11, s5, 8 ; GFX8-NEXT: s_and_b32 s5, s5, 0xff ; GFX8-NEXT: s_lshl_b32 s5, s5, 8 -; GFX8-NEXT: v_mul_lo_u32 v2, v2, 24 -; GFX8-NEXT: s_and_b32 s8, s11, 0xff ; GFX8-NEXT: s_or_b32 s5, s10, s5 -; GFX8-NEXT: s_lshl_b32 s8, s8, 16 -; GFX8-NEXT: s_or_b32 s5, s5, s8 -; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s4, v2 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v1 +; GFX8-NEXT: v_readfirstlane_b32 s10, v0 +; GFX8-NEXT: s_add_i32 s8, s8, s10 +; GFX8-NEXT: v_mov_b32_e32 v0, s8 +; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0 +; GFX8-NEXT: s_and_b32 s9, s11, 0xff +; GFX8-NEXT: s_and_b32 s9, 0xffff, s9 +; GFX8-NEXT: s_and_b32 s5, 0xffff, s5 +; GFX8-NEXT: s_lshl_b32 s9, s9, 16 +; GFX8-NEXT: s_or_b32 s5, s5, s9 +; GFX8-NEXT: v_readfirstlane_b32 s9, v0 +; GFX8-NEXT: s_mul_i32 s9, s9, 24 +; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX8-NEXT: s_and_b32 s6, 0xffff, s6 +; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX8-NEXT: s_and_b32 s7, 0xffff, s7 +; GFX8-NEXT: s_sub_i32 s4, s4, s9 +; GFX8-NEXT: s_cmp_ge_u32 s4, 24 +; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_sub_i32 s10, s4, 24 +; GFX8-NEXT: s_cmp_lg_u32 s9, 0 +; GFX8-NEXT: s_cselect_b32 s4, s10, s4 +; GFX8-NEXT: s_cmp_ge_u32 s4, 24 +; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_sub_i32 s10, s4, 24 +; GFX8-NEXT: v_mov_b32_e32 v0, s8 +; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v1 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 -; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2 -; GFX8-NEXT: s_lshl_b32 s4, s6, 17 +; GFX8-NEXT: s_cselect_b32 s4, s10, s4 +; GFX8-NEXT: s_lshl_b32 s6, s6, 17 ; GFX8-NEXT: s_lshl_b32 s0, s0, 1 -; GFX8-NEXT: s_or_b32 s0, s4, s0 -; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; GFX8-NEXT: v_lshlrev_b32_e64 v3, v3, s0 -; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s2 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0 -; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v0, v1 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1 -; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 23, v0 -; GFX8-NEXT: s_lshl_b32 s0, s7, 17 +; GFX8-NEXT: s_sub_i32 s9, 23, s4 +; GFX8-NEXT: s_or_b32 s0, s6, s0 +; GFX8-NEXT: s_lshl_b32 s0, s0, s9 +; GFX8-NEXT: s_lshr_b32 s2, s2, s4 +; GFX8-NEXT: s_or_b32 s0, s0, s2 +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: s_mul_i32 s2, s2, 24 +; GFX8-NEXT: s_sub_i32 s2, s5, s2 +; GFX8-NEXT: s_cmp_ge_u32 s2, 24 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_sub_i32 s5, s2, 24 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-NEXT: s_cselect_b32 s2, s5, s2 +; GFX8-NEXT: s_cmp_ge_u32 s2, 24 +; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_sub_i32 s5, s2, 24 +; GFX8-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-NEXT: s_cselect_b32 s2, s5, s2 +; GFX8-NEXT: s_lshl_b32 s5, s7, 17 ; GFX8-NEXT: s_lshl_b32 s1, s1, 1 -; GFX8-NEXT: s_or_b32 s0, s0, s1 -; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0 -; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s3 -; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 8 -; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 -; GFX8-NEXT: v_mov_b32_e32 v4, 16 -; GFX8-NEXT: v_or_b32_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 -; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 -; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v0 -; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 -; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 -; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD -; GFX8-NEXT: v_readfirstlane_b32 s0, v2 -; GFX8-NEXT: v_readfirstlane_b32 s1, v0 +; GFX8-NEXT: s_sub_i32 s4, 23, s2 +; GFX8-NEXT: s_or_b32 s1, s5, s1 +; GFX8-NEXT: s_lshl_b32 s1, s1, s4 +; GFX8-NEXT: s_lshr_b32 s2, s3, s2 +; GFX8-NEXT: s_bfe_u32 s3, s0, 0x80008 +; GFX8-NEXT: s_or_b32 s1, s1, s2 +; GFX8-NEXT: s_and_b32 s2, s0, 0xff +; GFX8-NEXT: s_lshl_b32 s3, s3, 8 +; GFX8-NEXT: s_bfe_u32 s0, s0, 0x80010 +; GFX8-NEXT: s_or_b32 s2, s2, s3 +; GFX8-NEXT: s_lshl_b32 s0, s0, 16 +; GFX8-NEXT: s_or_b32 s0, s2, s0 +; GFX8-NEXT: s_and_b32 s2, s1, 0xff +; GFX8-NEXT: s_lshl_b32 s2, s2, 24 +; GFX8-NEXT: s_or_b32 s0, s0, s2 +; GFX8-NEXT: s_bfe_u32 s2, s1, 0x80008 +; GFX8-NEXT: s_bfe_u32 s1, s1, 0x80010 +; GFX8-NEXT: s_lshl_b32 s1, s1, 8 +; GFX8-NEXT: s_or_b32 s1, s2, s1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_fshr_v2i24: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_lshr_b32 s9, s1, 8 ; GFX9-NEXT: s_and_b32 s1, s1, 0xff ; GFX9-NEXT: s_lshr_b32 s6, s0, 8 ; GFX9-NEXT: s_lshr_b32 s8, s0, 24 ; GFX9-NEXT: s_lshl_b32 s1, s1, 8 -; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: s_and_b32 s6, s6, 0xff ; GFX9-NEXT: s_or_b32 s1, s8, s1 ; GFX9-NEXT: s_lshr_b32 s8, s2, 8 -; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: s_lshr_b32 s7, s0, 16 ; GFX9-NEXT: s_and_b32 s0, s0, 0xff ; GFX9-NEXT: s_lshl_b32 s6, s6, 8 @@ -2020,307 +2137,359 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i ; GFX9-NEXT: s_lshl_b32 s8, s8, 8 ; GFX9-NEXT: s_or_b32 s2, s2, s8 ; GFX9-NEXT: s_and_b32 s8, s9, 0xff -; GFX9-NEXT: v_not_b32_e32 v1, 23 +; GFX9-NEXT: s_and_b32 s8, 0xffff, s8 ; GFX9-NEXT: s_lshr_b32 s11, s3, 8 +; GFX9-NEXT: s_and_b32 s2, 0xffff, s2 ; GFX9-NEXT: s_lshl_b32 s8, s8, 16 ; GFX9-NEXT: s_and_b32 s3, s3, 0xff -; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1 ; GFX9-NEXT: s_or_b32 s2, s2, s8 ; GFX9-NEXT: s_lshl_b32 s3, s3, 8 ; GFX9-NEXT: s_and_b32 s8, s11, 0xff ; GFX9-NEXT: s_or_b32 s3, s10, s3 +; GFX9-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX9-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX9-NEXT: s_lshl_b32 s8, s8, 16 +; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX9-NEXT: s_or_b32 s3, s3, s8 ; GFX9-NEXT: s_lshr_b32 s8, s4, 8 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_and_b32 s8, s8, 0xff -; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: s_lshr_b32 s9, s4, 16 ; GFX9-NEXT: s_lshr_b32 s10, s4, 24 ; GFX9-NEXT: s_and_b32 s4, s4, 0xff ; GFX9-NEXT: s_lshl_b32 s8, s8, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s8 ; GFX9-NEXT: s_and_b32 s8, s9, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s8, 16 -; GFX9-NEXT: s_or_b32 s4, s4, s8 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 -; GFX9-NEXT: v_mul_hi_u32 v1, s4, v0 +; GFX9-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: s_lshr_b32 s11, s5, 8 +; GFX9-NEXT: s_and_b32 s4, 0xffff, s4 +; GFX9-NEXT: s_lshl_b32 s8, s8, 16 ; GFX9-NEXT: s_and_b32 s5, s5, 0xff +; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: s_or_b32 s4, s4, s8 ; GFX9-NEXT: s_lshl_b32 s5, s5, 8 ; GFX9-NEXT: s_and_b32 s8, s11, 0xff ; GFX9-NEXT: s_or_b32 s5, s10, s5 -; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24 +; GFX9-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX9-NEXT: s_and_b32 s5, 0xffff, s5 ; GFX9-NEXT: s_lshl_b32 s8, s8, 16 ; GFX9-NEXT: s_or_b32 s5, s5, s8 -; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0 -; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v1 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v1 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1 -; GFX9-NEXT: s_lshl_b32 s4, s6, 17 +; GFX9-NEXT: v_readfirstlane_b32 s8, v0 +; GFX9-NEXT: s_mul_i32 s9, s8, 0xffffffe8 +; GFX9-NEXT: s_mul_hi_u32 s9, s8, s9 +; GFX9-NEXT: s_add_i32 s8, s8, s9 +; GFX9-NEXT: s_mul_hi_u32 s9, s4, s8 +; GFX9-NEXT: s_mul_i32 s9, s9, 24 +; GFX9-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX9-NEXT: s_and_b32 s6, 0xffff, s6 +; GFX9-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX9-NEXT: s_and_b32 s7, 0xffff, s7 +; GFX9-NEXT: s_sub_i32 s4, s4, s9 +; GFX9-NEXT: s_cmp_ge_u32 s4, 24 +; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_sub_i32 s10, s4, 24 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: s_cselect_b32 s4, s10, s4 +; GFX9-NEXT: s_cmp_ge_u32 s4, 24 +; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_sub_i32 s10, s4, 24 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: s_cselect_b32 s4, s10, s4 +; GFX9-NEXT: s_lshl_b32 s6, s6, 17 ; GFX9-NEXT: s_lshl_b32 s0, s0, 1 -; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX9-NEXT: s_or_b32 s0, s4, s0 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s2 -; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0 -; GFX9-NEXT: v_lshl_or_b32 v1, s0, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_sub_u32_e32 v2, 23, v0 -; GFX9-NEXT: s_lshl_b32 s0, s7, 17 +; GFX9-NEXT: s_sub_i32 s9, 23, s4 +; GFX9-NEXT: s_or_b32 s0, s6, s0 +; GFX9-NEXT: s_lshl_b32 s0, s0, s9 +; GFX9-NEXT: s_lshr_b32 s2, s2, s4 +; GFX9-NEXT: s_or_b32 s0, s0, s2 +; GFX9-NEXT: s_mul_hi_u32 s2, s5, s8 +; GFX9-NEXT: s_mul_i32 s2, s2, 24 +; GFX9-NEXT: s_sub_i32 s2, s5, s2 +; GFX9-NEXT: s_cmp_ge_u32 s2, 24 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_sub_i32 s5, s2, 24 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-NEXT: s_cselect_b32 s2, s5, s2 +; GFX9-NEXT: s_cmp_ge_u32 s2, 24 +; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_sub_i32 s5, s2, 24 +; GFX9-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-NEXT: s_cselect_b32 s2, s5, s2 +; GFX9-NEXT: s_lshl_b32 s5, s7, 17 ; GFX9-NEXT: s_lshl_b32 s1, s1, 1 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX9-NEXT: s_or_b32 s0, s0, s1 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s3 -; GFX9-NEXT: v_mov_b32_e32 v3, 8 -; GFX9-NEXT: v_lshl_or_b32 v0, s0, v2, v0 -; GFX9-NEXT: v_mov_b32_e32 v2, 0xff -; GFX9-NEXT: v_lshlrev_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 -; GFX9-NEXT: v_and_or_b32 v2, v1, v2, v3 -; GFX9-NEXT: v_mov_b32_e32 v3, 16 -; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v0 -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3 -; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8 -; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8 -; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s0, v1 -; GFX9-NEXT: v_readfirstlane_b32 s1, v0 +; GFX9-NEXT: s_sub_i32 s4, 23, s2 +; GFX9-NEXT: s_or_b32 s1, s5, s1 +; GFX9-NEXT: s_lshl_b32 s1, s1, s4 +; GFX9-NEXT: s_lshr_b32 s2, s3, s2 +; GFX9-NEXT: s_bfe_u32 s3, s0, 0x80008 +; GFX9-NEXT: s_or_b32 s1, s1, s2 +; GFX9-NEXT: s_and_b32 s2, s0, 0xff +; GFX9-NEXT: s_lshl_b32 s3, s3, 8 +; GFX9-NEXT: s_bfe_u32 s0, s0, 0x80010 +; GFX9-NEXT: s_or_b32 s2, s2, s3 +; GFX9-NEXT: s_lshl_b32 s0, s0, 16 +; GFX9-NEXT: s_or_b32 s0, s2, s0 +; GFX9-NEXT: s_and_b32 s2, s1, 0xff +; GFX9-NEXT: s_lshl_b32 s2, s2, 24 +; GFX9-NEXT: s_or_b32 s0, s0, s2 +; GFX9-NEXT: s_bfe_u32 s2, s1, 0x80008 +; GFX9-NEXT: s_bfe_u32 s1, s1, 0x80010 +; GFX9-NEXT: s_lshl_b32 s1, s1, 8 +; GFX9-NEXT: s_or_b32 s1, s2, s1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_fshr_v2i24: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 -; GFX10-NEXT: s_lshr_b32 s13, s4, 8 -; GFX10-NEXT: s_lshr_b32 s14, s4, 16 -; GFX10-NEXT: s_and_b32 s13, s13, 0xff -; GFX10-NEXT: s_lshr_b32 s15, s4, 24 -; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX10-NEXT: s_and_b32 s4, s4, 0xff -; GFX10-NEXT: s_and_b32 s14, s14, 0xff -; GFX10-NEXT: s_lshl_b32 s13, s13, 8 -; GFX10-NEXT: s_lshl_b32 s14, s14, 16 -; GFX10-NEXT: s_or_b32 s4, s4, s13 -; GFX10-NEXT: s_lshr_b32 s16, s5, 8 -; GFX10-NEXT: s_and_b32 s5, s5, 0xff -; GFX10-NEXT: s_or_b32 s4, s4, s14 -; GFX10-NEXT: s_lshl_b32 s5, s5, 8 -; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 -; GFX10-NEXT: s_and_b32 s16, s16, 0xff -; GFX10-NEXT: s_or_b32 s5, s15, s5 -; GFX10-NEXT: s_lshl_b32 s13, s16, 16 -; GFX10-NEXT: s_lshr_b32 s10, s2, 8 -; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX10-NEXT: s_or_b32 s5, s5, s13 ; GFX10-NEXT: s_lshr_b32 s9, s1, 8 ; GFX10-NEXT: s_and_b32 s1, s1, 0xff -; GFX10-NEXT: s_lshr_b32 s11, s2, 16 -; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0 -; GFX10-NEXT: s_lshr_b32 s13, s3, 8 -; GFX10-NEXT: s_and_b32 s3, s3, 0xff -; GFX10-NEXT: s_and_b32 s10, s10, 0xff ; GFX10-NEXT: s_lshr_b32 s6, s0, 8 ; GFX10-NEXT: s_lshr_b32 s8, s0, 24 -; GFX10-NEXT: s_lshr_b32 s12, s2, 24 -; GFX10-NEXT: s_and_b32 s2, s2, 0xff -; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 8 -; GFX10-NEXT: s_and_b32 s11, s11, 0xff -; GFX10-NEXT: s_lshl_b32 s3, s3, 8 -; GFX10-NEXT: s_and_b32 s13, s13, 0xff +; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: s_and_b32 s6, s6, 0xff ; GFX10-NEXT: s_or_b32 s1, s8, s1 -; GFX10-NEXT: s_or_b32 s3, s12, s3 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 -; GFX10-NEXT: s_lshl_b32 s8, s13, 16 +; GFX10-NEXT: s_lshr_b32 s8, s2, 8 ; GFX10-NEXT: s_lshr_b32 s7, s0, 16 ; GFX10-NEXT: s_and_b32 s0, s0, 0xff ; GFX10-NEXT: s_lshl_b32 s6, s6, 8 -; GFX10-NEXT: v_mul_hi_u32 v2, s4, v0 -; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0 -; GFX10-NEXT: s_or_b32 s3, s3, s8 -; GFX10-NEXT: s_and_b32 s7, s7, 0xff -; GFX10-NEXT: s_and_b32 s9, s9, 0xff +; GFX10-NEXT: s_and_b32 s8, s8, 0xff ; GFX10-NEXT: s_or_b32 s0, s0, s6 -; GFX10-NEXT: s_lshl_b32 s7, s7, 17 -; GFX10-NEXT: s_lshl_b32 s9, s9, 17 -; GFX10-NEXT: v_mul_lo_u32 v2, v2, 24 -; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24 +; GFX10-NEXT: s_and_b32 s6, s7, 0xff +; GFX10-NEXT: s_and_b32 s7, s9, 0xff +; GFX10-NEXT: s_lshr_b32 s9, s2, 16 +; GFX10-NEXT: s_lshr_b32 s10, s2, 24 +; GFX10-NEXT: s_and_b32 s2, s2, 0xff +; GFX10-NEXT: s_lshl_b32 s8, s8, 8 +; GFX10-NEXT: s_lshr_b32 s11, s3, 8 +; GFX10-NEXT: s_or_b32 s2, s2, s8 +; GFX10-NEXT: s_and_b32 s8, s9, 0xff +; GFX10-NEXT: s_and_b32 s3, s3, 0xff +; GFX10-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX10-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX10-NEXT: s_lshl_b32 s8, s8, 16 +; GFX10-NEXT: s_lshl_b32 s3, s3, 8 +; GFX10-NEXT: s_and_b32 s9, s11, 0xff +; GFX10-NEXT: s_or_b32 s3, s10, s3 +; GFX10-NEXT: s_and_b32 s9, 0xffff, s9 +; GFX10-NEXT: s_or_b32 s2, s2, s8 +; GFX10-NEXT: s_lshr_b32 s8, s4, 8 +; GFX10-NEXT: s_and_b32 s3, 0xffff, s3 +; GFX10-NEXT: s_lshl_b32 s9, s9, 16 +; GFX10-NEXT: s_and_b32 s8, s8, 0xff +; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX10-NEXT: s_or_b32 s3, s3, s9 +; GFX10-NEXT: s_lshr_b32 s9, s4, 16 +; GFX10-NEXT: s_lshr_b32 s10, s4, 24 +; GFX10-NEXT: s_and_b32 s4, s4, 0xff +; GFX10-NEXT: s_lshl_b32 s8, s8, 8 +; GFX10-NEXT: s_lshr_b32 s11, s5, 8 +; GFX10-NEXT: s_or_b32 s4, s4, s8 +; GFX10-NEXT: s_and_b32 s8, s9, 0xff +; GFX10-NEXT: v_readfirstlane_b32 s9, v0 +; GFX10-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX10-NEXT: s_and_b32 s4, 0xffff, s4 +; GFX10-NEXT: s_lshl_b32 s8, s8, 16 +; GFX10-NEXT: s_and_b32 s5, s5, 0xff +; GFX10-NEXT: s_or_b32 s4, s4, s8 +; GFX10-NEXT: s_mul_i32 s8, s9, 0xffffffe8 +; GFX10-NEXT: s_lshl_b32 s5, s5, 8 +; GFX10-NEXT: s_mul_hi_u32 s8, s9, s8 +; GFX10-NEXT: s_or_b32 s5, s10, s5 +; GFX10-NEXT: s_add_i32 s9, s9, s8 +; GFX10-NEXT: s_and_b32 s10, s11, 0xff +; GFX10-NEXT: s_mul_hi_u32 s8, s4, s9 +; GFX10-NEXT: s_and_b32 s10, 0xffff, s10 +; GFX10-NEXT: s_mul_i32 s8, s8, 24 +; GFX10-NEXT: s_and_b32 s5, 0xffff, s5 +; GFX10-NEXT: s_lshl_b32 s10, s10, 16 +; GFX10-NEXT: s_sub_i32 s4, s4, s8 +; GFX10-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX10-NEXT: s_and_b32 s6, 0xffff, s6 +; GFX10-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX10-NEXT: s_and_b32 s7, 0xffff, s7 +; GFX10-NEXT: s_or_b32 s5, s5, s10 +; GFX10-NEXT: s_cmp_ge_u32 s4, 24 +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_sub_i32 s10, s4, 24 +; GFX10-NEXT: s_cmp_lg_u32 s8, 0 +; GFX10-NEXT: s_cselect_b32 s4, s10, s4 +; GFX10-NEXT: s_cmp_ge_u32 s4, 24 +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_sub_i32 s10, s4, 24 +; GFX10-NEXT: s_cmp_lg_u32 s8, 0 +; GFX10-NEXT: s_cselect_b32 s4, s10, s4 +; GFX10-NEXT: s_lshl_b32 s6, s6, 17 ; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_sub_i32 s8, 23, s4 +; GFX10-NEXT: s_or_b32 s0, s6, s0 +; GFX10-NEXT: s_mul_hi_u32 s6, s5, s9 +; GFX10-NEXT: s_lshl_b32 s0, s0, s8 +; GFX10-NEXT: s_mul_i32 s6, s6, 24 +; GFX10-NEXT: s_lshr_b32 s2, s2, s4 +; GFX10-NEXT: s_sub_i32 s4, s5, s6 +; GFX10-NEXT: s_or_b32 s0, s0, s2 +; GFX10-NEXT: s_cmp_ge_u32 s4, 24 +; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_sub_i32 s5, s4, 24 +; GFX10-NEXT: s_cmp_lg_u32 s2, 0 +; GFX10-NEXT: s_cselect_b32 s2, s5, s4 +; GFX10-NEXT: s_cmp_ge_u32 s2, 24 +; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_sub_i32 s5, s2, 24 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: s_cselect_b32 s2, s5, s2 +; GFX10-NEXT: s_lshl_b32 s4, s7, 17 ; GFX10-NEXT: s_lshl_b32 s1, s1, 1 -; GFX10-NEXT: s_or_b32 s0, s7, s0 -; GFX10-NEXT: s_or_b32 s1, s9, s1 -; GFX10-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, s4, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0 -; GFX10-NEXT: s_lshl_b32 s4, s10, 8 -; GFX10-NEXT: s_lshl_b32 s5, s11, 16 -; GFX10-NEXT: s_or_b32 s2, s2, s4 -; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2 -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2 -; GFX10-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v0 -; GFX10-NEXT: s_or_b32 s2, s2, s5 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2 -; GFX10-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX10-NEXT: v_lshrrev_b32_e64 v2, v2, s2 -; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4 -; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s3 -; GFX10-NEXT: v_lshl_or_b32 v2, s0, v3, v2 -; GFX10-NEXT: v_mov_b32_e32 v3, 16 -; GFX10-NEXT: v_lshl_or_b32 v0, s1, v4, v0 -; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 -; GFX10-NEXT: v_lshlrev_b32_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 -; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v0 -; GFX10-NEXT: v_bfe_u32 v5, v0, 8, 8 -; GFX10-NEXT: v_and_or_b32 v1, 0xff, v2, v1 -; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8 -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v4 -; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v5 -; GFX10-NEXT: v_or3_b32 v1, v1, v3, v2 -; GFX10-NEXT: v_readfirstlane_b32 s1, v0 -; GFX10-NEXT: v_readfirstlane_b32 s0, v1 +; GFX10-NEXT: s_sub_i32 s5, 23, s2 +; GFX10-NEXT: s_or_b32 s1, s4, s1 +; GFX10-NEXT: s_lshr_b32 s2, s3, s2 +; GFX10-NEXT: s_lshl_b32 s1, s1, s5 +; GFX10-NEXT: s_and_b32 s3, s0, 0xff +; GFX10-NEXT: s_or_b32 s1, s1, s2 +; GFX10-NEXT: s_bfe_u32 s2, s0, 0x80008 +; GFX10-NEXT: s_bfe_u32 s0, s0, 0x80010 +; GFX10-NEXT: s_lshl_b32 s2, s2, 8 +; GFX10-NEXT: s_lshl_b32 s0, s0, 16 +; GFX10-NEXT: s_or_b32 s2, s3, s2 +; GFX10-NEXT: s_and_b32 s3, s1, 0xff +; GFX10-NEXT: s_or_b32 s0, s2, s0 +; GFX10-NEXT: s_lshl_b32 s2, s3, 24 +; GFX10-NEXT: s_bfe_u32 s3, s1, 0x80010 +; GFX10-NEXT: s_bfe_u32 s1, s1, 0x80008 +; GFX10-NEXT: s_lshl_b32 s3, s3, 8 +; GFX10-NEXT: s_or_b32 s0, s0, s2 +; GFX10-NEXT: s_or_b32 s1, s1, s3 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: s_fshr_v2i24: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 -; GFX11-NEXT: s_lshr_b32 s14, s4, 8 -; GFX11-NEXT: s_lshr_b32 s15, s4, 16 -; GFX11-NEXT: s_and_b32 s14, s14, 0xff -; GFX11-NEXT: s_lshr_b32 s16, s4, 24 +; GFX11-NEXT: s_lshr_b32 s9, s1, 8 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_lshr_b32 s6, s0, 8 +; GFX11-NEXT: s_lshr_b32 s8, s0, 24 +; GFX11-NEXT: s_lshl_b32 s1, s1, 8 ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX11-NEXT: s_and_b32 s4, s4, 0xff -; GFX11-NEXT: s_and_b32 s15, s15, 0xff -; GFX11-NEXT: s_lshl_b32 s14, s14, 8 -; GFX11-NEXT: s_lshl_b32 s15, s15, 16 -; GFX11-NEXT: s_or_b32 s4, s4, s14 -; GFX11-NEXT: s_lshr_b32 s17, s5, 8 -; GFX11-NEXT: s_and_b32 s5, s5, 0xff -; GFX11-NEXT: s_or_b32 s4, s4, s15 -; GFX11-NEXT: s_lshl_b32 s5, s5, 8 +; GFX11-NEXT: s_and_b32 s6, s6, 0xff +; GFX11-NEXT: s_or_b32 s1, s8, s1 +; GFX11-NEXT: s_lshr_b32 s8, s2, 8 +; GFX11-NEXT: s_lshr_b32 s7, s0, 16 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s6, 8 +; GFX11-NEXT: s_and_b32 s8, s8, 0xff +; GFX11-NEXT: s_or_b32 s0, s0, s6 +; GFX11-NEXT: s_and_b32 s6, s7, 0xff +; GFX11-NEXT: s_and_b32 s7, s9, 0xff +; GFX11-NEXT: s_lshr_b32 s9, s2, 16 +; GFX11-NEXT: s_lshr_b32 s10, s2, 24 +; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: s_lshl_b32 s8, s8, 8 +; GFX11-NEXT: s_lshr_b32 s11, s3, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s8 +; GFX11-NEXT: s_and_b32 s8, s9, 0xff +; GFX11-NEXT: s_and_b32 s3, s3, 0xff +; GFX11-NEXT: s_and_b32 s8, 0xffff, s8 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 -; GFX11-NEXT: s_and_b32 s17, s17, 0xff -; GFX11-NEXT: s_or_b32 s5, s16, s5 -; GFX11-NEXT: s_lshl_b32 s14, s17, 16 -; GFX11-NEXT: s_lshr_b32 s10, s2, 8 -; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX11-NEXT: s_or_b32 s5, s5, s14 -; GFX11-NEXT: s_lshr_b32 s11, s2, 16 -; GFX11-NEXT: s_and_b32 s10, s10, 0xff -; GFX11-NEXT: s_lshr_b32 s6, s0, 8 -; GFX11-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0 -; GFX11-NEXT: s_lshr_b32 s12, s2, 24 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_and_b32 s11, s11, 0xff -; GFX11-NEXT: s_and_b32 s6, s6, 0xff -; GFX11-NEXT: s_lshr_b32 s7, s0, 16 -; GFX11-NEXT: s_lshr_b32 s8, s0, 24 -; GFX11-NEXT: s_lshr_b32 s9, s1, 8 -; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1 -; GFX11-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-NEXT: s_and_b32 s1, s1, 0xff -; GFX11-NEXT: s_lshr_b32 s13, s3, 8 -; GFX11-NEXT: s_and_b32 s3, s3, 0xff -; GFX11-NEXT: s_lshl_b32 s6, s6, 8 -; GFX11-NEXT: s_and_b32 s7, s7, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s1, 8 -; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX11-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 ; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_and_b32 s13, s13, 0xff -; GFX11-NEXT: s_or_b32 s0, s0, s6 -; GFX11-NEXT: s_or_b32 s1, s8, s1 -; GFX11-NEXT: v_mul_hi_u32 v1, s4, v0 -; GFX11-NEXT: v_mul_hi_u32 v0, s5, v0 -; GFX11-NEXT: s_or_b32 s3, s12, s3 -; GFX11-NEXT: s_lshl_b32 s8, s13, 16 -; GFX11-NEXT: s_lshl_b32 s7, s7, 17 +; GFX11-NEXT: s_and_b32 s9, s11, 0xff +; GFX11-NEXT: s_or_b32 s3, s10, s3 +; GFX11-NEXT: s_and_b32 s9, 0xffff, s9 +; GFX11-NEXT: s_or_b32 s2, s2, s8 +; GFX11-NEXT: s_lshr_b32 s8, s4, 8 +; GFX11-NEXT: s_and_b32 s3, 0xffff, s3 +; GFX11-NEXT: s_lshl_b32 s9, s9, 16 +; GFX11-NEXT: s_and_b32 s8, s8, 0xff +; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX11-NEXT: s_or_b32 s3, s3, s9 +; GFX11-NEXT: s_lshr_b32 s9, s4, 16 +; GFX11-NEXT: s_lshr_b32 s10, s4, 24 +; GFX11-NEXT: s_and_b32 s4, s4, 0xff +; GFX11-NEXT: s_lshl_b32 s8, s8, 8 +; GFX11-NEXT: s_lshr_b32 s11, s5, 8 +; GFX11-NEXT: s_or_b32 s4, s4, s8 +; GFX11-NEXT: s_and_b32 s8, s9, 0xff +; GFX11-NEXT: v_readfirstlane_b32 s9, v0 +; GFX11-NEXT: s_and_b32 s8, 0xffff, s8 +; GFX11-NEXT: s_and_b32 s4, 0xffff, s4 +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 +; GFX11-NEXT: s_and_b32 s5, s5, 0xff +; GFX11-NEXT: s_or_b32 s4, s4, s8 +; GFX11-NEXT: s_mul_i32 s8, s9, 0xffffffe8 +; GFX11-NEXT: s_lshl_b32 s5, s5, 8 +; GFX11-NEXT: s_mul_hi_u32 s8, s9, s8 +; GFX11-NEXT: s_or_b32 s5, s10, s5 +; GFX11-NEXT: s_add_i32 s9, s9, s8 +; GFX11-NEXT: s_and_b32 s10, s11, 0xff +; GFX11-NEXT: s_mul_hi_u32 s8, s4, s9 +; GFX11-NEXT: s_and_b32 s10, 0xffff, s10 +; GFX11-NEXT: s_mul_i32 s8, s8, 24 +; GFX11-NEXT: s_and_b32 s5, 0xffff, s5 +; GFX11-NEXT: s_lshl_b32 s10, s10, 16 +; GFX11-NEXT: s_sub_i32 s4, s4, s8 +; GFX11-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX11-NEXT: s_and_b32 s6, 0xffff, s6 +; GFX11-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX11-NEXT: s_and_b32 s7, 0xffff, s7 +; GFX11-NEXT: s_or_b32 s5, s5, s10 +; GFX11-NEXT: s_cmp_ge_u32 s4, 24 +; GFX11-NEXT: s_cselect_b32 s8, 1, 0 +; GFX11-NEXT: s_sub_i32 s10, s4, 24 +; GFX11-NEXT: s_cmp_lg_u32 s8, 0 +; GFX11-NEXT: s_cselect_b32 s4, s10, s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_ge_u32 s4, 24 +; GFX11-NEXT: s_cselect_b32 s8, 1, 0 +; GFX11-NEXT: s_sub_i32 s10, s4, 24 +; GFX11-NEXT: s_cmp_lg_u32 s8, 0 +; GFX11-NEXT: s_cselect_b32 s4, s10, s4 +; GFX11-NEXT: s_lshl_b32 s6, s6, 17 ; GFX11-NEXT: s_lshl_b32 s0, s0, 1 -; GFX11-NEXT: s_or_b32 s3, s3, s8 -; GFX11-NEXT: s_or_b32 s0, s7, s0 -; GFX11-NEXT: v_mul_lo_u32 v1, v1, 24 -; GFX11-NEXT: v_mul_lo_u32 v0, v0, 24 -; GFX11-NEXT: s_and_b32 s9, s9, 0xff +; GFX11-NEXT: s_sub_i32 s8, 23, s4 +; GFX11-NEXT: s_or_b32 s0, s6, s0 +; GFX11-NEXT: s_mul_hi_u32 s6, s5, s9 +; GFX11-NEXT: s_lshl_b32 s0, s0, s8 +; GFX11-NEXT: s_mul_i32 s6, s6, 24 +; GFX11-NEXT: s_lshr_b32 s2, s2, s4 +; GFX11-NEXT: s_sub_i32 s4, s5, s6 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_cmp_ge_u32 s4, 24 +; GFX11-NEXT: s_cselect_b32 s2, 1, 0 +; GFX11-NEXT: s_sub_i32 s5, s4, 24 +; GFX11-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-NEXT: s_cselect_b32 s2, s5, s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_ge_u32 s2, 24 +; GFX11-NEXT: s_cselect_b32 s4, 1, 0 +; GFX11-NEXT: s_sub_i32 s5, s2, 24 +; GFX11-NEXT: s_cmp_lg_u32 s4, 0 +; GFX11-NEXT: s_cselect_b32 s2, s5, s2 +; GFX11-NEXT: s_lshl_b32 s4, s7, 17 ; GFX11-NEXT: s_lshl_b32 s1, s1, 1 -; GFX11-NEXT: s_lshl_b32 s9, s9, 17 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_sub_nc_u32_e32 v1, s4, v1 -; GFX11-NEXT: v_sub_nc_u32_e32 v0, s5, v0 -; GFX11-NEXT: s_lshl_b32 s4, s10, 8 -; GFX11-NEXT: s_lshl_b32 s5, s11, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s4 -; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v1 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1 -; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v0 -; GFX11-NEXT: s_or_b32 s2, s2, s5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo -; GFX11-NEXT: v_sub_nc_u32_e32 v2, 23, v1 -; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; GFX11-NEXT: v_lshrrev_b32_e64 v1, v1, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX11-NEXT: v_lshl_or_b32 v1, s0, v2, v1 -; GFX11-NEXT: s_or_b32 s0, s9, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v0 -; GFX11-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX11-NEXT: v_bfe_u32 v2, v1, 8, 8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX11-NEXT: v_lshrrev_b32_e64 v0, v0, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX11-NEXT: v_lshl_or_b32 v0, s0, v3, v0 -; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_and_or_b32 v1, 0xff, v1, v2 -; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v0 -; GFX11-NEXT: v_bfe_u32 v5, v0, 8, 8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX11-NEXT: v_bfe_u32 v0, v0, 16, 8 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_lshl_or_b32 v0, v0, 8, v5 -; GFX11-NEXT: v_or3_b32 v1, v1, v3, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_readfirstlane_b32 s1, v0 -; GFX11-NEXT: v_readfirstlane_b32 s0, v1 +; GFX11-NEXT: s_sub_i32 s5, 23, s2 +; GFX11-NEXT: s_or_b32 s1, s4, s1 +; GFX11-NEXT: s_lshr_b32 s2, s3, s2 +; GFX11-NEXT: s_lshl_b32 s1, s1, s5 +; GFX11-NEXT: s_and_b32 s3, s0, 0xff +; GFX11-NEXT: s_or_b32 s1, s1, s2 +; GFX11-NEXT: s_bfe_u32 s2, s0, 0x80008 +; GFX11-NEXT: s_bfe_u32 s0, s0, 0x80010 +; GFX11-NEXT: s_lshl_b32 s2, s2, 8 +; GFX11-NEXT: s_lshl_b32 s0, s0, 16 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_and_b32 s3, s1, 0xff +; GFX11-NEXT: s_or_b32 s0, s2, s0 +; GFX11-NEXT: s_lshl_b32 s2, s3, 24 +; GFX11-NEXT: s_bfe_u32 s3, s1, 0x80010 +; GFX11-NEXT: s_bfe_u32 s1, s1, 0x80008 +; GFX11-NEXT: s_lshl_b32 s3, s3, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_or_b32 s1, s1, s3 ; GFX11-NEXT: ; return to shader part epilog %lhs = bitcast i48 %lhs.arg to <2 x i24> %rhs = bitcast i48 %rhs.arg to <2 x i24> @@ -2336,33 +2505,35 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6 -; GFX6-NEXT: v_not_b32_e32 v7, 23 ; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4 +; GFX6-NEXT: v_not_b32_e32 v7, 23 ; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5 ; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1 -; GFX6-NEXT: v_mul_lo_u32 v8, v6, v7 +; GFX6-NEXT: v_readfirstlane_b32 s4, v6 +; GFX6-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX6-NEXT: v_mul_hi_u32 v6, v6, s5 ; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 -; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6 -; GFX6-NEXT: v_mul_lo_u32 v8, v8, 24 +; GFX6-NEXT: v_readfirstlane_b32 s5, v6 +; GFX6-NEXT: s_add_i32 s4, s4, s5 +; GFX6-NEXT: v_mul_hi_u32 v6, v4, s4 +; GFX6-NEXT: v_mul_hi_u32 v8, v5, s4 ; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24 -; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v8 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v4, v7 +; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6 +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v4, v7 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v4, v7 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v4, v7 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 23, v4 -; GFX6-NEXT: v_and_b32_e32 v8, 0xffffff, v8 +; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4 +; GFX6-NEXT: v_and_b32_e32 v6, 0xffffff, v6 +; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0 +; GFX6-NEXT: v_mul_lo_u32 v6, v8, 24 ; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6 @@ -2385,33 +2556,35 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6 -; GFX8-NEXT: v_not_b32_e32 v7, 23 ; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4 +; GFX8-NEXT: v_not_b32_e32 v7, 23 ; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5 ; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1 -; GFX8-NEXT: v_mul_lo_u32 v8, v6, v7 +; GFX8-NEXT: v_readfirstlane_b32 s4, v6 +; GFX8-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX8-NEXT: v_mul_hi_u32 v6, v6, s5 ; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8 -; GFX8-NEXT: v_mul_hi_u32 v8, v4, v6 -; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6 -; GFX8-NEXT: v_mul_lo_u32 v8, v8, 24 +; GFX8-NEXT: v_readfirstlane_b32 s5, v6 +; GFX8-NEXT: s_add_i32 s4, s4, s5 +; GFX8-NEXT: v_mul_hi_u32 v6, v4, s4 +; GFX8-NEXT: v_mul_hi_u32 v8, v5, s4 ; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24 -; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v8 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v7 +; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6 +; GFX8-NEXT: v_add_u32_e32 v6, vcc, v4, v7 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v7 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX8-NEXT: v_add_u32_e32 v6, vcc, v4, v7 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 23, v4 -; GFX8-NEXT: v_and_b32_e32 v8, 0xffffff, v8 +; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4 +; GFX8-NEXT: v_and_b32_e32 v6, 0xffffff, v6 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, v6, v0 +; GFX8-NEXT: v_mul_lo_u32 v6, v8, 24 ; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4 -; GFX8-NEXT: v_lshlrev_b32_e32 v0, v8, v0 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6 @@ -2434,24 +2607,23 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6 -; GFX9-NEXT: v_not_b32_e32 v7, 23 ; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5 +; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1 -; GFX9-NEXT: v_mul_hi_u32 v7, v6, v7 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v7 -; GFX9-NEXT: v_mul_hi_u32 v7, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6 -; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24 +; GFX9-NEXT: v_readfirstlane_b32 s4, v6 +; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX9-NEXT: s_add_i32 s4, s4, s5 +; GFX9-NEXT: v_mul_hi_u32 v6, v4, s4 +; GFX9-NEXT: v_mul_hi_u32 v7, v5, s4 ; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24 -; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7 -; GFX9-NEXT: v_sub_u32_e32 v5, v5, v6 +; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24 +; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6 ; GFX9-NEXT: v_add_u32_e32 v6, 0xffffffe8, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc @@ -2463,9 +2635,10 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2 -; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v5 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7 +; GFX9-NEXT: v_add_u32_e32 v4, 0xffffffe8, v2 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_add_u32_e32 v4, 0xffffffe8, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc @@ -2489,15 +2662,16 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1 ; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GFX10-NEXT: v_mul_lo_u32 v7, 0xffffffe8, v6 -; GFX10-NEXT: v_mul_hi_u32 v7, v6, v7 -; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v7 -; GFX10-NEXT: v_mul_hi_u32 v7, v4, v6 -; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6 -; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24 +; GFX10-NEXT: v_readfirstlane_b32 s4, v6 +; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8 +; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX10-NEXT: s_add_i32 s4, s4, s5 +; GFX10-NEXT: v_mul_hi_u32 v6, v4, s4 +; GFX10-NEXT: v_mul_hi_u32 v7, v5, s4 ; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6 +; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24 +; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6 +; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v5 @@ -2535,29 +2709,29 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_lshlrev_b32 v1, 1, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GFX11-NEXT: v_mul_lo_u32 v7, 0xffffffe8, v6 +; GFX11-NEXT: v_readfirstlane_b32 s0, v6 +; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1 +; GFX11-NEXT: s_add_i32 s0, s0, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mul_hi_u32 v6, v4, s0 +; GFX11-NEXT: v_mul_lo_u32 v6, v6, 24 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_hi_u32 v7, v6, v7 -; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_hi_u32 v7, v4, v6 +; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v6 +; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4 +; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_and_b32 v5, 0xffffff, v5 +; GFX11-NEXT: v_mul_hi_u32 v7, v5, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4 ; GFX11-NEXT: v_mul_lo_u32 v7, v7, 24 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v7 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mul_hi_u32 v6, v5, v6 -; GFX11-NEXT: v_mul_lo_u32 v6, v6, 24 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v6 -; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5 -; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4 +; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v7 ; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo ; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5 @@ -3463,12 +3637,12 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, < ; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s2, s4, s5 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX9-NEXT: s_lshr_b32 s2, s1, 16 -; GFX9-NEXT: s_and_b32 s1, s1, 0xffff +; GFX9-NEXT: s_and_b32 s2, s1, 0xffff +; GFX9-NEXT: s_lshr_b32 s1, s1, 16 ; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_lshr_b32 s1, s1, s3 -; GFX9-NEXT: s_lshr_b32 s2, s2, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 +; GFX9-NEXT: s_lshr_b32 s2, s2, s3 +; GFX9-NEXT: s_lshr_b32 s1, s1, s4 +; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1 ; GFX9-NEXT: s_or_b32 s0, s0, s1 ; GFX9-NEXT: ; return to shader part epilog ; @@ -3484,13 +3658,13 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, < ; GFX10-NEXT: s_lshr_b32 s5, s2, 16 ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s2, s3, s5 -; GFX10-NEXT: s_lshr_b32 s3, s1, 16 -; GFX10-NEXT: s_and_b32 s1, s1, 0xffff +; GFX10-NEXT: s_and_b32 s3, s1, 0xffff +; GFX10-NEXT: s_lshr_b32 s1, s1, 16 ; GFX10-NEXT: s_lshr_b32 s5, s4, 16 -; GFX10-NEXT: s_lshr_b32 s1, s1, s4 -; GFX10-NEXT: s_lshr_b32 s3, s3, s5 +; GFX10-NEXT: s_lshr_b32 s3, s3, s4 +; GFX10-NEXT: s_lshr_b32 s1, s1, s5 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1 ; GFX10-NEXT: s_or_b32 s0, s0, s1 ; GFX10-NEXT: ; return to shader part epilog ; @@ -3506,13 +3680,13 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, < ; GFX11-NEXT: s_lshr_b32 s5, s2, 16 ; GFX11-NEXT: s_lshl_b32 s0, s0, s2 ; GFX11-NEXT: s_lshl_b32 s2, s3, s5 -; GFX11-NEXT: s_lshr_b32 s3, s1, 16 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: s_and_b32 s3, s1, 0xffff +; GFX11-NEXT: s_lshr_b32 s1, s1, 16 ; GFX11-NEXT: s_lshr_b32 s5, s4, 16 -; GFX11-NEXT: s_lshr_b32 s1, s1, s4 -; GFX11-NEXT: s_lshr_b32 s3, s3, s5 +; GFX11-NEXT: s_lshr_b32 s3, s3, s4 +; GFX11-NEXT: s_lshr_b32 s1, s1, s5 ; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX11-NEXT: s_pack_ll_b32_b16 s1, s3, s1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -3931,12 +4105,12 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, < ; GFX9-NEXT: s_andn2_b32 s1, 0xf000f, s1 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1] ; GFX9-NEXT: v_pk_lshlrev_b16 v0, s1, v0 -; GFX9-NEXT: s_lshr_b32 s1, s0, 16 -; GFX9-NEXT: s_and_b32 s0, s0, 0xffff +; GFX9-NEXT: s_and_b32 s1, s0, 0xffff +; GFX9-NEXT: s_lshr_b32 s0, s0, 16 ; GFX9-NEXT: s_lshr_b32 s3, s2, 16 -; GFX9-NEXT: s_lshr_b32 s0, s0, s2 -; GFX9-NEXT: s_lshr_b32 s1, s1, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX9-NEXT: s_lshr_b32 s1, s1, s2 +; GFX9-NEXT: s_lshr_b32 s0, s0, s3 +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0 ; GFX9-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; @@ -3945,13 +4119,13 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, < ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1] ; GFX10-NEXT: s_and_b32 s2, s1, 0xf000f ; GFX10-NEXT: s_andn2_b32 s1, 0xf000f, s1 -; GFX10-NEXT: s_lshr_b32 s3, s0, 16 -; GFX10-NEXT: s_and_b32 s0, s0, 0xffff +; GFX10-NEXT: s_and_b32 s3, s0, 0xffff +; GFX10-NEXT: s_lshr_b32 s0, s0, 16 ; GFX10-NEXT: s_lshr_b32 s4, s2, 16 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, s1, v0 -; GFX10-NEXT: s_lshr_b32 s0, s0, s2 -; GFX10-NEXT: s_lshr_b32 s1, s3, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX10-NEXT: s_lshr_b32 s1, s3, s2 +; GFX10-NEXT: s_lshr_b32 s0, s0, s4 +; GFX10-NEXT: s_pack_ll_b32_b16 s0, s1, s0 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; @@ -3960,14 +4134,14 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, < ; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1] ; GFX11-NEXT: s_and_b32 s2, s1, 0xf000f ; GFX11-NEXT: s_and_not1_b32 s1, 0xf000f, s1 -; GFX11-NEXT: s_lshr_b32 s3, s0, 16 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_and_b32 s3, s0, 0xffff +; GFX11-NEXT: s_lshr_b32 s0, s0, 16 ; GFX11-NEXT: s_lshr_b32 s4, s2, 16 ; GFX11-NEXT: v_pk_lshlrev_b16 v0, s1, v0 -; GFX11-NEXT: s_lshr_b32 s0, s0, s2 -; GFX11-NEXT: s_lshr_b32 s1, s3, s4 +; GFX11-NEXT: s_lshr_b32 s1, s3, s2 +; GFX11-NEXT: s_lshr_b32 s0, s0, s4 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX11-NEXT: s_pack_ll_b32_b16 s0, s1, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -4054,12 +4228,12 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX9-NEXT: s_lshl_b32 s0, s0, s4 ; GFX9-NEXT: s_lshl_b32 s4, s7, s8 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_and_b32 s2, s2, 0xffff +; GFX9-NEXT: s_and_b32 s4, s2, 0xffff +; GFX9-NEXT: s_lshr_b32 s2, s2, 16 ; GFX9-NEXT: s_lshr_b32 s7, s6, 16 -; GFX9-NEXT: s_lshr_b32 s2, s2, s6 -; GFX9-NEXT: s_lshr_b32 s4, s4, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 +; GFX9-NEXT: s_lshr_b32 s4, s4, s6 +; GFX9-NEXT: s_lshr_b32 s2, s2, s7 +; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2 ; GFX9-NEXT: s_or_b32 s0, s0, s2 ; GFX9-NEXT: s_and_b32 s2, s5, 0xf000f ; GFX9-NEXT: s_andn2_b32 s4, 0xf000f, s5 @@ -4072,11 +4246,11 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX9-NEXT: s_lshl_b32 s1, s1, s4 ; GFX9-NEXT: s_lshl_b32 s4, s5, s6 ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_and_b32 s3, s3, 0xffff +; GFX9-NEXT: s_and_b32 s4, s3, 0xffff +; GFX9-NEXT: s_lshr_b32 s3, s3, 16 ; GFX9-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-NEXT: s_lshr_b32 s2, s3, s2 -; GFX9-NEXT: s_lshr_b32 s3, s4, s5 +; GFX9-NEXT: s_lshr_b32 s2, s4, s2 +; GFX9-NEXT: s_lshr_b32 s3, s3, s5 ; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 ; GFX9-NEXT: s_or_b32 s1, s1, s2 ; GFX9-NEXT: s_lshr_b32 s2, s0, 16 @@ -4098,13 +4272,13 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX10-NEXT: s_lshr_b32 s8, s4, 16 ; GFX10-NEXT: s_lshl_b32 s0, s0, s4 ; GFX10-NEXT: s_lshl_b32 s4, s6, s8 -; GFX10-NEXT: s_lshr_b32 s6, s2, 16 -; GFX10-NEXT: s_and_b32 s2, s2, 0xffff +; GFX10-NEXT: s_and_b32 s6, s2, 0xffff +; GFX10-NEXT: s_lshr_b32 s2, s2, 16 ; GFX10-NEXT: s_lshr_b32 s8, s7, 16 -; GFX10-NEXT: s_lshr_b32 s2, s2, s7 -; GFX10-NEXT: s_lshr_b32 s6, s6, s8 +; GFX10-NEXT: s_lshr_b32 s6, s6, s7 +; GFX10-NEXT: s_lshr_b32 s2, s2, s8 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6 +; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s2 ; GFX10-NEXT: s_and_b32 s4, s5, 0xf000f ; GFX10-NEXT: s_or_b32 s0, s0, s2 ; GFX10-NEXT: s_lshr_b32 s2, s1, 16 @@ -4116,13 +4290,13 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX10-NEXT: s_lshr_b32 s6, s2, 16 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 ; GFX10-NEXT: s_lshl_b32 s2, s5, s6 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_and_b32 s3, s3, 0xffff +; GFX10-NEXT: s_and_b32 s5, s3, 0xffff +; GFX10-NEXT: s_lshr_b32 s3, s3, 16 ; GFX10-NEXT: s_lshr_b32 s6, s4, 16 -; GFX10-NEXT: s_lshr_b32 s3, s3, s4 -; GFX10-NEXT: s_lshr_b32 s4, s5, s6 +; GFX10-NEXT: s_lshr_b32 s4, s5, s4 +; GFX10-NEXT: s_lshr_b32 s3, s3, s6 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4 +; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s3 ; GFX10-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-NEXT: s_and_b32 s0, s0, 0xffff ; GFX10-NEXT: s_lshl_b32 s3, s3, 16 @@ -4143,13 +4317,13 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX11-NEXT: s_lshr_b32 s8, s4, 16 ; GFX11-NEXT: s_lshl_b32 s0, s0, s4 ; GFX11-NEXT: s_lshl_b32 s4, s6, s8 -; GFX11-NEXT: s_lshr_b32 s6, s2, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_and_b32 s6, s2, 0xffff +; GFX11-NEXT: s_lshr_b32 s2, s2, 16 ; GFX11-NEXT: s_lshr_b32 s8, s7, 16 -; GFX11-NEXT: s_lshr_b32 s2, s2, s7 -; GFX11-NEXT: s_lshr_b32 s6, s6, s8 +; GFX11-NEXT: s_lshr_b32 s6, s6, s7 +; GFX11-NEXT: s_lshr_b32 s2, s2, s8 ; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s6 +; GFX11-NEXT: s_pack_ll_b32_b16 s2, s6, s2 ; GFX11-NEXT: s_and_b32 s4, s5, 0xf000f ; GFX11-NEXT: s_or_b32 s0, s0, s2 ; GFX11-NEXT: s_lshr_b32 s2, s1, 16 @@ -4162,13 +4336,13 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX11-NEXT: s_lshr_b32 s6, s2, 16 ; GFX11-NEXT: s_lshl_b32 s1, s1, s2 ; GFX11-NEXT: s_lshl_b32 s2, s5, s6 -; GFX11-NEXT: s_lshr_b32 s5, s3, 16 -; GFX11-NEXT: s_and_b32 s3, s3, 0xffff +; GFX11-NEXT: s_and_b32 s5, s3, 0xffff +; GFX11-NEXT: s_lshr_b32 s3, s3, 16 ; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s3, s3, s4 -; GFX11-NEXT: s_lshr_b32 s4, s5, s6 +; GFX11-NEXT: s_lshr_b32 s4, s5, s4 +; GFX11-NEXT: s_lshr_b32 s3, s3, s6 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s2 -; GFX11-NEXT: s_pack_ll_b32_b16 s2, s3, s4 +; GFX11-NEXT: s_pack_ll_b32_b16 s2, s4, s3 ; GFX11-NEXT: s_lshr_b32 s3, s0, 16 ; GFX11-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-NEXT: s_lshl_b32 s3, s3, 16 @@ -4416,12 +4590,12 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX9-NEXT: s_lshl_b32 s0, s0, s4 ; GFX9-NEXT: s_lshl_b32 s4, s7, s8 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_and_b32 s2, s2, 0xffff +; GFX9-NEXT: s_and_b32 s4, s2, 0xffff +; GFX9-NEXT: s_lshr_b32 s2, s2, 16 ; GFX9-NEXT: s_lshr_b32 s7, s6, 16 -; GFX9-NEXT: s_lshr_b32 s2, s2, s6 -; GFX9-NEXT: s_lshr_b32 s4, s4, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 +; GFX9-NEXT: s_lshr_b32 s4, s4, s6 +; GFX9-NEXT: s_lshr_b32 s2, s2, s7 +; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2 ; GFX9-NEXT: s_or_b32 s0, s0, s2 ; GFX9-NEXT: s_and_b32 s2, s5, 0xf000f ; GFX9-NEXT: s_andn2_b32 s4, 0xf000f, s5 @@ -4434,11 +4608,11 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX9-NEXT: s_lshl_b32 s1, s1, s4 ; GFX9-NEXT: s_lshl_b32 s4, s5, s6 ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_and_b32 s3, s3, 0xffff +; GFX9-NEXT: s_and_b32 s4, s3, 0xffff +; GFX9-NEXT: s_lshr_b32 s3, s3, 16 ; GFX9-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-NEXT: s_lshr_b32 s2, s3, s2 -; GFX9-NEXT: s_lshr_b32 s3, s4, s5 +; GFX9-NEXT: s_lshr_b32 s2, s4, s2 +; GFX9-NEXT: s_lshr_b32 s3, s3, s5 ; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 ; GFX9-NEXT: s_or_b32 s1, s1, s2 ; GFX9-NEXT: ; return to shader part epilog @@ -4455,30 +4629,30 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX10-NEXT: s_lshr_b32 s8, s4, 16 ; GFX10-NEXT: s_lshl_b32 s0, s0, s4 ; GFX10-NEXT: s_lshl_b32 s4, s6, s8 -; GFX10-NEXT: s_lshr_b32 s6, s2, 16 +; GFX10-NEXT: s_and_b32 s6, s2, 0xffff ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 ; GFX10-NEXT: s_lshr_b32 s4, s1, 16 -; GFX10-NEXT: s_and_b32 s2, s2, 0xffff +; GFX10-NEXT: s_lshr_b32 s2, s2, 16 ; GFX10-NEXT: s_lshr_b32 s8, s7, 16 ; GFX10-NEXT: s_lshl_b32 s1, s1, 0x10001 ; GFX10-NEXT: s_lshl_b32 s4, s4, 1 -; GFX10-NEXT: s_lshr_b32 s2, s2, s7 -; GFX10-NEXT: s_lshr_b32 s6, s6, s8 +; GFX10-NEXT: s_lshr_b32 s6, s6, s7 +; GFX10-NEXT: s_lshr_b32 s2, s2, s8 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4 ; GFX10-NEXT: s_andn2_b32 s4, 0xf000f, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6 +; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s2 ; GFX10-NEXT: s_and_b32 s6, s5, 0xf000f ; GFX10-NEXT: s_lshr_b32 s5, s1, 16 ; GFX10-NEXT: s_lshr_b32 s7, s4, 16 ; GFX10-NEXT: s_lshl_b32 s1, s1, s4 ; GFX10-NEXT: s_lshl_b32 s4, s5, s7 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_and_b32 s3, s3, 0xffff +; GFX10-NEXT: s_and_b32 s5, s3, 0xffff +; GFX10-NEXT: s_lshr_b32 s3, s3, 16 ; GFX10-NEXT: s_lshr_b32 s7, s6, 16 -; GFX10-NEXT: s_lshr_b32 s3, s3, s6 -; GFX10-NEXT: s_lshr_b32 s5, s5, s7 +; GFX10-NEXT: s_lshr_b32 s5, s5, s6 +; GFX10-NEXT: s_lshr_b32 s3, s3, s7 ; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 +; GFX10-NEXT: s_pack_ll_b32_b16 s3, s5, s3 ; GFX10-NEXT: s_or_b32 s0, s0, s2 ; GFX10-NEXT: s_or_b32 s1, s1, s3 ; GFX10-NEXT: ; return to shader part epilog @@ -4495,30 +4669,30 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX11-NEXT: s_lshr_b32 s8, s4, 16 ; GFX11-NEXT: s_lshl_b32 s0, s0, s4 ; GFX11-NEXT: s_lshl_b32 s4, s6, s8 -; GFX11-NEXT: s_lshr_b32 s6, s2, 16 +; GFX11-NEXT: s_and_b32 s6, s2, 0xffff ; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s4 ; GFX11-NEXT: s_lshr_b32 s4, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshr_b32 s2, s2, 16 ; GFX11-NEXT: s_lshr_b32 s8, s7, 16 ; GFX11-NEXT: s_lshl_b32 s1, s1, 0x10001 ; GFX11-NEXT: s_lshl_b32 s4, s4, 1 -; GFX11-NEXT: s_lshr_b32 s2, s2, s7 -; GFX11-NEXT: s_lshr_b32 s6, s6, s8 +; GFX11-NEXT: s_lshr_b32 s6, s6, s7 +; GFX11-NEXT: s_lshr_b32 s2, s2, s8 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4 ; GFX11-NEXT: s_and_not1_b32 s4, 0xf000f, s5 -; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s6 +; GFX11-NEXT: s_pack_ll_b32_b16 s2, s6, s2 ; GFX11-NEXT: s_and_b32 s6, s5, 0xf000f ; GFX11-NEXT: s_lshr_b32 s5, s1, 16 ; GFX11-NEXT: s_lshr_b32 s7, s4, 16 ; GFX11-NEXT: s_lshl_b32 s1, s1, s4 ; GFX11-NEXT: s_lshl_b32 s4, s5, s7 -; GFX11-NEXT: s_lshr_b32 s5, s3, 16 -; GFX11-NEXT: s_and_b32 s3, s3, 0xffff +; GFX11-NEXT: s_and_b32 s5, s3, 0xffff +; GFX11-NEXT: s_lshr_b32 s3, s3, 16 ; GFX11-NEXT: s_lshr_b32 s7, s6, 16 -; GFX11-NEXT: s_lshr_b32 s3, s3, s6 -; GFX11-NEXT: s_lshr_b32 s5, s5, s7 +; GFX11-NEXT: s_lshr_b32 s5, s5, s6 +; GFX11-NEXT: s_lshr_b32 s3, s3, s7 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s5 +; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s3 ; GFX11-NEXT: s_or_b32 s0, s0, s2 ; GFX11-NEXT: s_or_b32 s1, s1, s3 ; GFX11-NEXT: ; return to shader part epilog @@ -5026,60 +5200,67 @@ define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64 define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg %amt) { ; GFX6-LABEL: v_fshr_i64_svs: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_not_b32 s3, s2 -; GFX6-NEXT: s_and_b32 s2, s2, 63 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s2 +; GFX6-NEXT: s_not_b32 s3, s2 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s3 -; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX6-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX6-NEXT: s_and_b32 s2, s2, 63 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s2 +; GFX6-NEXT: v_mov_b32_e32 v3, s1 +; GFX6-NEXT: v_mov_b32_e32 v2, s0 +; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX6-NEXT: v_or_b32_e32 v1, v3, v1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_fshr_i64_svs: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s3, s2 -; GFX8-NEXT: s_and_b32 s2, s2, 63 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX8-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1] +; GFX8-NEXT: s_not_b32 s3, s2 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s3 -; GFX8-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX8-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX8-NEXT: s_and_b32 s2, s2, 63 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX8-NEXT: v_or_b32_e32 v1, v3, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_fshr_i64_svs: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s3, s2 -; GFX9-NEXT: s_and_b32 s2, s2, 63 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX9-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1] +; GFX9-NEXT: s_not_b32 s3, s2 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s3 -; GFX9-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX9-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX9-NEXT: s_and_b32 s2, s2, 63 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX9-NEXT: v_or_b32_e32 v1, v3, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_fshr_i64_svs: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_and_b32 s3, s2, 63 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX10-NEXT: v_lshrrev_b64 v[0:1], s3, v[0:1] -; GFX10-NEXT: s_not_b32 s2, s2 -; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 -; GFX10-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX10-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX10-NEXT: s_not_b32 s3, s2 +; GFX10-NEXT: s_and_b32 s2, s2, 63 +; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s3 +; GFX10-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1] +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_or_b32_e32 v1, v3, v1 +; GFX10-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_fshr_i64_svs: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s3, s2, 63 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 -; GFX11-NEXT: v_lshrrev_b64 v[0:1], s3, v[0:1] -; GFX11-NEXT: s_not_b32 s2, s2 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX11-NEXT: s_not_b32 s3, s2 +; GFX11-NEXT: s_and_b32 s2, s2, 63 +; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s3 +; GFX11-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1] +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_or_b32_e32 v1, v3, v1 +; GFX11-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX11-NEXT: ; return to shader part epilog %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt) %cast = bitcast i64 %result to <2 x float> @@ -5091,30 +5272,36 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg ; GFX6: ; %bb.0: ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GFX6-NEXT: s_andn2_b32 s3, 63, s2 -; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s3 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 -; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX6-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s3 +; GFX6-NEXT: v_mov_b32_e32 v3, s1 +; GFX6-NEXT: v_mov_b32_e32 v2, s0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_fshr_i64_vss: ; GFX8: ; %bb.0: ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX8-NEXT: s_andn2_b32 s3, 63, s2 -; GFX8-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1] ; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 -; GFX8-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX8-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX8-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_fshr_i64_vss: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX9-NEXT: s_andn2_b32 s3, 63, s2 -; GFX9-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1] ; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 -; GFX9-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX9-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX9-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_fshr_i64_vss: @@ -5122,9 +5309,11 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: s_andn2_b32 s3, 63, s2 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1] -; GFX10-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX10-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_fshr_i64_vss: @@ -5132,11 +5321,12 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: s_and_not1_b32 s3, 63, s2 ; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1] -; GFX11-NEXT: v_or_b32_e32 v0, s0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX11-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX11-NEXT: ; return to shader part epilog %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt) %cast = bitcast i64 %result to <2 x float> @@ -6084,37 +6274,43 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] ; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], s12 ; GFX6-NEXT: s_cmp_lg_u32 s13, 0 -; GFX6-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 -; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[6:7] +; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] ; GFX6-NEXT: s_cmp_lg_u32 s14, 0 -; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX6-NEXT: s_and_b32 s0, s4, 0x7f -; GFX6-NEXT: s_sub_i32 s1, s0, 64 -; GFX6-NEXT: s_sub_i32 s4, 64, s0 -; GFX6-NEXT: s_cmp_lt_u32 s0, 64 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 -; GFX6-NEXT: s_cmp_eq_u32 s0, 0 -; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s0 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 -; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s0 -; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s1 -; GFX6-NEXT: s_and_b32 s0, 1, s5 +; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX6-NEXT: s_and_b32 s4, s4, 0x7f +; GFX6-NEXT: s_sub_i32 s5, s4, 64 +; GFX6-NEXT: s_sub_i32 s6, 64, s4 +; GFX6-NEXT: s_cmp_lt_u32 s4, 64 +; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s4, 0 +; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s4 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s6 +; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s4 +; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s5 +; GFX6-NEXT: s_cmp_lg_u32 s7, 0 ; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX6-NEXT: s_and_b32 s0, 1, s6 +; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc -; GFX6-NEXT: v_or_b32_e32 v0, s10, v0 -; GFX6-NEXT: v_or_b32_e32 v1, s11, v1 -; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX6-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: s_cmp_lg_u32 s7, 0 +; GFX6-NEXT: v_mov_b32_e32 v1, s1 +; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 +; GFX6-NEXT: v_mov_b32_e32 v2, s2 +; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX6-NEXT: v_mov_b32_e32 v3, s3 +; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX6-NEXT: v_or_b32_e32 v3, v3, v5 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_fshr_i128_svs: @@ -6137,37 +6333,43 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] ; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], s12 ; GFX8-NEXT: s_cmp_lg_u32 s13, 0 -; GFX8-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 -; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[6:7] +; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 +; GFX8-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] ; GFX8-NEXT: s_cmp_lg_u32 s14, 0 -; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX8-NEXT: s_and_b32 s0, s4, 0x7f -; GFX8-NEXT: s_sub_i32 s1, s0, 64 -; GFX8-NEXT: s_sub_i32 s4, 64, s0 -; GFX8-NEXT: s_cmp_lt_u32 s0, 64 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 -; GFX8-NEXT: s_cmp_eq_u32 s0, 0 -; GFX8-NEXT: v_lshrrev_b64 v[4:5], s0, v[0:1] -; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 -; GFX8-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] -; GFX8-NEXT: v_lshrrev_b64 v[2:3], s1, v[2:3] -; GFX8-NEXT: s_and_b32 s0, 1, s5 +; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX8-NEXT: s_and_b32 s4, s4, 0x7f +; GFX8-NEXT: s_sub_i32 s5, s4, 64 +; GFX8-NEXT: s_sub_i32 s6, 64, s4 +; GFX8-NEXT: s_cmp_lt_u32 s4, 64 +; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cmp_eq_u32 s4, 0 +; GFX8-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s6, v[2:3] +; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3] +; GFX8-NEXT: v_lshrrev_b64 v[2:3], s5, v[2:3] +; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_and_b32 s0, 1, s6 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] -; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc -; GFX8-NEXT: v_or_b32_e32 v0, s10, v0 -; GFX8-NEXT: v_or_b32_e32 v1, s11, v1 -; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX8-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: s_cmp_lg_u32 s7, 0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX8-NEXT: v_or_b32_e32 v3, v3, v5 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_fshr_i128_svs: @@ -6190,37 +6392,43 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] ; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], s12 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 -; GFX9-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 -; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[6:7] +; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 -; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX9-NEXT: s_and_b32 s0, s4, 0x7f -; GFX9-NEXT: s_sub_i32 s1, s0, 64 -; GFX9-NEXT: s_sub_i32 s4, 64, s0 -; GFX9-NEXT: s_cmp_lt_u32 s0, 64 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 -; GFX9-NEXT: s_cmp_eq_u32 s0, 0 -; GFX9-NEXT: v_lshrrev_b64 v[4:5], s0, v[0:1] -; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 -; GFX9-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] -; GFX9-NEXT: v_lshrrev_b64 v[2:3], s1, v[2:3] -; GFX9-NEXT: s_and_b32 s0, 1, s5 +; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[6:7] +; GFX9-NEXT: s_and_b32 s4, s4, 0x7f +; GFX9-NEXT: s_sub_i32 s5, s4, 64 +; GFX9-NEXT: s_sub_i32 s6, 64, s4 +; GFX9-NEXT: s_cmp_lt_u32 s4, 64 +; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s4, 0 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s6, v[2:3] +; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3] +; GFX9-NEXT: v_lshrrev_b64 v[2:3], s5, v[2:3] +; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX9-NEXT: s_and_b32 s0, 1, s6 +; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc -; GFX9-NEXT: v_or_b32_e32 v0, s10, v0 -; GFX9-NEXT: v_or_b32_e32 v1, s11, v1 -; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: s_cmp_lg_u32 s7, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX9-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX9-NEXT: v_or_b32_e32 v1, v1, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX9-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX9-NEXT: v_or_b32_e32 v3, v3, v5 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_fshr_i128_svs: @@ -6246,34 +6454,40 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX10-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 -; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX10-NEXT: s_and_b32 s0, s4, 0x7f -; GFX10-NEXT: s_sub_i32 s1, 64, s0 -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s0, v[0:1] -; GFX10-NEXT: v_lshlrev_b64 v[6:7], s1, v[2:3] -; GFX10-NEXT: s_sub_i32 s1, s0, 64 -; GFX10-NEXT: s_cmp_lt_u32 s0, 64 -; GFX10-NEXT: v_lshrrev_b64 v[8:9], s1, v[2:3] +; GFX10-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] +; GFX10-NEXT: s_and_b32 s2, s4, 0x7f +; GFX10-NEXT: s_sub_i32 s4, 64, s2 +; GFX10-NEXT: v_lshrrev_b64 v[4:5], s2, v[0:1] +; GFX10-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] +; GFX10-NEXT: s_sub_i32 s3, s2, 64 +; GFX10-NEXT: s_cmp_lt_u32 s2, 64 +; GFX10-NEXT: v_lshrrev_b64 v[8:9], s2, v[2:3] ; GFX10-NEXT: s_cselect_b32 s4, 1, 0 -; GFX10-NEXT: s_cmp_eq_u32 s0, 0 +; GFX10-NEXT: s_cmp_eq_u32 s2, 0 +; GFX10-NEXT: v_lshrrev_b64 v[2:3], s3, v[2:3] ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX10-NEXT: s_cselect_b32 s5, 1, 0 -; GFX10-NEXT: s_and_b32 s1, 1, s4 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 -; GFX10-NEXT: v_lshrrev_b64 v[2:3], s0, v[2:3] -; GFX10-NEXT: s_and_b32 s0, 1, s5 -; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0 -; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 -; GFX10-NEXT: v_or_b32_e32 v0, s8, v0 -; GFX10-NEXT: v_or_b32_e32 v1, s9, v1 +; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX10-NEXT: s_cmp_lg_u32 s5, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX10-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc_lo +; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX10-NEXT: v_mov_b32_e32 v0, s8 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v1, s9 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo +; GFX10-NEXT: v_or_b32_e32 v0, v0, v4 +; GFX10-NEXT: v_or_b32_e32 v1, v1, v5 +; GFX10-NEXT: v_or_b32_e32 v2, v2, v6 +; GFX10-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_fshr_i128_svs: @@ -6299,37 +6513,39 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i ; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX11-NEXT: s_cmp_lg_u32 s5, 0 -; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] -; GFX11-NEXT: s_and_b32 s0, s4, 0x7f +; GFX11-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] +; GFX11-NEXT: s_and_b32 s2, s4, 0x7f ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_sub_i32 s1, 64, s0 -; GFX11-NEXT: v_lshrrev_b64 v[4:5], s0, v[0:1] -; GFX11-NEXT: v_lshlrev_b64 v[6:7], s1, v[2:3] -; GFX11-NEXT: s_sub_i32 s1, s0, 64 -; GFX11-NEXT: s_cmp_lt_u32 s0, 64 -; GFX11-NEXT: v_lshrrev_b64 v[8:9], s1, v[2:3] +; GFX11-NEXT: s_sub_i32 s4, 64, s2 +; GFX11-NEXT: v_lshrrev_b64 v[4:5], s2, v[0:1] +; GFX11-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] +; GFX11-NEXT: s_sub_i32 s3, s2, 64 +; GFX11-NEXT: s_cmp_lt_u32 s2, 64 +; GFX11-NEXT: v_lshrrev_b64 v[8:9], s2, v[2:3] ; GFX11-NEXT: s_cselect_b32 s4, 1, 0 -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 +; GFX11-NEXT: s_cmp_eq_u32 s2, 0 +; GFX11-NEXT: v_lshrrev_b64 v[2:3], s3, v[2:3] ; GFX11-NEXT: v_or_b32_e32 v4, v4, v6 -; GFX11-NEXT: s_cselect_b32 s5, 1, 0 -; GFX11-NEXT: s_and_b32 s1, 1, s4 ; GFX11-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 -; GFX11-NEXT: v_lshrrev_b64 v[2:3], s0, v[2:3] -; GFX11-NEXT: s_and_b32 s0, 1, s5 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 -; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v5, v9, v5 -; GFX11-NEXT: v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v3, 0, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX11-NEXT: v_or_b32_e32 v3, s3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_or_b32_e32 v0, s8, v0 -; GFX11-NEXT: v_or_b32_e32 v1, s9, v1 +; GFX11-NEXT: s_cselect_b32 s5, 1, 0 +; GFX11-NEXT: s_cmp_lg_u32 s4, 0 +; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX11-NEXT: s_cmp_lg_u32 s5, 0 +; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5 +; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX11-NEXT: s_cmp_lg_u32 s4, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1 +; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_cndmask_b32 v6, 0, v8 +; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9 +; GFX11-NEXT: v_or_b32_e32 v0, v0, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_or_b32_e32 v1, v1, v5 +; GFX11-NEXT: v_or_b32_e32 v2, v2, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_or_b32_e32 v3, v3, v7 ; GFX11-NEXT: ; return to shader part epilog %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) %cast.result = bitcast i128 %result to <4 x float> @@ -6340,30 +6556,31 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX6-LABEL: v_fshr_i128_vss: ; GFX6: ; %bb.0: ; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; GFX6-NEXT: s_andn2_b32 s5, 0x7f, s4 ; GFX6-NEXT: v_lshl_b64 v[4:5], v[0:1], 1 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1 -; GFX6-NEXT: s_andn2_b32 s5, 0x7f, s4 -; GFX6-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX6-NEXT: s_sub_i32 s6, s5, 64 ; GFX6-NEXT: s_sub_i32 s7, 64, s5 +; GFX6-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX6-NEXT: s_cmp_lt_u32 s5, 64 -; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s7 -; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5 ; GFX6-NEXT: s_cselect_b32 s8, 1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s5, 0 +; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s7 +; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5 ; GFX6-NEXT: s_cselect_b32 s9, 1, 0 ; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s5 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX6-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s6 -; GFX6-NEXT: s_and_b32 s5, 1, s8 -; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 -; GFX6-NEXT: s_and_b32 s5, 1, s9 +; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX6-NEXT: s_cmp_lg_u32 s9, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc -; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX6-NEXT: s_and_b32 s5, s4, 0x7f ; GFX6-NEXT: s_sub_i32 s10, s5, 64 ; GFX6-NEXT: s_sub_i32 s8, 64, s5 @@ -6381,42 +6598,47 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_cmp_lg_u32 s11, 0 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 -; GFX6-NEXT: v_or_b32_e32 v0, s0, v4 -; GFX6-NEXT: v_or_b32_e32 v1, s1, v5 -; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX6-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX6-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: v_mov_b32_e32 v2, s2 +; GFX6-NEXT: v_mov_b32_e32 v1, s1 +; GFX6-NEXT: v_mov_b32_e32 v3, s3 +; GFX6-NEXT: v_or_b32_e32 v0, v4, v0 +; GFX6-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX6-NEXT: v_or_b32_e32 v2, v6, v2 +; GFX6-NEXT: v_or_b32_e32 v3, v7, v3 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_fshr_i128_vss: ; GFX8: ; %bb.0: ; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] +; GFX8-NEXT: s_andn2_b32 s5, 0x7f, s4 ; GFX8-NEXT: v_lshlrev_b64 v[4:5], 1, v[0:1] ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1 -; GFX8-NEXT: s_andn2_b32 s5, 0x7f, s4 -; GFX8-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX8-NEXT: s_sub_i32 s6, s5, 64 ; GFX8-NEXT: s_sub_i32 s7, 64, s5 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX8-NEXT: s_cmp_lt_u32 s5, 64 -; GFX8-NEXT: v_lshrrev_b64 v[0:1], s7, v[4:5] -; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX8-NEXT: s_cselect_b32 s8, 1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s5, 0 +; GFX8-NEXT: v_lshrrev_b64 v[0:1], s7, v[4:5] +; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: v_lshlrev_b64 v[8:9], s5, v[4:5] +; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX8-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], s6, v[4:5] -; GFX8-NEXT: s_and_b32 s5, 1, s8 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 -; GFX8-NEXT: s_and_b32 s5, 1, s9 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: s_and_b32 s5, s4, 0x7f ; GFX8-NEXT: s_sub_i32 s10, s5, 64 ; GFX8-NEXT: s_sub_i32 s8, 64, s5 @@ -6434,42 +6656,47 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 -; GFX8-NEXT: v_or_b32_e32 v0, s0, v4 -; GFX8-NEXT: v_or_b32_e32 v1, s1, v5 -; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX8-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 +; GFX8-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX8-NEXT: v_or_b32_e32 v2, v6, v2 +; GFX8-NEXT: v_or_b32_e32 v3, v7, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_fshr_i128_vss: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] +; GFX9-NEXT: s_andn2_b32 s5, 0x7f, s4 ; GFX9-NEXT: v_lshlrev_b64 v[4:5], 1, v[0:1] ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 31, v1 -; GFX9-NEXT: s_andn2_b32 s5, 0x7f, s4 -; GFX9-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX9-NEXT: s_sub_i32 s6, s5, 64 ; GFX9-NEXT: s_sub_i32 s7, 64, s5 +; GFX9-NEXT: v_or_b32_e32 v2, v2, v0 ; GFX9-NEXT: s_cmp_lt_u32 s5, 64 -; GFX9-NEXT: v_lshrrev_b64 v[0:1], s7, v[4:5] -; GFX9-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX9-NEXT: s_cselect_b32 s8, 1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s5, 0 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], s7, v[4:5] +; GFX9-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: v_lshlrev_b64 v[8:9], s5, v[4:5] +; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX9-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], s6, v[4:5] -; GFX9-NEXT: s_and_b32 s5, 1, s8 -; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 -; GFX9-NEXT: s_and_b32 s5, 1, s9 +; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc +; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc -; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 +; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX9-NEXT: s_and_b32 s5, s4, 0x7f ; GFX9-NEXT: s_sub_i32 s10, s5, 64 ; GFX9-NEXT: s_sub_i32 s8, 64, s5 @@ -6487,13 +6714,17 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX9-NEXT: s_cmp_lg_u32 s12, 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 -; GFX9-NEXT: v_or_b32_e32 v0, s0, v4 -; GFX9-NEXT: v_or_b32_e32 v1, s1, v5 -; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NEXT: v_or_b32_e32 v0, v4, v0 +; GFX9-NEXT: v_or_b32_e32 v1, v5, v1 +; GFX9-NEXT: v_or_b32_e32 v2, v6, v2 +; GFX9-NEXT: v_or_b32_e32 v3, v7, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_fshr_i128_vss: @@ -6502,51 +6733,56 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v1 ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: s_andn2_b32 s5, 0x7f, s4 -; GFX10-NEXT: s_sub_i32 s7, 64, s5 -; GFX10-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX10-NEXT: s_sub_i32 s6, s5, 64 +; GFX10-NEXT: s_sub_i32 s6, 64, s5 +; GFX10-NEXT: s_sub_i32 s7, s5, 64 ; GFX10-NEXT: s_cmp_lt_u32 s5, 64 -; GFX10-NEXT: v_lshrrev_b64 v[4:5], s7, v[0:1] -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 -; GFX10-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] +; GFX10-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s5, 0 ; GFX10-NEXT: v_lshlrev_b64 v[8:9], s5, v[0:1] -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 -; GFX10-NEXT: s_and_b32 s5, 1, s8 -; GFX10-NEXT: v_lshlrev_b64 v[0:1], s6, v[0:1] -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 +; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cmp_lg_u32 s6, 0 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] +; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX10-NEXT: s_cselect_b32 s5, exec_lo, 0 +; GFX10-NEXT: s_cmp_lg_u32 s8, 0 +; GFX10-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1] +; GFX10-NEXT: s_cselect_b32 s6, exec_lo, 0 +; GFX10-NEXT: s_and_b32 s7, s4, 0x7f ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX10-NEXT: s_sub_i32 s12, s7, 64 +; GFX10-NEXT: s_sub_i32 s10, 64, s7 +; GFX10-NEXT: s_cmp_lt_u32 s7, 64 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX10-NEXT: s_and_b32 s5, 1, s9 -; GFX10-NEXT: s_and_b32 s6, s4, 0x7f +; GFX10-NEXT: s_cselect_b32 s13, 1, 0 +; GFX10-NEXT: s_cmp_eq_u32 s7, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, v4, s5 +; GFX10-NEXT: s_cselect_b32 s7, 1, 0 +; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s4 +; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s10 ; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 -; GFX10-NEXT: s_sub_i32 s10, s6, 64 -; GFX10-NEXT: s_sub_i32 s5, 64, s6 -; GFX10-NEXT: s_cmp_lt_u32 s6, 64 -; GFX10-NEXT: s_cselect_b32 s11, 1, 0 -; GFX10-NEXT: s_cmp_eq_u32 s6, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 -; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s4 -; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s5 +; GFX10-NEXT: v_cndmask_b32_e64 v8, v1, v5, s5 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[2:3], s4 -; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] -; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 -; GFX10-NEXT: s_cmp_lg_u32 s11, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo -; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3] -; GFX10-NEXT: s_cmp_lg_u32 s12, 0 +; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s12 +; GFX10-NEXT: s_cmp_lg_u32 s13, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX10-NEXT: s_cmp_lg_u32 s7, 0 +; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] -; GFX10-NEXT: s_cmp_lg_u32 s11, 0 -; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 +; GFX10-NEXT: s_cmp_lg_u32 s13, 0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 -; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 -; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: v_mov_b32_e32 v5, s3 +; GFX10-NEXT: v_mov_b32_e32 v4, s2 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v8, v3, s6 +; GFX10-NEXT: v_or_b32_e32 v0, v6, v0 +; GFX10-NEXT: v_or_b32_e32 v1, v7, v1 +; GFX10-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX10-NEXT: v_or_b32_e32 v3, v3, v5 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_fshr_i128_vss: @@ -6555,50 +6791,57 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v1 ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: s_and_not1_b32 s5, 0x7f, s4 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: s_sub_i32 s7, 64, s5 -; GFX11-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX11-NEXT: s_sub_i32 s6, s5, 64 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_sub_i32 s6, 64, s5 +; GFX11-NEXT: s_sub_i32 s7, s5, 64 ; GFX11-NEXT: s_cmp_lt_u32 s5, 64 -; GFX11-NEXT: v_lshrrev_b64 v[4:5], s7, v[0:1] -; GFX11-NEXT: s_cselect_b32 s8, 1, 0 -; GFX11-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] +; GFX11-NEXT: v_or_b32_e32 v2, v2, v4 +; GFX11-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] +; GFX11-NEXT: s_cselect_b32 s6, 1, 0 ; GFX11-NEXT: s_cmp_eq_u32 s5, 0 ; GFX11-NEXT: v_lshlrev_b64 v[8:9], s5, v[0:1] -; GFX11-NEXT: s_cselect_b32 s9, 1, 0 -; GFX11-NEXT: s_and_b32 s5, 1, s8 -; GFX11-NEXT: v_lshlrev_b64 v[0:1], s6, v[0:1] -; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 +; GFX11-NEXT: s_cselect_b32 s8, 1, 0 +; GFX11-NEXT: s_cmp_lg_u32 s6, 0 +; GFX11-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] +; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX11-NEXT: s_cselect_b32 s5, exec_lo, 0 +; GFX11-NEXT: s_cmp_lg_u32 s8, 0 +; GFX11-NEXT: v_lshlrev_b64 v[0:1], s7, v[0:1] +; GFX11-NEXT: s_cselect_b32 s6, exec_lo, 0 +; GFX11-NEXT: s_and_b32 s7, s4, 0x7f ; GFX11-NEXT: v_or_b32_e32 v4, v4, v6 +; GFX11-NEXT: s_sub_i32 s12, s7, 64 +; GFX11-NEXT: s_sub_i32 s10, 64, s7 +; GFX11-NEXT: s_cmp_lt_u32 s7, 64 ; GFX11-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX11-NEXT: s_and_b32 s5, 1, s9 -; GFX11-NEXT: s_and_b32 s6, s4, 0x7f +; GFX11-NEXT: s_cselect_b32 s13, 1, 0 +; GFX11-NEXT: s_cmp_eq_u32 s7, 0 +; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, v4, s5 +; GFX11-NEXT: s_cselect_b32 s7, 1, 0 +; GFX11-NEXT: s_lshr_b64 s[8:9], s[0:1], s4 +; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s10 ; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5 -; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 -; GFX11-NEXT: s_sub_i32 s10, s6, 64 -; GFX11-NEXT: s_sub_i32 s5, 64, s6 -; GFX11-NEXT: s_cmp_lt_u32 s6, 64 -; GFX11-NEXT: s_cselect_b32 s11, 1, 0 -; GFX11-NEXT: s_cmp_eq_u32 s6, 0 -; GFX11-NEXT: v_dual_cndmask_b32 v2, v0, v2 :: v_dual_cndmask_b32 v3, v1, v3 -; GFX11-NEXT: s_cselect_b32 s12, 1, 0 -; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s4 -; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s5 +; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, v5, s5 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[2:3], s4 -; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] -; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 -; GFX11-NEXT: s_cmp_lg_u32 s11, 0 -; GFX11-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3] -; GFX11-NEXT: s_cmp_lg_u32 s12, 0 +; GFX11-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s12 +; GFX11-NEXT: s_cmp_lg_u32 s13, 0 +; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] +; GFX11-NEXT: s_cmp_lg_u32 s7, 0 +; GFX11-NEXT: v_cndmask_b32_e64 v3, v8, v3, s6 ; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] -; GFX11-NEXT: s_cmp_lg_u32 s11, 0 -; GFX11-NEXT: v_or_b32_e32 v0, s0, v6 +; GFX11-NEXT: s_cmp_lg_u32 s13, 0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 -; GFX11-NEXT: v_or_b32_e32 v1, s1, v7 -; GFX11-NEXT: v_or_b32_e32 v2, s2, v2 -; GFX11-NEXT: v_or_b32_e32 v3, s3, v3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX11-NEXT: v_or_b32_e32 v0, v6, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_or_b32_e32 v1, v7, v1 +; GFX11-NEXT: v_or_b32_e32 v3, v3, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX11-NEXT: ; return to shader part epilog %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) %cast.result = bitcast i128 %result to <4 x float>