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[AMDGPU] Add missing -wwm-regalloc=fast to 4 more tests (NFC) (#184966)

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Adding the missing wwm-regalloc=fast option in 4 more tests
that already specify -sgpr-regalloc=fast and -vgpr-regalloc=fast.
For consistency, the same preference should be applied to the
wwm-regalloc pipeline as well.
This is a follow-up to #184190 which addressed the same issue in
attr-amdgpu-flat-work-group-size-vgpr-limit.ll.
This commit is contained in:
Christudasan Devadasan 2026-03-09 00:09:57 +05:30 committed by GitHub
parent 6365d46654
commit aca4a8f644
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4 changed files with 4 additions and 4 deletions
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2
llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
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@ -4,7 +4,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -early-live-intervals < %s | FileCheck -enable-var-scope --check-prefixes=GREEDY90A %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope --check-prefixes=GREEDY942 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -enable-var-scope --check-prefixes=GREEDY90A-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -sgpr-regalloc=fast -vgpr-regalloc=fast < %s | FileCheck -enable-var-scope --check-prefixes=FAST90A %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck -enable-var-scope --check-prefixes=FAST90A %s
; This is better with 90a

2
llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
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@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -sgpr-regalloc=fast -vgpr-regalloc=fast < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck -check-prefix=GCN %s
; Make sure there's no verifier error from improperly updated
; SlotIndexes if regalloc fast is manually used.

2
llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
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@ -1,6 +1,6 @@
; -enable-misched=false makes the register usage more predictable
; -regalloc=fast just makes the test run faster
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX90A
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX90A
define internal void @use256vgprs() {
%v0 = call i32 asm sideeffect "; def $0", "=v"()

2
llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
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@ -1,6 +1,6 @@
; -enable-misched=false makes the register usage more predictable
; -regalloc=fast just makes the test run faster
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -O0 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX1250
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -O0 -amdgpu-function-calls=false -enable-misched=false -sgpr-regalloc=fast -vgpr-regalloc=fast -wwm-regalloc=fast < %s | FileCheck %s --check-prefixes=GCN,GFX1250
define internal void @use256vgprs_asm() {
%v0 = call i32 asm sideeffect "; def $0", "=v"()