diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index 9c3df1fdc01b..7355b2d8eb81 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -2924,22 +2924,10 @@ let Predicates = [UseHVX] in { def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>; def vzero: PatFrag<(ops), (HexagonVZERO)>; -def VSxtb: OutPatFrag<(ops node:$Vs), - (V6_vshuffvdd (HiVec (V6_vsb $Vs)), - (LoVec (V6_vsb $Vs)), - (A2_tfrsi -2))>; -def VSxth: OutPatFrag<(ops node:$Vs), - (V6_vshuffvdd (HiVec (V6_vsh $Vs)), - (LoVec (V6_vsh $Vs)), - (A2_tfrsi -4))>; -def VZxtb: OutPatFrag<(ops node:$Vs), - (V6_vshuffvdd (HiVec (V6_vzb $Vs)), - (LoVec (V6_vzb $Vs)), - (A2_tfrsi -2))>; -def VZxth: OutPatFrag<(ops node:$Vs), - (V6_vshuffvdd (HiVec (V6_vzh $Vs)), - (LoVec (V6_vzh $Vs)), - (A2_tfrsi -4))>; +def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>; +def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>; +def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>; +def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>; let Predicates = [UseHVX] in { def: Pat<(VecI8 vzero), (V6_vd0)>; diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll index d7574a277dea..ba1d57f04899 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll @@ -4,7 +4,7 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i target triple = "hexagon" ; CHECK-LABEL: danny: -; CHECK: vsxt +; CHECK: vunpack ; CHECK-NOT: vinsert define void @danny() local_unnamed_addr #0 { b2: @@ -15,7 +15,7 @@ b2: } ; CHECK-LABEL: sammy: -; CHECK: vsxt +; CHECK: vunpack ; CHECK-NOT: vinsert define void @sammy() local_unnamed_addr #1 { b2: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll index 3a0cd06578e5..1b464a404e14 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll @@ -1,48 +1,36 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: -; CHECK-DAG: v[[H00:[0-9]+]]:[[L00:[0-9]+]].h = vsxt(v0.b) -; CHECK-DAG: r[[R00:[0-9]+]] = #-2 -; CHECK: v1:0 = vshuff(v[[H00]],v[[L00]],r[[R00]]) +; CHECK: v1:0.h = vunpack(v0.b) define <128 x i16> @test_00(<128 x i8> %v0) #0 { %p = sext <128 x i8> %v0 to <128 x i16> ret <128 x i16> %p } ; CHECK-LABEL: test_01: -; CHECK-DAG: v[[H10:[0-9]+]]:[[L10:[0-9]+]].w = vsxt(v0.h) -; CHECK-DAG: r[[R10:[0-9]+]] = #-4 -; CHECK: v1:0 = vshuff(v[[H10]],v[[L10]],r[[R10]]) +; CHECK: v1:0.w = vunpack(v0.h) define <64 x i32> @test_01(<64 x i16> %v0) #0 { %p = sext <64 x i16> %v0 to <64 x i32> ret <64 x i32> %p } ; CHECK-LABEL: test_02: -; CHECK-DAG: v[[H20:[0-9]+]]:[[L20:[0-9]+]].uh = vzxt(v0.ub) -; CHECK-DAG: r[[R20:[0-9]+]] = #-2 -; CHECK: v1:0 = vshuff(v[[H20]],v[[L20]],r[[R20]]) +; CHECK: v1:0.uh = vunpack(v0.ub) define <128 x i16> @test_02(<128 x i8> %v0) #0 { %p = zext <128 x i8> %v0 to <128 x i16> ret <128 x i16> %p } ; CHECK-LABEL: test_03: -; CHECK-DAG: v[[H30:[0-9]+]]:[[L30:[0-9]+]].uw = vzxt(v0.uh) -; CHECK-DAG: r[[R30:[0-9]+]] = #-4 -; CHECK: v1:0 = vshuff(v[[H30]],v[[L30]],r[[R30]]) +; CHECK: v1:0.uw = vunpack(v0.uh) define <64 x i32> @test_03(<64 x i16> %v0) #0 { %p = zext <64 x i16> %v0 to <64 x i32> ret <64 x i32> %p } ; CHECK-LABEL: test_04: -; CHECK-DAG: v[[H40:[0-9]+]]:[[L40:[0-9]+]].h = vsxt(v0.b) -; CHECK-DAG: r[[R40:[0-9]+]] = #-2 -; CHECK-DAG: r[[R41:[0-9]+]] = #-4 -; CHECK: v[[H41:[0-9]+]]:[[L41:[0-9]+]] = vshuff(v[[H40]],v[[L40]],r[[R40]]) -; CHECK: v[[H42:[0-9]+]]:[[L42:[0-9]+]].w = vsxt(v[[L41]].h) -; CHECK: v1:0 = vshuff(v[[H42]],v[[L42]],r[[R41]]) +; CHECK: v[[H40:[0-9]+]]:[[L40:[0-9]+]].h = vunpack(v0.b) +; CHECK: v1:0.w = vunpack(v[[L40]].h) define <32 x i32> @test_04(<128 x i8> %v0) #0 { %x = sext <128 x i8> %v0 to <128 x i32> %p = shufflevector <128 x i32> %x, <128 x i32> undef, <32 x i32> @@ -50,12 +38,8 @@ define <32 x i32> @test_04(<128 x i8> %v0) #0 { } ; CHECK-LABEL: test_05: -; CHECK-DAG: v[[H50:[0-9]+]]:[[L50:[0-9]+]].uh = vzxt(v0.ub) -; CHECK-DAG: r[[R50:[0-9]+]] = #-2 -; CHECK-DAG: r[[R51:[0-9]+]] = #-4 -; CHECK: v[[H51:[0-9]+]]:[[L51:[0-9]+]] = vshuff(v[[H50]],v[[L50]],r[[R50]]) -; CHECK: v[[H52:[0-9]+]]:[[L52:[0-9]+]].uw = vzxt(v[[L51]].uh) -; CHECK: v1:0 = vshuff(v[[H52]],v[[L52]],r[[R51]]) +; CHECK: v[[H50:[0-9]+]]:[[L50:[0-9]+]].uh = vunpack(v0.ub) +; CHECK: v1:0.uw = vunpack(v[[L50]].uh) define <32 x i32> @test_05(<128 x i8> %v0) #0 { %x = zext <128 x i8> %v0 to <128 x i32> %p = shufflevector <128 x i32> %x, <128 x i32> undef, <32 x i32> diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll index ff246aebde3c..7791fa4a81ee 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll @@ -1,48 +1,36 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: -; CHECK-DAG: v[[H00:[0-9]+]]:[[L00:[0-9]+]].h = vsxt(v0.b) -; CHECK-DAG: r[[R00:[0-9]+]] = #-2 -; CHECK: v1:0 = vshuff(v[[H00]],v[[L00]],r[[R00]]) +; CHECK: v1:0.h = vunpack(v0.b) define <64 x i16> @test_00(<64 x i8> %v0) #0 { %p = sext <64 x i8> %v0 to <64 x i16> ret <64 x i16> %p } ; CHECK-LABEL: test_01: -; CHECK-DAG: v[[H10:[0-9]+]]:[[L10:[0-9]+]].w = vsxt(v0.h) -; CHECK-DAG: r[[R10:[0-9]+]] = #-4 -; CHECK: v1:0 = vshuff(v[[H10]],v[[L10]],r[[R10]]) +; CHECK: v1:0.w = vunpack(v0.h) define <32 x i32> @test_01(<32 x i16> %v0) #0 { %p = sext <32 x i16> %v0 to <32 x i32> ret <32 x i32> %p } ; CHECK-LABEL: test_02: -; CHECK-DAG: v[[H20:[0-9]+]]:[[L20:[0-9]+]].uh = vzxt(v0.ub) -; CHECK-DAG: r[[R20:[0-9]+]] = #-2 -; CHECK: v1:0 = vshuff(v[[H20]],v[[L20]],r[[R20]]) +; CHECK: v1:0.uh = vunpack(v0.ub) define <64 x i16> @test_02(<64 x i8> %v0) #0 { %p = zext <64 x i8> %v0 to <64 x i16> ret <64 x i16> %p } ; CHECK-LABEL: test_03: -; CHECK-DAG: v[[H30:[0-9]+]]:[[L30:[0-9]+]].uw = vzxt(v0.uh) -; CHECK-DAG: r[[R30:[0-9]+]] = #-4 -; CHECK: v1:0 = vshuff(v[[H30]],v[[L30]],r[[R30]]) +; CHECK: v1:0.uw = vunpack(v0.uh) define <32 x i32> @test_03(<32 x i16> %v0) #0 { %p = zext <32 x i16> %v0 to <32 x i32> ret <32 x i32> %p } ; CHECK-LABEL: test_04: -; CHECK-DAG: v[[H40:[0-9]+]]:[[L40:[0-9]+]].h = vsxt(v0.b) -; CHECK-DAG: r[[R40:[0-9]+]] = #-2 -; CHECK-DAG: r[[R41:[0-9]+]] = #-4 -; CHECK: v[[H41:[0-9]+]]:[[L41:[0-9]+]] = vshuff(v[[H40]],v[[L40]],r[[R40]]) -; CHECK: v[[H42:[0-9]+]]:[[L42:[0-9]+]].w = vsxt(v[[L41]].h) -; CHECK: v1:0 = vshuff(v[[H42]],v[[L42]],r[[R41]]) +; CHECK-DAG: v[[H40:[0-9]+]]:[[L40:[0-9]+]].h = vunpack(v0.b) +; CHECK: v1:0.w = vunpack(v[[L40]].h) define <16 x i32> @test_04(<64 x i8> %v0) #0 { %x = sext <64 x i8> %v0 to <64 x i32> %p = shufflevector <64 x i32> %x, <64 x i32> undef, <16 x i32> @@ -50,12 +38,8 @@ define <16 x i32> @test_04(<64 x i8> %v0) #0 { } ; CHECK-LABEL: test_05: -; CHECK-DAG: v[[H50:[0-9]+]]:[[L50:[0-9]+]].uh = vzxt(v0.ub) -; CHECK-DAG: r[[R50:[0-9]+]] = #-2 -; CHECK-DAG: r[[R51:[0-9]+]] = #-4 -; CHECK: v[[H51:[0-9]+]]:[[L51:[0-9]+]] = vshuff(v[[H50]],v[[L50]],r[[R50]]) -; CHECK: v[[H52:[0-9]+]]:[[L52:[0-9]+]].uw = vzxt(v[[L51]].uh) -; CHECK: v1:0 = vshuff(v[[H52]],v[[L52]],r[[R51]]) +; CHECK-DAG: v[[H50:[0-9]+]]:[[L50:[0-9]+]].uh = vunpack(v0.ub) +; CHECK: v1:0.uw = vunpack(v[[L50]].uh) define <16 x i32> @test_05(<64 x i8> %v0) #0 { %x = zext <64 x i8> %v0 to <64 x i32> %p = shufflevector <64 x i32> %x, <64 x i32> undef, <16 x i32>