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[RISCV] Use a vector MemVT when converting store+extractelt into a vector store. (#190107)

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This is needed so that `allowsMemoryAccessForAlignment` checks for
unaligned vector memory
support instead of unaligned scalar memory support when called from
`RISCVTargetLowering::expandUnalignedVPStore`

While there remove incorrect setting of the truncating store flag
on the vector instruction. And restrict the transform to simple stores
since we don't have tests for volatile or atomic.

Fixes #189037
This commit is contained in:
Craig Topper 2026-04-06 09:58:04 -07:00 committed by GitHub
parent 0d14772a91
commit b44d2c977c
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GPG Key ID: B5690EEEBB952194
2 changed files with 20 additions and 4 deletions
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10
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -22378,16 +22378,18 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
SDValue Src = Val.getOperand(0);
MVT VecVT = Src.getSimpleValueType();
// VecVT should be scalable and memory VT should match the element type.
if (!Store->isIndexed() && VecVT.isScalableVector() &&
MemVT == VecVT.getVectorElementType()) {
if (!Store->isIndexed() && Store->isSimple() &&
VecVT.isScalableVector() && MemVT == VecVT.getVectorElementType()) {
SDLoc DL(N);
MVT MaskVT = getMaskTypeFor(VecVT);
// Create a vector memory VT so allowsMisalignedMemoryAccesses will
// work correctly.
MemVT = EVT::getVectorVT(*DAG.getContext(), MemVT, 1);
return DAG.getStoreVP(
Store->getChain(), DL, Src, Store->getBasePtr(), Store->getOffset(),
DAG.getConstant(1, DL, MaskVT),
DAG.getConstant(1, DL, Subtarget.getXLenVT()), MemVT,
Store->getMemOperand(), Store->getAddressingMode(),
Store->isTruncatingStore(), /*IsCompress*/ false);
Store->getMemOperand(), Store->getAddressingMode());
}
}

14
llvm/test/CodeGen/RISCV/rvv/pr189037.ll Normal file
View File

@ -0,0 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem | FileCheck %s
; We should produce a vse8 due to the align 1
define void @test(ptr %out, <1 x i16> %v) {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%coerce.val.ii.i = extractelement <1 x i16> %v, i64 0
store i16 %coerce.val.ii.i, ptr %out, align 1
ret void
}