[VPlan] Handle non-free bitcasts in getCostForRecipeWithOpcode.
Update bitcast cost handling to match the legacy cost model.
This commit is contained in:
Florian Hahn
parent
e2ee738b6d
commit
b4d833135a
@ -978,8 +978,12 @@ InstructionCost VPRecipeWithIRFlags::getCostForRecipeWithOpcode(
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Ctx.CostKind, {TTI::OK_AnyValue, TTI::OP_None},
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{TTI::OK_AnyValue, TTI::OP_None}, CtxI);
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}
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case Instruction::BitCast:
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return 0;
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case Instruction::BitCast: {
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Type *ScalarTy = Ctx.Types.inferScalarType(this);
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if (ScalarTy->isPointerTy())
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return 0;
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[[fallthrough]];
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}
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case Instruction::SExt:
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case Instruction::ZExt:
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case Instruction::FPToUI:
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@ -218,4 +218,102 @@ exit:
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ret void
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}
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define i16 @bitcast_half_to_i16(ptr %src, ptr %dst, i64 %n) {
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; CHECK-LABEL: define i16 @bitcast_half_to_i16(
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; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ITER_CHECK:.*]]:
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
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; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
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; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 16
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <8 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[SRC]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr half, ptr [[TMP0]], i64 8
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; CHECK-NEXT: [[LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
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; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x half>, ptr [[TMP1]], align 2
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; CHECK-NEXT: [[FADD:%.*]] = fadd <8 x half> [[LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = fadd <8 x half> [[WIDE_LOAD3]], zeroinitializer
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <8 x half> [[FADD]] to <8 x i16>
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; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x half> [[TMP3]] to <8 x i16>
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; CHECK-NEXT: [[TMP6]] = or <8 x i16> [[VEC_PHI]], [[BITCAST]]
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; CHECK-NEXT: [[TMP7]] = or <8 x i16> [[VEC_PHI2]], [[TMP5]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
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; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[BIN_RDX:%.*]] = or <8 x i16> [[TMP7]], [[TMP6]]
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; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[BIN_RDX]])
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
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; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 4
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; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF12:![0-9]+]]
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; CHECK: [[VEC_EPILOG_PH]]:
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; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP9]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
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; CHECK-NEXT: [[N_MOD_VF4:%.*]] = urem i64 [[N]], 4
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; CHECK-NEXT: [[N_VEC5:%.*]] = sub i64 [[N]], [[N_MOD_VF4]]
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i16> zeroinitializer, i16 [[BC_MERGE_RDX]], i32 0
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; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
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; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX6:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i16> [ [[TMP10]], %[[VEC_EPILOG_PH]] ], [ [[TMP14:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr half, ptr [[SRC]], i64 [[INDEX6]]
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; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x half>, ptr [[TMP11]], align 2
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; CHECK-NEXT: [[TMP12:%.*]] = fadd <4 x half> [[WIDE_LOAD8]], zeroinitializer
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; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x half> [[TMP12]] to <4 x i16>
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; CHECK-NEXT: [[TMP14]] = or <4 x i16> [[VEC_PHI7]], [[TMP13]]
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; CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX6]], 4
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; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC5]]
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; CHECK-NEXT: br i1 [[TMP15]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
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; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[TMP16:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP14]])
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; CHECK-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC5]]
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; CHECK-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
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; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC5]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX11:%.*]] = phi i16 [ [[TMP16]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP9]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[RDX:%.*]] = phi i16 [ [[BC_MERGE_RDX11]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[OR:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr half, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[LOAD1:%.*]] = load half, ptr [[GEP]], align 2
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; CHECK-NEXT: [[FADD1:%.*]] = fadd half [[LOAD1]], 0xH0000
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; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast half [[FADD1]] to i16
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; CHECK-NEXT: [[OR]] = or i16 [[RDX]], [[BITCAST1]]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i16 [ [[OR]], %[[LOOP]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ [[TMP16]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i16 [[OR_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%rdx = phi i16 [ 0, %entry ], [ %or, %loop ]
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%gep = getelementptr half, ptr %src, i64 %iv
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%load = load half, ptr %gep, align 2
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%fadd = fadd half %load, 0xH0000
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%bitcast = bitcast half %fadd to i16
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%or = or i16 %rdx, %bitcast
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv.next, %n
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br i1 %ec, label %exit, label %loop
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exit:
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ret i16 %or
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}
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attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" }
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