[HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (#127137)
Fixes #99205. - Implements the HLSL intrinsic `AddUint64` used to perform unsigned 64-bit integer addition by using pairs of unsigned 32-bit integers instead of native 64-bit types - The LLVM intrinsic `uadd_with_overflow` is used in the implementation of `AddUint64` in `CGBuiltin.cpp` - The DXIL op `UAddc` was defined in `DXIL.td`, and a lowering of the LLVM intrinsic `uadd_with_overflow` to the `UAddc` DXIL op was implemented in `DXILOpLowering.cpp` Notes: - `__builtin_addc` was not able to be used to implement `AddUint64` in `hlsl_intrinsics.h` because its `CarryOut` argument is a pointer, and pointers are not supported in HLSL - A lowering of the LLVM intrinsic `uadd_with_overflow` to SPIR-V [already exists](https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll) - When lowering the LLVM intrinsic `uadd_with_overflow` to the `UAddc` DXIL op, the anonymous struct type `{ i32, i1 }` is replaced with a named struct type `%dx.types.i32c`. This aspect of the implementation may be changed when issue #113192 gets addressed - Fixes issues mentioned in the comments on the original PR #125319 --------- Co-authored-by: Finn Plummer <50529406+inbelic@users.noreply.github.com> Co-authored-by: Farzon Lotfi <farzonlotfi@microsoft.com> Co-authored-by: Chris B <beanz@abolishcrlf.org> Co-authored-by: Justin Bogner <mail@justinbogner.com>
This commit is contained in:
Deric C.
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commit
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@ -4765,6 +4765,12 @@ def GetDeviceSideMangledName : LangBuiltin<"CUDA_LANG"> {
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}
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// HLSL
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def HLSLAddUint64: LangBuiltin<"HLSL_LANG"> {
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let Spellings = ["__builtin_hlsl_adduint64"];
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let Attributes = [NoThrow, Const];
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let Prototype = "void(...)";
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}
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def HLSLResourceGetPointer : LangBuiltin<"HLSL_LANG"> {
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let Spellings = ["__builtin_hlsl_resource_getpointer"];
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let Attributes = [NoThrow];
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@ -10709,6 +10709,11 @@ def err_vector_incorrect_num_elements : Error<
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"%select{too many|too few}0 elements in vector %select{initialization|operand}3 (expected %1 elements, have %2)">;
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def err_altivec_empty_initializer : Error<"expected initializer">;
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def err_vector_incorrect_bit_count : Error<
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"incorrect number of bits in vector operand (expected %select{|a multiple of}0 %1 bits, have %2)">;
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def err_integer_incorrect_bit_count : Error<
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"incorrect number of bits in integer (expected %0 bits, have %1)">;
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def err_invalid_neon_type_code : Error<
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"incompatible constant for this __builtin_neon function">;
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def err_argument_invalid_range : Error<
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@ -19470,6 +19470,62 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
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return nullptr;
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switch (BuiltinID) {
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case Builtin::BI__builtin_hlsl_adduint64: {
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Value *OpA = EmitScalarExpr(E->getArg(0));
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Value *OpB = EmitScalarExpr(E->getArg(1));
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QualType Arg0Ty = E->getArg(0)->getType();
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uint64_t NumElements = Arg0Ty->castAs<VectorType>()->getNumElements();
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assert(Arg0Ty == E->getArg(1)->getType() &&
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"AddUint64 operand types must match");
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assert(Arg0Ty->hasIntegerRepresentation() &&
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"AddUint64 operands must have an integer representation");
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assert((NumElements == 2 || NumElements == 4) &&
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"AddUint64 operands must have 2 or 4 elements");
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llvm::Value *LowA;
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llvm::Value *HighA;
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llvm::Value *LowB;
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llvm::Value *HighB;
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// Obtain low and high words of inputs A and B
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if (NumElements == 2) {
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LowA = Builder.CreateExtractElement(OpA, (uint64_t)0, "LowA");
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HighA = Builder.CreateExtractElement(OpA, (uint64_t)1, "HighA");
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LowB = Builder.CreateExtractElement(OpB, (uint64_t)0, "LowB");
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HighB = Builder.CreateExtractElement(OpB, (uint64_t)1, "HighB");
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} else {
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LowA = Builder.CreateShuffleVector(OpA, ArrayRef<int>{0, 2}, "LowA");
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HighA = Builder.CreateShuffleVector(OpA, ArrayRef<int>{1, 3}, "HighA");
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LowB = Builder.CreateShuffleVector(OpB, ArrayRef<int>{0, 2}, "LowB");
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HighB = Builder.CreateShuffleVector(OpB, ArrayRef<int>{1, 3}, "HighB");
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}
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// Use an uadd_with_overflow to compute the sum of low words and obtain a
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// carry value
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llvm::Value *Carry;
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llvm::Value *LowSum = EmitOverflowIntrinsic(
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*this, llvm::Intrinsic::uadd_with_overflow, LowA, LowB, Carry);
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llvm::Value *ZExtCarry =
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Builder.CreateZExt(Carry, HighA->getType(), "CarryZExt");
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// Sum the high words and the carry
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llvm::Value *HighSum = Builder.CreateAdd(HighA, HighB, "HighSum");
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llvm::Value *HighSumPlusCarry =
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Builder.CreateAdd(HighSum, ZExtCarry, "HighSumPlusCarry");
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if (NumElements == 4) {
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return Builder.CreateShuffleVector(LowSum, HighSumPlusCarry,
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ArrayRef<int>{0, 2, 1, 3},
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"hlsl.AddUint64");
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}
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llvm::Value *Result = PoisonValue::get(OpA->getType());
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Result = Builder.CreateInsertElement(Result, LowSum, (uint64_t)0,
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"hlsl.AddUint64.upto0");
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Result = Builder.CreateInsertElement(Result, HighSumPlusCarry, (uint64_t)1,
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"hlsl.AddUint64");
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return Result;
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}
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case Builtin::BI__builtin_hlsl_resource_getpointer: {
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Value *HandleOp = EmitScalarExpr(E->getArg(0));
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Value *IndexOp = EmitScalarExpr(E->getArg(1));
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@ -174,6 +174,27 @@ float3 acos(float3);
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_HLSL_BUILTIN_ALIAS(__builtin_elementwise_acos)
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float4 acos(float4);
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//===----------------------------------------------------------------------===//
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// AddUint64 builtins
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//===----------------------------------------------------------------------===//
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/// \fn T AddUint64(T a, T b)
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/// \brief Implements unsigned 64-bit integer addition using pairs of unsigned
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/// 32-bit integers.
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/// \param x [in] The first unsigned 32-bit integer pair(s)
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/// \param y [in] The second unsigned 32-bit integer pair(s)
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///
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/// This function takes one or two pairs (low, high) of unsigned 32-bit integer
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/// values and returns pairs (low, high) of unsigned 32-bit integer
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/// values representing the result of unsigned 64-bit integer addition.
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_HLSL_AVAILABILITY(shadermodel, 6.0)
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_HLSL_BUILTIN_ALIAS(__builtin_hlsl_adduint64)
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uint32_t2 AddUint64(uint32_t2, uint32_t2);
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_HLSL_AVAILABILITY(shadermodel, 6.0)
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_HLSL_BUILTIN_ALIAS(__builtin_hlsl_adduint64)
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uint32_t4 AddUint64(uint32_t4, uint32_t4);
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//===----------------------------------------------------------------------===//
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// all builtins
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//===----------------------------------------------------------------------===//
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@ -2086,6 +2086,18 @@ static bool CheckAllArgsHaveFloatRepresentation(Sema *S, CallExpr *TheCall) {
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checkAllFloatTypes);
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}
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static bool CheckUnsignedIntRepresentations(Sema *S, CallExpr *TheCall) {
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auto checkUnsignedInteger = [](clang::QualType PassedType) -> bool {
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clang::QualType BaseType =
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PassedType->isVectorType()
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? PassedType->getAs<clang::VectorType>()->getElementType()
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: PassedType;
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return !BaseType->isUnsignedIntegerType();
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};
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return CheckAllArgTypesAreCorrect(S, TheCall, S->Context.UnsignedIntTy,
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checkUnsignedInteger);
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}
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static bool CheckFloatOrHalfRepresentations(Sema *S, CallExpr *TheCall) {
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auto checkFloatorHalf = [](clang::QualType PassedType) -> bool {
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clang::QualType BaseType =
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@ -2277,6 +2289,52 @@ static bool CheckResourceHandle(
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// returning an ExprError
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bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
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switch (BuiltinID) {
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case Builtin::BI__builtin_hlsl_adduint64: {
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if (SemaRef.checkArgCount(TheCall, 2))
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return true;
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if (CheckVectorElementCallArgs(&SemaRef, TheCall))
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return true;
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if (CheckUnsignedIntRepresentations(&SemaRef, TheCall))
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return true;
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// CheckVectorElementCallArgs(...) guarantees both args are the same type.
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assert(TheCall->getArg(0)->getType() == TheCall->getArg(1)->getType() &&
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"Both args must be of the same type");
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// ensure both args are vectors
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auto *VTy = TheCall->getArg(0)->getType()->getAs<VectorType>();
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if (!VTy) {
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SemaRef.Diag(TheCall->getBeginLoc(), diag::err_vec_builtin_non_vector)
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<< TheCall->getDirectCallee() << /*all*/ 1;
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return true;
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}
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// ensure arg integers are 32-bits
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uint64_t ElementBitCount = getASTContext()
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.getTypeSizeInChars(VTy->getElementType())
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.getQuantity() *
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8;
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if (ElementBitCount != 32) {
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SemaRef.Diag(TheCall->getBeginLoc(),
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diag::err_integer_incorrect_bit_count)
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<< 32 << ElementBitCount;
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return true;
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}
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// ensure both args are vectors of total bit size of a multiple of 64
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int NumElementsArg = VTy->getNumElements();
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if (NumElementsArg != 2 && NumElementsArg != 4) {
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SemaRef.Diag(TheCall->getBeginLoc(), diag::err_vector_incorrect_bit_count)
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<< 1 /*a multiple of*/ << 64 << NumElementsArg * ElementBitCount;
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return true;
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}
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ExprResult A = TheCall->getArg(0);
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QualType ArgTyA = A.get()->getType();
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// return type is the same as the input type
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TheCall->setType(ArgTyA);
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break;
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}
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case Builtin::BI__builtin_hlsl_resource_getpointer: {
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if (SemaRef.checkArgCount(TheCall, 2) ||
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CheckResourceHandle(&SemaRef, TheCall, 0) ||
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58
clang/test/CodeGenHLSL/builtins/AddUint64.hlsl
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58
clang/test/CodeGenHLSL/builtins/AddUint64.hlsl
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@ -0,0 +1,58 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \
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// RUN: -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s --check-prefixes=CHECK
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// CHECK-LABEL: define noundef <2 x i32> @_Z20test_AddUint64_uint2Dv2_jS_(
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// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i32>, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i32>, align 8
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// CHECK-NEXT: store <2 x i32> [[A]], ptr [[A_ADDR]], align 8
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// CHECK-NEXT: store <2 x i32> [[B]], ptr [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[A_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[B_ADDR]], align 8
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// CHECK-NEXT: [[LOWA:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0
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// CHECK-NEXT: [[HIGHA:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
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// CHECK-NEXT: [[LOWB:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
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// CHECK-NEXT: [[HIGHB:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
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// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[LOWA]], i32 [[LOWB]])
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
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// CHECK-NEXT: [[CARRYZEXT:%.*]] = zext i1 [[TMP3]] to i32
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// CHECK-NEXT: [[HIGHSUM:%.*]] = add i32 [[HIGHA]], [[HIGHB]]
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// CHECK-NEXT: [[HIGHSUMPLUSCARRY:%.*]] = add i32 [[HIGHSUM]], [[CARRYZEXT]]
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// CHECK-NEXT: [[HLSL_ADDUINT64_UPTO0:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i64 0
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// CHECK-NEXT: [[HLSL_ADDUINT64:%.*]] = insertelement <2 x i32> [[HLSL_ADDUINT64_UPTO0]], i32 [[HIGHSUMPLUSCARRY]], i64 1
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// CHECK-NEXT: ret <2 x i32> [[HLSL_ADDUINT64]]
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//
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uint2 test_AddUint64_uint2(uint2 a, uint2 b) {
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return AddUint64(a, b);
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}
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// CHECK-LABEL: define noundef <4 x i32> @_Z20test_AddUint64_uint4Dv4_jS_(
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// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: store <4 x i32> [[A]], ptr [[A_ADDR]], align 16
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// CHECK-NEXT: store <4 x i32> [[B]], ptr [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[B_ADDR]], align 16
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// CHECK-NEXT: [[LOWA:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>
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// CHECK-NEXT: [[HIGHA:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>
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// CHECK-NEXT: [[LOWB:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>
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// CHECK-NEXT: [[HIGHB:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>
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// CHECK-NEXT: [[TMP2:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> [[LOWA]], <2 x i32> [[LOWB]])
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP2]], 1
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP2]], 0
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// CHECK-NEXT: [[CARRYZEXT:%.*]] = zext <2 x i1> [[TMP3]] to <2 x i32>
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// CHECK-NEXT: [[HIGHSUM:%.*]] = add <2 x i32> [[HIGHA]], [[HIGHB]]
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// CHECK-NEXT: [[HIGHSUMPLUSCARRY:%.*]] = add <2 x i32> [[HIGHSUM]], [[CARRYZEXT]]
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// CHECK-NEXT: [[HLSL_ADDUINT64:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> [[HIGHSUMPLUSCARRY]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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// CHECK-NEXT: ret <4 x i32> [[HLSL_ADDUINT64]]
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//
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uint4 test_AddUint64_uint4(uint4 a, uint4 b) {
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return AddUint64(a, b);
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}
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46
clang/test/SemaHLSL/BuiltIns/AddUint64-errors.hlsl
Normal file
46
clang/test/SemaHLSL/BuiltIns/AddUint64-errors.hlsl
Normal file
@ -0,0 +1,46 @@
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// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify
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uint2 test_too_few_arg() {
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return __builtin_hlsl_adduint64();
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// expected-error@-1 {{too few arguments to function call, expected 2, have 0}}
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}
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uint4 test_too_many_arg(uint4 a) {
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return __builtin_hlsl_adduint64(a, a, a);
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// expected-error@-1 {{too many arguments to function call, expected 2, have 3}}
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}
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uint2 test_mismatched_arg_types(uint2 a, uint4 b) {
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return __builtin_hlsl_adduint64(a, b);
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// expected-error@-1 {{all arguments to '__builtin_hlsl_adduint64' must have the same type}}
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}
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uint2 test_bad_num_arg_elements(uint3 a, uint3 b) {
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return __builtin_hlsl_adduint64(a, b);
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// expected-error@-1 {{incorrect number of bits in vector operand (expected a multiple of 64 bits, have 96)}}
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}
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uint2 test_scalar_arg_type(uint a) {
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return __builtin_hlsl_adduint64(a, a);
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// expected-error@-1 {{all arguments to '__builtin_hlsl_adduint64' must be vectors}}
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}
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uint2 test_uint64_args(uint16_t2 a) {
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return __builtin_hlsl_adduint64(a, a);
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// expected-error@-1 {{incorrect number of bits in integer (expected 32 bits, have 16)}}
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}
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uint2 test_signed_integer_args(int2 a, int2 b) {
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return __builtin_hlsl_adduint64(a, b);
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// expected-error@-1 {{passing 'int2' (aka 'vector<int, 2>') to parameter of incompatible type '__attribute__((__vector_size__(2 * sizeof(unsigned int)))) unsigned int' (vector of 2 'unsigned int' values)}}
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}
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struct S {
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uint2 a;
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};
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uint2 test_incorrect_arg_type(S a) {
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return __builtin_hlsl_adduint64(a, a);
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// expected-error@-1 {{passing 'S' to parameter of incompatible type 'unsigned int'}}
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}
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@ -56,6 +56,7 @@ def HandleTy : DXILOpParamType;
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def ResBindTy : DXILOpParamType;
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def ResPropsTy : DXILOpParamType;
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def SplitDoubleTy : DXILOpParamType;
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def BinaryWithCarryTy : DXILOpParamType;
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class DXILOpClass;
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@ -744,6 +745,16 @@ def UMin : DXILOp<40, binary> {
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def UAddc : DXILOp<44, binaryWithCarryOrBorrow > {
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let Doc = "unsigned add of 32-bit operand with the carry";
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let intrinsics = [IntrinSelect<int_uadd_with_overflow>];
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let arguments = [OverloadTy, OverloadTy];
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let result = BinaryWithCarryTy;
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let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def FMad : DXILOp<46, tertiary> {
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let Doc = "Floating point arithmetic multiply/add operation. fmad(m,a,b) = m "
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"* a + b.";
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@ -253,6 +253,14 @@ static StructType *getSplitDoubleType(LLVMContext &Context) {
|
||||
return StructType::create({Int32Ty, Int32Ty}, "dx.types.splitdouble");
|
||||
}
|
||||
|
||||
static StructType *getBinaryWithCarryType(LLVMContext &Context) {
|
||||
if (auto *ST = StructType::getTypeByName(Context, "dx.types.i32c"))
|
||||
return ST;
|
||||
Type *Int32Ty = Type::getInt32Ty(Context);
|
||||
Type *Int1Ty = Type::getInt1Ty(Context);
|
||||
return StructType::create({Int32Ty, Int1Ty}, "dx.types.i32c");
|
||||
}
|
||||
|
||||
static Type *getTypeFromOpParamType(OpParamType Kind, LLVMContext &Ctx,
|
||||
Type *OverloadTy) {
|
||||
switch (Kind) {
|
||||
@ -308,6 +316,8 @@ static Type *getTypeFromOpParamType(OpParamType Kind, LLVMContext &Ctx,
|
||||
return getResPropsType(Ctx);
|
||||
case OpParamType::SplitDoubleTy:
|
||||
return getSplitDoubleType(Ctx);
|
||||
case OpParamType::BinaryWithCarryTy:
|
||||
return getBinaryWithCarryType(Ctx);
|
||||
}
|
||||
llvm_unreachable("Invalid parameter kind");
|
||||
return nullptr;
|
||||
|
||||
75
llvm/test/CodeGen/DirectX/UAddc.ll
Normal file
75
llvm/test/CodeGen/DirectX/UAddc.ll
Normal file
@ -0,0 +1,75 @@
|
||||
; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
|
||||
|
||||
; This test exercises the lowering of the intrinsic @llvm.uadd.with.overflow.i32 to the UAddc DXIL op
|
||||
|
||||
; CHECK-DAG: [[DX_TYPES_I32C:%dx\.types\.i32c]] = type { i32, i1 }
|
||||
|
||||
; NOTE: The uint2 overload of AddUint64 HLSL uses @llvm.uadd.with.overflow.i32, resulting in one UAddc op
|
||||
define noundef i32 @test_UAddc(i32 noundef %a, i32 noundef %b) {
|
||||
; CHECK-LABEL: define noundef i32 @test_UAddc(
|
||||
; CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) {
|
||||
; CHECK-NEXT: [[UADDC:%.*]] = call [[DX_TYPES_I32C]] @dx.op.binaryWithCarryOrBorrow.i32(i32 44, i32 [[A]], i32 [[B]]) #[[ATTR0:[0-9]+]]
|
||||
; CHECK-NEXT: [[CARRY:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC]], 1
|
||||
; CHECK-NEXT: [[SUM:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC]], 0
|
||||
; CHECK-NEXT: [[CARRY_ZEXT:%.*]] = zext i1 [[CARRY]] to i32
|
||||
; CHECK-NEXT: [[RESULT:%.*]] = add i32 [[SUM]], [[CARRY_ZEXT]]
|
||||
; CHECK-NEXT: ret i32 [[RESULT]]
|
||||
;
|
||||
%uaddc = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
|
||||
%carry = extractvalue { i32, i1 } %uaddc, 1
|
||||
%sum = extractvalue { i32, i1 } %uaddc, 0
|
||||
%carry_zext = zext i1 %carry to i32
|
||||
%result = add i32 %sum, %carry_zext
|
||||
ret i32 %result
|
||||
}
|
||||
|
||||
; NOTE: The uint4 overload of AddUint64 HLSL uses @llvm.uadd.with.overflow.v2i32, resulting in two UAddc ops after scalarization
|
||||
define noundef <2 x i32> @test_UAddc_vec2(<2 x i32> noundef %a, <2 x i32> noundef %b) {
|
||||
; CHECK-LABEL: define noundef <2 x i32> @test_UAddc_vec2(
|
||||
; CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) {
|
||||
; CHECK-NEXT: [[A_I0:%.*]] = extractelement <2 x i32> [[A]], i64 0
|
||||
; CHECK-NEXT: [[B_I0:%.*]] = extractelement <2 x i32> [[B]], i64 0
|
||||
; CHECK-NEXT: [[UADDC_I0:%.*]] = call [[DX_TYPES_I32C]] @dx.op.binaryWithCarryOrBorrow.i32(i32 44, i32 [[A_I0]], i32 [[B_I0]]) #[[ATTR0]]
|
||||
; CHECK-NEXT: [[A_I1:%.*]] = extractelement <2 x i32> [[A]], i64 1
|
||||
; CHECK-NEXT: [[B_I1:%.*]] = extractelement <2 x i32> [[B]], i64 1
|
||||
; CHECK-NEXT: [[UADDC_I1:%.*]] = call [[DX_TYPES_I32C]] @dx.op.binaryWithCarryOrBorrow.i32(i32 44, i32 [[A_I1]], i32 [[B_I1]]) #[[ATTR0]]
|
||||
; CHECK-NEXT: [[CARRY_ELEM0:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I0]], 1
|
||||
; CHECK-NEXT: [[CARRY_ELEM1:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I1]], 1
|
||||
; CHECK-NEXT: [[CARRY_UPTO0:%.*]] = insertelement <2 x i1> poison, i1 [[CARRY_ELEM0]], i64 0
|
||||
; CHECK-NEXT: [[CARRY:%.*]] = insertelement <2 x i1> [[CARRY_UPTO0]], i1 [[CARRY_ELEM1]], i64 1
|
||||
; CHECK-NEXT: [[CARRY_I0:%.*]] = extractelement <2 x i1> [[CARRY]], i64 0
|
||||
; CHECK-NEXT: [[CARRY_I1:%.*]] = extractelement <2 x i1> [[CARRY]], i64 1
|
||||
; CHECK-NEXT: [[SUM_ELEM0:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I0]], 0
|
||||
; CHECK-NEXT: [[SUM_ELEM1:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC_I1]], 0
|
||||
; CHECK-NEXT: [[CARRY_ZEXT_I0:%.*]] = zext i1 [[CARRY_I0]] to i32
|
||||
; CHECK-NEXT: [[CARRY_ZEXT_I1:%.*]] = zext i1 [[CARRY_I1]] to i32
|
||||
; CHECK-NEXT: [[RESULT_I0:%.*]] = add i32 [[SUM_ELEM0]], [[CARRY_ZEXT_I0]]
|
||||
; CHECK-NEXT: [[RESULT_I1:%.*]] = add i32 [[SUM_ELEM1]], [[CARRY_ZEXT_I1]]
|
||||
; CHECK-NEXT: [[RESULT_UPTO0:%.*]] = insertelement <2 x i32> poison, i32 [[RESULT_I0]], i64 0
|
||||
; CHECK-NEXT: [[RESULT:%.*]] = insertelement <2 x i32> [[RESULT_UPTO0]], i32 [[RESULT_I1]], i64 1
|
||||
; CHECK-NEXT: ret <2 x i32> [[RESULT]]
|
||||
;
|
||||
%uaddc = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)
|
||||
%carry = extractvalue { <2 x i32>, <2 x i1> } %uaddc, 1
|
||||
%sum = extractvalue { <2 x i32>, <2 x i1> } %uaddc, 0
|
||||
%carry_zext = zext <2 x i1> %carry to <2 x i32>
|
||||
%result = add <2 x i32> %sum, %carry_zext
|
||||
ret <2 x i32> %result
|
||||
}
|
||||
|
||||
define noundef i32 @test_UAddc_insert(i32 noundef %a, i32 noundef %b) {
|
||||
; CHECK-LABEL: define noundef i32 @test_UAddc_insert(
|
||||
; CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) {
|
||||
; CHECK-NEXT: [[UADDC:%.*]] = call [[DX_TYPES_I32C]] @dx.op.binaryWithCarryOrBorrow.i32(i32 44, i32 [[A]], i32 [[B]]) #[[ATTR0]]
|
||||
; CHECK-NEXT: [[UNUSED:%.*]] = insertvalue [[DX_TYPES_I32C]] [[UADDC]], i32 [[A]], 0
|
||||
; CHECK-NEXT: [[RESULT:%.*]] = extractvalue [[DX_TYPES_I32C]] [[UADDC]], 0
|
||||
; CHECK-NEXT: ret i32 [[RESULT]]
|
||||
;
|
||||
%uaddc = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
|
||||
insertvalue { i32, i1 } %uaddc, i32 %a, 0
|
||||
%result = extractvalue { i32, i1 } %uaddc, 0
|
||||
ret i32 %result
|
||||
}
|
||||
|
||||
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
|
||||
|
||||
30
llvm/test/CodeGen/DirectX/UAddc_errors.ll
Normal file
30
llvm/test/CodeGen/DirectX/UAddc_errors.ll
Normal file
@ -0,0 +1,30 @@
|
||||
; We use llc for this test so that we don't abort after the first error.
|
||||
; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s
|
||||
|
||||
target triple = "dxil-pc-shadermodel6.3-library"
|
||||
|
||||
; DXIL operation UAddc only supports i32. Other integer types are unsupported.
|
||||
; CHECK: error:
|
||||
; CHECK-SAME: in function uaddc_i16
|
||||
; CHECK-SAME: Cannot create UAddc operation: Invalid overload type
|
||||
|
||||
define noundef i16 @uaddc_i16(i16 noundef %a, i16 noundef %b) "hlsl.export" {
|
||||
%uaddc = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %a, i16 %b)
|
||||
%carry = extractvalue { i16, i1 } %uaddc, 1
|
||||
%sum = extractvalue { i16, i1 } %uaddc, 0
|
||||
%carry_zext = zext i1 %carry to i16
|
||||
%result = add i16 %sum, %carry_zext
|
||||
ret i16 %result
|
||||
}
|
||||
|
||||
; CHECK: error:
|
||||
; CHECK-SAME: in function uaddc_return
|
||||
; CHECK-SAME: DXIL ops that return structs may only be used by insert- and extractvalue
|
||||
|
||||
define noundef { i32, i1 } @uaddc_return(i32 noundef %a, i32 noundef %b) "hlsl.export" {
|
||||
%uaddc = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
|
||||
ret { i32, i1 } %uaddc
|
||||
}
|
||||
|
||||
declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16)
|
||||
|
||||
88
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/AddUint64.ll
Normal file
88
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/AddUint64.ll
Normal file
@ -0,0 +1,88 @@
|
||||
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
|
||||
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
|
||||
|
||||
; Code here is an excerpt of clang/test/CodeGenHLSL/builtins/AddUint64.hlsl compiled for spirv using the following command
|
||||
; clang -cc1 -finclude-default-header -triple spirv-unknown-vulkan-compute clang/test/CodeGenHLSL/builtins/AddUint64.hlsl -emit-llvm -disable-llvm-passes -o llvm/test/CodeGen/SPIRV/hlsl-intrinsics/uadd_with_overflow.ll
|
||||
|
||||
; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 0
|
||||
; CHECK-DAG: %[[#vec2_int_32:]] = OpTypeVector %[[#int_32]] 2
|
||||
; CHECK-DAG: %[[#bool:]] = OpTypeBool
|
||||
; CHECK-DAG: %[[#const_i32_1:]] = OpConstant %[[#int_32]] 1
|
||||
; CHECK-DAG: %[[#struct_i32_i32:]] = OpTypeStruct %[[#int_32]] %[[#int_32]]
|
||||
; CHECK-DAG: %[[#func_v2i32_v2i32_v2i32:]] = OpTypeFunction %[[#vec2_int_32]] %[[#vec2_int_32]] %[[#vec2_int_32]]
|
||||
; CHECK-DAG: %[[#const_i32_0:]] = OpConstant %[[#int_32]] 0
|
||||
; CHECK-DAG: %[[#undef_v2i32:]] = OpUndef %[[#vec2_int_32]]
|
||||
; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
|
||||
; CHECK-DAG: %[[#vec2_bool:]] = OpTypeVector %[[#bool]] 2
|
||||
; CHECK-DAG: %[[#const_v2i32_0_0:]] = OpConstantComposite %[[#vec2_int_32]] %[[#const_i32_0]] %[[#const_i32_0]]
|
||||
; CHECK-DAG: %[[#const_v2i32_1_1:]] = OpConstantComposite %[[#vec2_int_32]] %[[#const_i32_1]] %[[#const_i32_1]]
|
||||
; CHECK-DAG: %[[#struct_v2i32_v2i32:]] = OpTypeStruct %[[#vec2_int_32]] %[[#vec2_int_32]]
|
||||
; CHECK-DAG: %[[#func_v4i32_v4i32_v4i32:]] = OpTypeFunction %[[#vec4_int_32]] %[[#vec4_int_32]] %[[#vec4_int_32]]
|
||||
; CHECK-DAG: %[[#undef_v4i32:]] = OpUndef %[[#vec4_int_32]]
|
||||
|
||||
|
||||
define spir_func <2 x i32> @test_AddUint64_uint2(<2 x i32> %a, <2 x i32> %b) {
|
||||
entry:
|
||||
; CHECK: %[[#a:]] = OpFunctionParameter %[[#vec2_int_32]]
|
||||
; CHECK: %[[#b:]] = OpFunctionParameter %[[#vec2_int_32]]
|
||||
; CHECK: %[[#a_low:]] = OpCompositeExtract %[[#int_32]] %[[#a]] 0
|
||||
; CHECK: %[[#a_high:]] = OpCompositeExtract %[[#int_32]] %[[#a]] 1
|
||||
; CHECK: %[[#b_low:]] = OpCompositeExtract %[[#int_32]] %[[#b]] 0
|
||||
; CHECK: %[[#b_high:]] = OpCompositeExtract %[[#int_32]] %[[#b]] 1
|
||||
; CHECK: %[[#iaddcarry:]] = OpIAddCarry %[[#struct_i32_i32]] %[[#a_low]] %[[#b_low]]
|
||||
; CHECK: %[[#lowsum:]] = OpCompositeExtract %[[#int_32]] %[[#iaddcarry]] 0
|
||||
; CHECK: %[[#carry:]] = OpCompositeExtract %[[#int_32]] %[[#iaddcarry]] 1
|
||||
; CHECK: %[[#carry_ne0:]] = OpINotEqual %[[#bool]] %[[#carry]] %[[#const_i32_0]]
|
||||
; CHECK: %[[#select_1_or_0:]] = OpSelect %[[#int_32]] %[[#carry_ne0]] %[[#const_i32_1]] %[[#const_i32_0]]
|
||||
; CHECK: %[[#highsum:]] = OpIAdd %[[#int_32]] %[[#a_high]] %[[#b_high]]
|
||||
; CHECK: %[[#highsumpluscarry:]] = OpIAdd %[[#int_32]] %[[#highsum]] %[[#select_1_or_0]]
|
||||
; CHECK: %[[#adduint64_upto0:]] = OpCompositeInsert %[[#vec2_int_32]] %[[#lowsum]] %[[#undef_v2i32]] 0
|
||||
; CHECK: %[[#adduint64:]] = OpCompositeInsert %[[#vec2_int_32]] %[[#highsumpluscarry]] %[[#adduint64_upto0]] 1
|
||||
; CHECK: OpReturnValue %[[#adduint64]]
|
||||
;
|
||||
%LowA = extractelement <2 x i32> %a, i64 0
|
||||
%HighA = extractelement <2 x i32> %a, i64 1
|
||||
%LowB = extractelement <2 x i32> %b, i64 0
|
||||
%HighB = extractelement <2 x i32> %b, i64 1
|
||||
%3 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %LowA, i32 %LowB)
|
||||
%4 = extractvalue { i32, i1 } %3, 1
|
||||
%5 = extractvalue { i32, i1 } %3, 0
|
||||
%CarryZExt = zext i1 %4 to i32
|
||||
%HighSum = add i32 %HighA, %HighB
|
||||
%HighSumPlusCarry = add i32 %HighSum, %CarryZExt
|
||||
%hlsl.AddUint64.upto0 = insertelement <2 x i32> poison, i32 %5, i64 0
|
||||
%hlsl.AddUint64 = insertelement <2 x i32> %hlsl.AddUint64.upto0, i32 %HighSumPlusCarry, i64 1
|
||||
ret <2 x i32> %hlsl.AddUint64
|
||||
}
|
||||
|
||||
define spir_func <4 x i32> @test_AddUint64_uint4(<4 x i32> %a, <4 x i32> %b) #0 {
|
||||
entry:
|
||||
; CHECK: %[[#a:]] = OpFunctionParameter %[[#vec4_int_32]]
|
||||
; CHECK: %[[#b:]] = OpFunctionParameter %[[#vec4_int_32]]
|
||||
; CHECK: %[[#a_low:]] = OpVectorShuffle %[[#vec2_int_32]] %[[#a]] %[[#undef_v4i32]] 0 2
|
||||
; CHECK: %[[#a_high:]] = OpVectorShuffle %[[#vec2_int_32]] %[[#a]] %[[#undef_v4i32]] 1 3
|
||||
; CHECK: %[[#b_low:]] = OpVectorShuffle %[[#vec2_int_32]] %[[#b]] %[[#undef_v4i32]] 0 2
|
||||
; CHECK: %[[#b_high:]] = OpVectorShuffle %[[#vec2_int_32]] %[[#b]] %[[#undef_v4i32]] 1 3
|
||||
; CHECK: %[[#iaddcarry:]] = OpIAddCarry %[[#struct_v2i32_v2i32]] %[[#a_low]] %[[#vec2_int_32]]
|
||||
; CHECK: %[[#lowsum:]] = OpCompositeExtract %[[#vec2_int_32]] %[[#iaddcarry]] 0
|
||||
; CHECK: %[[#carry:]] = OpCompositeExtract %[[#vec2_int_32]] %[[#iaddcarry]] 1
|
||||
; CHECK: %[[#carry_ne0:]] = OpINotEqual %[[#vec2_bool]] %[[#carry]] %[[#const_v2i32_0_0]]
|
||||
; CHECK: %[[#select_1_or_0:]] = OpSelect %[[#vec2_int_32]] %[[#carry_ne0]] %[[#const_v2i32_1_1]] %[[#const_v2i32_0_0]]
|
||||
; CHECK: %[[#highsum:]] = OpIAdd %[[#vec2_int_32]] %[[#a_high]] %[[#b_high]]
|
||||
; CHECK: %[[#highsumpluscarry:]] = OpIAdd %[[#vec2_int_32]] %[[#highsum]] %[[#select_1_or_0]]
|
||||
; CHECK: %[[#adduint64:]] = OpVectorShuffle %[[#vec4_int_32]] %[[#lowsum]] %[[#highsumpluscarry]] 0 2 1 3
|
||||
; CHECK: OpReturnValue %[[#adduint64]]
|
||||
;
|
||||
%LowA = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
|
||||
%HighA = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
|
||||
%LowB = shufflevector <4 x i32> %b, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
|
||||
%HighB = shufflevector <4 x i32> %b, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
|
||||
%3 = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> %LowA, <2 x i32> %LowB)
|
||||
%4 = extractvalue { <2 x i32>, <2 x i1> } %3, 1
|
||||
%5 = extractvalue { <2 x i32>, <2 x i1> } %3, 0
|
||||
%CarryZExt = zext <2 x i1> %4 to <2 x i32>
|
||||
%HighSum = add <2 x i32> %HighA, %HighB
|
||||
%HighSumPlusCarry = add <2 x i32> %HighSum, %CarryZExt
|
||||
%hlsl.AddUint64 = shufflevector <2 x i32> %5, <2 x i32> %HighSumPlusCarry, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
||||
ret <4 x i32> %hlsl.AddUint64
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user