[NFC][Docs] Add documentation for NVPTX conversion intrinsics (#175536)
This change adds documentation for the NVPTX narrow floating-point conversion intrinsics. PTX ISA Reference: https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
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Srinivasa Ravi
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@ -1106,6 +1106,183 @@ If the given pointer in the generic address space refers to memory which falls
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within the state space of the intrinsic (and therefore could be safely address
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space casted to this space), 1 is returned, otherwise 0 is returned.
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Narrow Floating-Point Conversion intrinsics
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-------------------------------------------
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These intrinsics perform conversions involving narrow floating-point formats.
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The following table describes the rounding modes used across these intrinsics:
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.. _narrow-fp-rounding-modes:
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.. table:: Narrow Floating-Point Conversion Rounding Modes
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:widths: 30 60
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+-----------------------+---------------------------------------------------+
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| Rounding Mode | Description |
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+=======================+===================================================+
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|``rn`` (default) | Round to nearest, with ties to even |
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+-----------------------+---------------------------------------------------+
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|``rz`` | Round towards zero |
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+-----------------------+---------------------------------------------------+
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|``rp`` | Round towards positive infinity |
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+-----------------------+---------------------------------------------------+
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|``rs`` | Stochastic rounding which is achieved through the |
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| | use of the supplied random bits (``%rnd_bits``). |
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| | The result s rounded in the direction towards |
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| | zero or away from zero based on the carry out of |
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| | the integer addition of the of mantissa from |
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| | the input. |
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+-----------------------+---------------------------------------------------+
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``fp8`` Conversion Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare i16 @llvm.nvvm.ff.to{.e4m3x2, .e5m2x2}.rn{.relu}(float %a, float %b)
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declare i16 @llvm.nvvm.ff.to.ue8m0x2{.rz, .rp}{.satfinite}(float %a, float %b)
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declare i16 @llvm.f16x2.to{.e4m3x2, .e5m2x2}.rn{.relu}(<2 x half> %a)
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declare i16 @llvm.bf16x2.to{.e4m3x2, .e5m2x2}.rn{.relu}.satfinite(<2 x bfloat> %a)
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declare i16 @llvm.bf16x2.to.ue8m0x2{.rz, .rp}{.satfinite}(<2 x bfloat> %a)
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declare <2 x half> @llvm.nvvm{.e4m3x2, .e5m2x2}.to.f16x2.rn{.relu}(i16 %a)
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declare <2 x bfloat> @llvm.nvvm.ue8m0x2.to.bf16x2(i16 %a)
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declare <4 x i8> @llvm.nvvm.f32x4.to{.e4m3x4, .e5m2x4}.rs{.relu}.satfinite(<4 x f32> %a, i32 %rnd_bits)
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Overview:
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"""""""""
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These intrinsics perform conversions involving the ``e4m3`` and ``e5m2`` narrow
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floating-point formats. In case of two inputs, the value converted from input
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``%a`` is stored in the upper 8-bits of the result, and the value converted
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from input ``%b`` is stored in the lower 8-bits of the result.
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For rounding modes, see :ref:`narrow-fp-rounding-modes`.
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The ``relu`` modifier clamps negative results to 0.
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When ``satfinite`` is specified, if the absolute value of input (ignoring sign)
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is greater than ``MAX_NORM`` of the specified destination format, then the
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result is sign-preserved ``MAX_NORM`` of the destination format and a positive
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``MAX_NORM`` in ``.ue8m0x2`` for which the destination sign is not supported.
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Also, if the input value is ``NaN``, then the result is ``NaN`` in the
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specified destination format. The ``satfinite`` modifier is assumed to be
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present for conversions involving ``e4m3`` and ``e5m2`` types as the
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destination.
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For more information, see `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt>`__.
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``s2f6`` Conversion Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare i16 @llvm.nvvm.ff.to.s2f6x2.rn{.relu}.satfinite.scale.n2.ue8m0(float %a, float %b, i16 %scale_factor)
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declare i16 @llvm.nvvm.bf16x2.to.s2f6x2.rn{.relu}.satfinite.scale.n2.ue8m0(<2 x bfloat> %a, i16 %scale_factor)
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declare <2 x bfloat> @llvm.nvvm.s2f6x2.to.bf16x2.rn{.relu}{.satfinite}.scale.n2.ue8m0(i16 %a, i16 %scale_factor)
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Overview:
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"""""""""
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These intrinsics perform conversions involving the ``s2f6`` narrow
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floating-point format. In case of two inputs, the value converted from input
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``%a`` is stored in the upper 8-bits of the result, and the value converted
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from input ``%b`` is stored in the lower 8-bits of the result.
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For rounding modes, see :ref:`narrow-fp-rounding-modes`.
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The ``relu`` modifier clamps negative results to 0.
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When ``satfinite`` is specified, if the absolute value of input (ignoring sign)
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is greater than ``MAX_NORM`` of the specified destination format, then the
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result is sign-preserved ``MAX_NORM`` of the destination format. Also, if the
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input is ``NaN``, then the result is the positive ``MAX_NORM`` of the
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destination format.
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The operand ``%scale_factor`` stores two packed scaling factors of type
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``ue8m0``, one for each input. For down conversion, inputs are divided by
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``scale_factor`` and then the conversion is performed. For up-conversion,
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inputs are converted to destination type and then multiplied by
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``scale_factor``.
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For more information, see `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt>`__.
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``fp6`` Conversion Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare i16 @llvm.nvvm.ff.to{.e2m3x2, .e3m2x2}.rn{.relu}.satfinite(float %a, float %b)
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declare i16 @llvm.nvvm.f16x2.to{.e2m3x2, .e3m2x2}.rn{.relu}.satfinite(<2 x half> %a)
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declare i16 @llvm.nvvm.bf16x2.to{.e2m3x2, .e3m2x2}.rn{.relu}.satfinite(<2 x bfloat> %a)
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declare <2 x half> @llvm.nvvm{.e2m3x2, .e3m2x2}.to.f16x2.rn{.relu}(i16 %a)
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declare <4 x i8> @llvm.nvvm.f32x4.to{.e2m3x4, .e3m2x4}.rs{.relu}.satfinite(<4 x f32> %a, i32 %rnd_bits)
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Overview:
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"""""""""
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These intrinsics perform conversions involving the ``e2m3`` and ``e3m2`` narrow
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floating-point formats. In case of two inputs, the value converted from input
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``%a`` is stored in the upper 8-bits of the result, and the value converted
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from input ``%b`` is stored in the lower 8-bits of the result with 2 MSBs
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padded with 0s in both cases.
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For rounding modes, see :ref:`narrow-fp-rounding-modes`.
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The ``relu`` modifier clamps negative results to 0.
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When ``satfinite`` is specified, if the absolute value of input (ignoring sign)
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is greater than ``MAX_NORM`` of the specified destination format, then the
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result is sign-preserved ``MAX_NORM`` of the destination format. Also, if the
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input is ``NaN``, then the result is the positive ``MAX_NORM`` of the
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destination format.
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For more information, see `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt>`__.
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``fp4`` Conversion Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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.. code-block:: llvm
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declare i16 @llvm.nvvm.ff.to.e2m1x2.rn{.relu}.satfinite(float %a, float %b)
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declare i16 @llvm.nvvm.f16x2.to.e2m1x2.rn{.relu}.satfinite(<2 x half> %a)
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declare i16 @llvm.nvvm.bf16x2.to.e2m1x2.rn{.relu}.satfinite(<2 x bfloat> %a)
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declare <2 x half> @llvm.nvvm.e2m1x2.to.f16x2.rn{.relu}(i16 %a)
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declare i16 @llvm.nvvm.f32x4.to.e2m1x4.rs{.relu}.satfinite(<4 x f32> %a, i32 %rnd_bits)
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Overview:
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"""""""""
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These intrinsics perform conversions involving the ``e2m1`` narrow
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floating-point format. For conversions involving ``e2m1x2``, the packed
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``e2m1x2`` value is stored in the lower byte of the ``i16`` argument or result.
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In case of two inputs, the value converted from input
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``%a`` is stored in the upper 4-bits of the result, and the value converted
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from input ``%b`` is stored in the lower 4-bits of the result.
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For rounding modes, see :ref:`narrow-fp-rounding-modes`.
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The ``relu`` modifier clamps negative results to 0.
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When ``satfinite`` is specified, if the absolute value of input (ignoring sign)
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is greater than ``MAX_NORM`` of the specified destination format, then the
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result is sign-preserved ``MAX_NORM`` of the destination format. Also, if the
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input is ``NaN``, then the result is the positive ``MAX_NORM`` of the
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destination format.
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For more information, see `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt>`__.
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Arithmetic Intrinsics
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---------------------
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