From b69f646c46de14279c35c3733e049f1e78e92983 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Sat, 16 Nov 2024 13:14:42 +0300 Subject: [PATCH] [AArch64] Remove unused SDNodes (NFC) (#116236) The corresponding enum members were only used by `EmitMOPS`, which immediately translated them to machine opcodes. Just pass the machine opcodes instead. --- .../Target/AArch64/AArch64ISelLowering.cpp | 10 ++-- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 6 --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 ---- .../AArch64/AArch64SelectionDAGInfo.cpp | 46 +++++++------------ .../Target/AArch64/AArch64SelectionDAGInfo.h | 8 ++-- 5 files changed, 23 insertions(+), 55 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index ff577f238d18..4a9bd819cd2d 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2947,10 +2947,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { MAKE_CASE(AArch64ISD::UADDLP) MAKE_CASE(AArch64ISD::CALL_RVMARKER) MAKE_CASE(AArch64ISD::ASSERT_ZEXT_BOOL) - MAKE_CASE(AArch64ISD::MOPS_MEMSET) - MAKE_CASE(AArch64ISD::MOPS_MEMSET_TAGGING) - MAKE_CASE(AArch64ISD::MOPS_MEMCOPY) - MAKE_CASE(AArch64ISD::MOPS_MEMMOVE) MAKE_CASE(AArch64ISD::CALL_BTI) MAKE_CASE(AArch64ISD::MRRS) MAKE_CASE(AArch64ISD::MSRR) @@ -5925,9 +5921,9 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, const auto &SDI = static_cast(DAG.getSelectionDAGInfo()); - SDValue MS = - SDI.EmitMOPS(AArch64ISD::MOPS_MEMSET_TAGGING, DAG, DL, Chain, Dst, Val, - Size, Alignment, IsVol, DstPtrInfo, MachinePointerInfo{}); + SDValue MS = SDI.EmitMOPS(AArch64::MOPSMemorySetTaggingPseudo, DAG, DL, + Chain, Dst, Val, Size, Alignment, IsVol, + DstPtrInfo, MachinePointerInfo{}); // MOPS_MEMSET_TAGGING has 3 results (DstWb, SizeWb, Chain) whereas the // intrinsic has 2. So hide SizeWb using MERGE_VALUES. Otherwise diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 176ad57a6ed7..cb0b9e965277 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -520,12 +520,6 @@ enum NodeType : unsigned { STP, STILP, STNP, - - // Memory Operations - MOPS_MEMSET, - MOPS_MEMSET_TAGGING, - MOPS_MEMCOPY, - MOPS_MEMMOVE, }; } // end namespace AArch64ISD diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 10e34a83a10d..c8d4291c5f28 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -10077,14 +10077,6 @@ let Predicates = [HasMOPS, HasMTE] in { } } -// MOPS Node operands: 0: Dst, 1: Src or Value, 2: Size, 3: Chain -// MOPS Node results: 0: Dst writeback, 1: Size writeback, 2: Chain -def SDT_AArch64mops : SDTypeProfile<2, 3, [ SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2> ]>; -def AArch64mops_memset : SDNode<"AArch64ISD::MOPS_MEMSET", SDT_AArch64mops>; -def AArch64mops_memset_tagging : SDNode<"AArch64ISD::MOPS_MEMSET_TAGGING", SDT_AArch64mops>; -def AArch64mops_memcopy : SDNode<"AArch64ISD::MOPS_MEMCOPY", SDT_AArch64mops>; -def AArch64mops_memmove : SDNode<"AArch64ISD::MOPS_MEMMOVE", SDT_AArch64mops>; - // MOPS operations always contain three 4-byte instructions let Predicates = [HasMOPS], Defs = [NZCV], Size = 12, mayStore = 1 in { let mayLoad = 1 in { diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp index 525538db8036..c4d60a0cb4a1 100644 --- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp @@ -23,11 +23,11 @@ static cl::opt "to lower to librt functions"), cl::init(true)); -SDValue AArch64SelectionDAGInfo::EmitMOPS(AArch64ISD::NodeType SDOpcode, - SelectionDAG &DAG, const SDLoc &DL, - SDValue Chain, SDValue Dst, - SDValue SrcOrValue, SDValue Size, - Align Alignment, bool isVolatile, +SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG, + const SDLoc &DL, SDValue Chain, + SDValue Dst, SDValue SrcOrValue, + SDValue Size, Align Alignment, + bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { @@ -36,23 +36,8 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(AArch64ISD::NodeType SDOpcode, if (auto *C = dyn_cast(Size)) ConstSize = C->getZExtValue(); - const bool IsSet = SDOpcode == AArch64ISD::MOPS_MEMSET || - SDOpcode == AArch64ISD::MOPS_MEMSET_TAGGING; - - const auto MachineOpcode = [&]() { - switch (SDOpcode) { - case AArch64ISD::MOPS_MEMSET: - return AArch64::MOPSMemorySetPseudo; - case AArch64ISD::MOPS_MEMSET_TAGGING: - return AArch64::MOPSMemorySetTaggingPseudo; - case AArch64ISD::MOPS_MEMCOPY: - return AArch64::MOPSMemoryCopyPseudo; - case AArch64ISD::MOPS_MEMMOVE: - return AArch64::MOPSMemoryMovePseudo; - default: - llvm_unreachable("Unhandled MOPS ISD Opcode"); - } - }(); + const bool IsSet = Opcode == AArch64::MOPSMemorySetPseudo || + Opcode == AArch64::MOPSMemorySetTaggingPseudo; MachineFunction &MF = DAG.getMachineFunction(); @@ -68,13 +53,13 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(AArch64ISD::NodeType SDOpcode, SrcOrValue = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, SrcOrValue); SDValue Ops[] = {Dst, Size, SrcOrValue, Chain}; const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::Other}; - MachineSDNode *Node = DAG.getMachineNode(MachineOpcode, DL, ResultTys, Ops); + MachineSDNode *Node = DAG.getMachineNode(Opcode, DL, ResultTys, Ops); DAG.setNodeMemRefs(Node, {DstOp}); return SDValue(Node, 2); } else { SDValue Ops[] = {Dst, SrcOrValue, Size, Chain}; const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::i64, MVT::Other}; - MachineSDNode *Node = DAG.getMachineNode(MachineOpcode, DL, ResultTys, Ops); + MachineSDNode *Node = DAG.getMachineNode(Opcode, DL, ResultTys, Ops); auto SrcFlags = MachineMemOperand::MOLoad | Vol; auto *SrcOp = @@ -150,8 +135,8 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy( DAG.getMachineFunction().getSubtarget(); if (STI.hasMOPS()) - return EmitMOPS(AArch64ISD::MOPS_MEMCOPY, DAG, DL, Chain, Dst, Src, Size, - Alignment, isVolatile, DstPtrInfo, SrcPtrInfo); + return EmitMOPS(AArch64::MOPSMemoryCopyPseudo, DAG, DL, Chain, Dst, Src, + Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo); SMEAttrs Attrs(DAG.getMachineFunction().getFunction()); if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) @@ -168,8 +153,9 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset( DAG.getMachineFunction().getSubtarget(); if (STI.hasMOPS()) - return EmitMOPS(AArch64ISD::MOPS_MEMSET, DAG, dl, Chain, Dst, Src, Size, - Alignment, isVolatile, DstPtrInfo, MachinePointerInfo{}); + return EmitMOPS(AArch64::MOPSMemorySetPseudo, DAG, dl, Chain, Dst, Src, + Size, Alignment, isVolatile, DstPtrInfo, + MachinePointerInfo{}); SMEAttrs Attrs(DAG.getMachineFunction().getFunction()); if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) @@ -186,8 +172,8 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemmove( DAG.getMachineFunction().getSubtarget(); if (STI.hasMOPS()) - return EmitMOPS(AArch64ISD::MOPS_MEMMOVE, DAG, dl, Chain, Dst, Src, Size, - Alignment, isVolatile, DstPtrInfo, SrcPtrInfo); + return EmitMOPS(AArch64::MOPSMemoryMovePseudo, DAG, dl, Chain, Dst, Src, + Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo); SMEAttrs Attrs(DAG.getMachineFunction().getFunction()); if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h index 514de4477863..9d1f2e9cba84 100644 --- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h +++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h @@ -19,10 +19,10 @@ namespace llvm { class AArch64SelectionDAGInfo : public SelectionDAGTargetInfo { public: - SDValue EmitMOPS(AArch64ISD::NodeType SDOpcode, SelectionDAG &DAG, - const SDLoc &DL, SDValue Chain, SDValue Dst, - SDValue SrcOrValue, SDValue Size, Align Alignment, - bool isVolatile, MachinePointerInfo DstPtrInfo, + SDValue EmitMOPS(unsigned Opcode, SelectionDAG &DAG, const SDLoc &DL, + SDValue Chain, SDValue Dst, SDValue SrcOrValue, SDValue Size, + Align Alignment, bool isVolatile, + MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const; SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,