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[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)

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The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147538
This commit is contained in:
LiaoChunyu 2023-04-07 08:37:21 +08:00
parent c8a2301555
commit b6ea46fe72
11 changed files with 491 additions and 568 deletions
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17
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -9130,10 +9130,23 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
if (SDValue V = combineSubOfBoolean(N, DAG))
return V;
// fold (sub x, (select lhs, rhs, cc, 0, y)) ->
// (select lhs, rhs, cc, x, (sub x, y))
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
// fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
isNullConstant(N1.getOperand(1))) {
ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
if (CCVal == ISD::SETLT) {
EVT VT = N->getValueType(0);
SDLoc DL(N);
unsigned ShAmt = N0.getValueSizeInBits() - 1;
return DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0),
DAG.getConstant(ShAmt, DL, VT));
}
}
// fold (sub x, (select lhs, rhs, cc, 0, y)) ->
// (select lhs, rhs, cc, x, (sub x, y))
return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false, Subtarget);
}

6
llvm/test/CodeGen/RISCV/alu64.ll
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@ -219,8 +219,7 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: slti a0, a4, 0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: srai a0, a4, 31
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: ret
%1 = shl i64 %a, %b
@ -307,8 +306,7 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB15_3:
; RV32I-NEXT: slti a1, a4, 0
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: srai a1, a4, 31
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: ret
%1 = lshr i64 %a, %b

4
llvm/test/CodeGen/RISCV/bittest.ll
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@ -367,7 +367,7 @@ define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
; RV32-NEXT: addi a1, a1, 722
; RV32-NEXT: srl a1, a1, a0
; RV32-NEXT: addi a0, a0, -32
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: ret
;
@ -407,7 +407,7 @@ define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
; RV32-NEXT: addi a1, a1, 722
; RV32-NEXT: srl a1, a1, a0
; RV32-NEXT: addi a0, a0, -32
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: ret
;

12
llvm/test/CodeGen/RISCV/fpclamptosat.ll
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@ -1969,8 +1969,7 @@ define i32 @stest_f64i32_mm(double %x) {
; RV32IF-NEXT: .LBB27_3: # %entry
; RV32IF-NEXT: mv a0, a3
; RV32IF-NEXT: .LBB27_4: # %entry
; RV32IF-NEXT: slti a3, a1, 0
; RV32IF-NEXT: neg a3, a3
; RV32IF-NEXT: srai a3, a1, 31
; RV32IF-NEXT: and a1, a3, a1
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bltz a1, .LBB27_11
@ -2302,8 +2301,7 @@ define i32 @stest_f16i32_mm(half %x) {
; RV32-NEXT: .LBB33_3: # %entry
; RV32-NEXT: mv a0, a3
; RV32-NEXT: .LBB33_4: # %entry
; RV32-NEXT: slti a3, a1, 0
; RV32-NEXT: neg a3, a3
; RV32-NEXT: srai a3, a1, 31
; RV32-NEXT: and a1, a3, a1
; RV32-NEXT: mv a3, a0
; RV32-NEXT: bltz a1, .LBB33_11
@ -3072,8 +3070,7 @@ define i64 @stest_f64i64_mm(double %x) {
; RV64IF-NEXT: .LBB45_3: # %entry
; RV64IF-NEXT: mv a0, a3
; RV64IF-NEXT: .LBB45_4: # %entry
; RV64IF-NEXT: slti a3, a1, 0
; RV64IF-NEXT: neg a3, a3
; RV64IF-NEXT: srai a3, a1, 63
; RV64IF-NEXT: and a1, a3, a1
; RV64IF-NEXT: slli a4, a2, 63
; RV64IF-NEXT: mv a3, a0
@ -3845,8 +3842,7 @@ define i64 @stest_f16i64_mm(half %x) {
; RV64-NEXT: .LBB51_3: # %entry
; RV64-NEXT: mv a0, a3
; RV64-NEXT: .LBB51_4: # %entry
; RV64-NEXT: slti a3, a1, 0
; RV64-NEXT: neg a3, a3
; RV64-NEXT: srai a3, a1, 63
; RV64-NEXT: and a1, a3, a1
; RV64-NEXT: slli a4, a2, 63
; RV64-NEXT: mv a3, a0

714
llvm/test/CodeGen/RISCV/rotl-rotr.ll
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File diff suppressed because it is too large Load Diff

48
llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
View File

@ -5442,15 +5442,13 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-NOV-NEXT: .LBB45_6: # %entry
; CHECK-NOV-NEXT: mv s0, a4
; CHECK-NOV-NEXT: .LBB45_7: # %entry
; CHECK-NOV-NEXT: slti a6, a1, 0
; CHECK-NOV-NEXT: slti a3, s1, 0
; CHECK-NOV-NEXT: neg a4, a3
; CHECK-NOV-NEXT: srai a4, s1, 63
; CHECK-NOV-NEXT: and a4, a4, s1
; CHECK-NOV-NEXT: slli a3, a0, 63
; CHECK-NOV-NEXT: mv a5, s0
; CHECK-NOV-NEXT: bltz a4, .LBB45_20
; CHECK-NOV-NEXT: # %bb.8: # %entry
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: srai a6, a1, 63
; CHECK-NOV-NEXT: bgeu a3, s0, .LBB45_21
; CHECK-NOV-NEXT: .LBB45_9: # %entry
; CHECK-NOV-NEXT: and a1, a6, a1
@ -5492,7 +5490,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-NOV-NEXT: j .LBB45_7
; CHECK-NOV-NEXT: .LBB45_20: # %entry
; CHECK-NOV-NEXT: mv a5, a3
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: srai a6, a1, 63
; CHECK-NOV-NEXT: bltu a3, s0, .LBB45_9
; CHECK-NOV-NEXT: .LBB45_21: # %entry
; CHECK-NOV-NEXT: mv s0, a3
@ -5555,15 +5553,13 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-V-NEXT: .LBB45_6: # %entry
; CHECK-V-NEXT: mv a0, a4
; CHECK-V-NEXT: .LBB45_7: # %entry
; CHECK-V-NEXT: slti a3, s1, 0
; CHECK-V-NEXT: neg a4, a3
; CHECK-V-NEXT: srai a4, s1, 63
; CHECK-V-NEXT: and a4, a4, s1
; CHECK-V-NEXT: slti a6, a1, 0
; CHECK-V-NEXT: slli a3, a2, 63
; CHECK-V-NEXT: mv a5, s0
; CHECK-V-NEXT: bltz a4, .LBB45_20
; CHECK-V-NEXT: # %bb.8: # %entry
; CHECK-V-NEXT: neg a6, a6
; CHECK-V-NEXT: srai a6, a1, 63
; CHECK-V-NEXT: bgeu a3, s0, .LBB45_21
; CHECK-V-NEXT: .LBB45_9: # %entry
; CHECK-V-NEXT: and a1, a6, a1
@ -5609,7 +5605,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-V-NEXT: j .LBB45_7
; CHECK-V-NEXT: .LBB45_20: # %entry
; CHECK-V-NEXT: mv a5, a3
; CHECK-V-NEXT: neg a6, a6
; CHECK-V-NEXT: srai a6, a1, 63
; CHECK-V-NEXT: bltu a3, s0, .LBB45_9
; CHECK-V-NEXT: .LBB45_21: # %entry
; CHECK-V-NEXT: mv s0, a3
@ -5917,15 +5913,13 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-NOV-NEXT: .LBB48_6: # %entry
; CHECK-NOV-NEXT: mv s0, a4
; CHECK-NOV-NEXT: .LBB48_7: # %entry
; CHECK-NOV-NEXT: slti a6, a1, 0
; CHECK-NOV-NEXT: slti a3, s1, 0
; CHECK-NOV-NEXT: neg a4, a3
; CHECK-NOV-NEXT: srai a4, s1, 63
; CHECK-NOV-NEXT: and a4, a4, s1
; CHECK-NOV-NEXT: slli a3, a0, 63
; CHECK-NOV-NEXT: mv a5, s0
; CHECK-NOV-NEXT: bltz a4, .LBB48_20
; CHECK-NOV-NEXT: # %bb.8: # %entry
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: srai a6, a1, 63
; CHECK-NOV-NEXT: bgeu a3, s0, .LBB48_21
; CHECK-NOV-NEXT: .LBB48_9: # %entry
; CHECK-NOV-NEXT: and a1, a6, a1
@ -5967,7 +5961,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-NOV-NEXT: j .LBB48_7
; CHECK-NOV-NEXT: .LBB48_20: # %entry
; CHECK-NOV-NEXT: mv a5, a3
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: srai a6, a1, 63
; CHECK-NOV-NEXT: bltu a3, s0, .LBB48_9
; CHECK-NOV-NEXT: .LBB48_21: # %entry
; CHECK-NOV-NEXT: mv s0, a3
@ -6030,15 +6024,13 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-V-NEXT: .LBB48_6: # %entry
; CHECK-V-NEXT: mv a0, a4
; CHECK-V-NEXT: .LBB48_7: # %entry
; CHECK-V-NEXT: slti a3, s1, 0
; CHECK-V-NEXT: neg a4, a3
; CHECK-V-NEXT: srai a4, s1, 63
; CHECK-V-NEXT: and a4, a4, s1
; CHECK-V-NEXT: slti a6, a1, 0
; CHECK-V-NEXT: slli a3, a2, 63
; CHECK-V-NEXT: mv a5, s0
; CHECK-V-NEXT: bltz a4, .LBB48_20
; CHECK-V-NEXT: # %bb.8: # %entry
; CHECK-V-NEXT: neg a6, a6
; CHECK-V-NEXT: srai a6, a1, 63
; CHECK-V-NEXT: bgeu a3, s0, .LBB48_21
; CHECK-V-NEXT: .LBB48_9: # %entry
; CHECK-V-NEXT: and a1, a6, a1
@ -6084,7 +6076,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-V-NEXT: j .LBB48_7
; CHECK-V-NEXT: .LBB48_20: # %entry
; CHECK-V-NEXT: mv a5, a3
; CHECK-V-NEXT: neg a6, a6
; CHECK-V-NEXT: srai a6, a1, 63
; CHECK-V-NEXT: bltu a3, s0, .LBB48_9
; CHECK-V-NEXT: .LBB48_21: # %entry
; CHECK-V-NEXT: mv s0, a3
@ -6394,15 +6386,13 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-NOV-NEXT: .LBB51_6: # %entry
; CHECK-NOV-NEXT: mv s0, a4
; CHECK-NOV-NEXT: .LBB51_7: # %entry
; CHECK-NOV-NEXT: slti a6, a1, 0
; CHECK-NOV-NEXT: slti a3, s1, 0
; CHECK-NOV-NEXT: neg a4, a3
; CHECK-NOV-NEXT: srai a4, s1, 63
; CHECK-NOV-NEXT: and a4, a4, s1
; CHECK-NOV-NEXT: slli a3, a0, 63
; CHECK-NOV-NEXT: mv a5, s0
; CHECK-NOV-NEXT: bltz a4, .LBB51_20
; CHECK-NOV-NEXT: # %bb.8: # %entry
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: srai a6, a1, 63
; CHECK-NOV-NEXT: bgeu a3, s0, .LBB51_21
; CHECK-NOV-NEXT: .LBB51_9: # %entry
; CHECK-NOV-NEXT: and a1, a6, a1
@ -6444,7 +6434,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-NOV-NEXT: j .LBB51_7
; CHECK-NOV-NEXT: .LBB51_20: # %entry
; CHECK-NOV-NEXT: mv a5, a3
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: srai a6, a1, 63
; CHECK-NOV-NEXT: bltu a3, s0, .LBB51_9
; CHECK-NOV-NEXT: .LBB51_21: # %entry
; CHECK-NOV-NEXT: mv s0, a3
@ -6500,15 +6490,13 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-V-NEXT: .LBB51_6: # %entry
; CHECK-V-NEXT: mv s0, a4
; CHECK-V-NEXT: .LBB51_7: # %entry
; CHECK-V-NEXT: slti a6, a1, 0
; CHECK-V-NEXT: slti a3, s1, 0
; CHECK-V-NEXT: neg a4, a3
; CHECK-V-NEXT: srai a4, s1, 63
; CHECK-V-NEXT: and a4, a4, s1
; CHECK-V-NEXT: slli a3, a2, 63
; CHECK-V-NEXT: mv a5, s0
; CHECK-V-NEXT: bltz a4, .LBB51_20
; CHECK-V-NEXT: # %bb.8: # %entry
; CHECK-V-NEXT: neg a6, a6
; CHECK-V-NEXT: srai a6, a1, 63
; CHECK-V-NEXT: bgeu a3, s0, .LBB51_21
; CHECK-V-NEXT: .LBB51_9: # %entry
; CHECK-V-NEXT: and a1, a6, a1
@ -6552,7 +6540,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-V-NEXT: j .LBB51_7
; CHECK-V-NEXT: .LBB51_20: # %entry
; CHECK-V-NEXT: mv a5, a3
; CHECK-V-NEXT: neg a6, a6
; CHECK-V-NEXT: srai a6, a1, 63
; CHECK-V-NEXT: bltu a3, s0, .LBB51_9
; CHECK-V-NEXT: .LBB51_21: # %entry
; CHECK-V-NEXT: mv s0, a3

36
llvm/test/CodeGen/RISCV/shift-amount-mod.ll
View File

@ -25,12 +25,12 @@ define i64 @shl_by_complemented_64(i64 %x) {
; RV32I-LABEL: shl_by_complemented_64:
; RV32I: # %bb.0:
; RV32I-NEXT: not a4, a0
; RV32I-NEXT: li a3, 31
; RV32I-NEXT: sub a3, a3, a0
; RV32I-NEXT: sll a2, a0, a4
; RV32I-NEXT: bltz a3, .LBB1_2
; RV32I-NEXT: li a2, 31
; RV32I-NEXT: sub a2, a2, a0
; RV32I-NEXT: sll a3, a0, a4
; RV32I-NEXT: bltz a2, .LBB1_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: sll a1, a1, a4
@ -41,9 +41,8 @@ define i64 @shl_by_complemented_64(i64 %x) {
; RV32I-NEXT: srl a0, a0, a4
; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: .LBB1_3:
; RV32I-NEXT: slti a0, a3, 0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: srai a0, a2, 31
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl_by_complemented_64:
@ -77,12 +76,12 @@ define i64 @lshr_by_complemented_64(i64 %x) {
; RV32I-LABEL: lshr_by_complemented_64:
; RV32I: # %bb.0:
; RV32I-NEXT: not a4, a0
; RV32I-NEXT: li a3, 31
; RV32I-NEXT: sub a3, a3, a0
; RV32I-NEXT: srl a2, a1, a4
; RV32I-NEXT: bltz a3, .LBB3_2
; RV32I-NEXT: li a2, 31
; RV32I-NEXT: sub a2, a2, a0
; RV32I-NEXT: srl a3, a1, a4
; RV32I-NEXT: bltz a2, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: srl a4, a0, a4
@ -93,9 +92,8 @@ define i64 @lshr_by_complemented_64(i64 %x) {
; RV32I-NEXT: sll a0, a1, a0
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: slti a1, a3, 0
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srai a1, a2, 31
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr_by_complemented_64:
@ -197,8 +195,7 @@ define i64 @shl_by_masked_complemented_64(i64 %x) {
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: sll a0, a0, a3
; RV32I-NEXT: slti a2, a2, 0
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: srai a2, a2, 31
; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: ret
;
@ -233,8 +230,7 @@ define i64 @lshr_by_masked_complemented_64(i64 %x) {
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: srl a1, a1, a3
; RV32I-NEXT: slti a2, a2, 0
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: srai a2, a2, 31
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: ret
;

10
llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
View File

@ -175,9 +175,8 @@ define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: .LBB9_3:
; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: slti a2, a3, 0
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: srai a3, a3, 31
; RV32I-NEXT: and a0, a3, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sll_redundant_mask_zeros_i64:
@ -209,9 +208,8 @@ define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: .LBB10_3:
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: slti a2, a3, 0
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srai a3, a3, 31
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: srl_redundant_mask_zeros_i64:

12
llvm/test/CodeGen/RISCV/shifts.ll
View File

@ -26,8 +26,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB0_3:
; RV32I-NEXT: slti a1, a4, 0
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: srai a1, a4, 31
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: ret
;
@ -119,8 +118,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: .LBB4_3:
; RV32I-NEXT: slti a0, a4, 0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: srai a0, a4, 31
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: ret
;
@ -285,8 +283,7 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: .LBB6_3:
; RV64I-NEXT: slti a1, a4, 0
; RV64I-NEXT: neg a1, a1
; RV64I-NEXT: srai a1, a4, 63
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: ret
%1 = lshr i128 %a, %b
@ -574,8 +571,7 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a1, a1, a0
; RV64I-NEXT: .LBB8_3:
; RV64I-NEXT: slti a0, a4, 0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: srai a0, a4, 63
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: ret
%1 = shl i128 %a, %b

100
llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
View File

@ -307,17 +307,16 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sll a3, a3, a5
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: slti a3, a4, 0
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: sb a1, 4(a2)
; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: srli a3, a1, 16
; RV32I-NEXT: sb a3, 6(a2)
; RV32I-NEXT: srli a3, a1, 24
; RV32I-NEXT: sb a3, 7(a2)
; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: sb a1, 5(a2)
; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: sb a1, 2(a2)
; RV32I-NEXT: srli a1, a0, 24
@ -444,23 +443,22 @@ define void @shl_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: srl a3, a3, a5
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: .LBB4_3:
; RV32I-NEXT: slti a3, a4, 0
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: sb a0, 4(a2)
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: sb a1, 0(a2)
; RV32I-NEXT: srli a3, a0, 16
; RV32I-NEXT: sb a3, 6(a2)
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: sb a3, 7(a2)
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: srli a0, a1, 16
; RV32I-NEXT: sb a0, 2(a2)
; RV32I-NEXT: srli a0, a1, 24
; RV32I-NEXT: sb a0, 3(a2)
; RV32I-NEXT: sb a0, 4(a2)
; RV32I-NEXT: srli a3, a1, 16
; RV32I-NEXT: sb a3, 2(a2)
; RV32I-NEXT: srli a3, a1, 24
; RV32I-NEXT: sb a3, 3(a2)
; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: sb a1, 1(a2)
; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: sb a1, 6(a2)
; RV32I-NEXT: srli a1, a0, 24
; RV32I-NEXT: sb a1, 7(a2)
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: ret
%src = load i64, ptr %src.ptr, align 1
%byteOff = load i64, ptr %byteOff.ptr, align 1
@ -689,11 +687,9 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sll a3, a3, a5
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: .LBB6_3:
; RV64I-NEXT: slti a3, a4, 0
; RV64I-NEXT: neg a3, a3
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srai a4, a4, 63
; RV64I-NEXT: and a1, a4, a1
; RV64I-NEXT: sb a1, 8(a2)
; RV64I-NEXT: sb a0, 0(a2)
; RV64I-NEXT: srli a3, a1, 56
; RV64I-NEXT: sb a3, 15(a2)
; RV64I-NEXT: srli a3, a1, 48
@ -708,6 +704,7 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sb a3, 10(a2)
; RV64I-NEXT: srli a1, a1, 8
; RV64I-NEXT: sb a1, 9(a2)
; RV64I-NEXT: sb a0, 0(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: sb a1, 7(a2)
; RV64I-NEXT: srli a1, a0, 48
@ -909,39 +906,38 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: srl a3, a3, a5
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: .LBB7_3:
; RV64I-NEXT: slti a3, a4, 0
; RV64I-NEXT: neg a3, a3
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: sb a0, 8(a2)
; RV64I-NEXT: srai a4, a4, 63
; RV64I-NEXT: and a1, a4, a1
; RV64I-NEXT: sb a1, 0(a2)
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: sb a3, 15(a2)
; RV64I-NEXT: srli a3, a0, 48
; RV64I-NEXT: sb a3, 14(a2)
; RV64I-NEXT: srli a3, a0, 40
; RV64I-NEXT: sb a3, 13(a2)
; RV64I-NEXT: srli a3, a0, 32
; RV64I-NEXT: sb a3, 12(a2)
; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: sb a3, 11(a2)
; RV64I-NEXT: srli a3, a0, 16
; RV64I-NEXT: sb a3, 10(a2)
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: sb a0, 9(a2)
; RV64I-NEXT: srli a0, a1, 56
; RV64I-NEXT: sb a0, 7(a2)
; RV64I-NEXT: srli a0, a1, 48
; RV64I-NEXT: sb a0, 6(a2)
; RV64I-NEXT: srli a0, a1, 40
; RV64I-NEXT: sb a0, 5(a2)
; RV64I-NEXT: srli a0, a1, 32
; RV64I-NEXT: sb a0, 4(a2)
; RV64I-NEXT: srli a0, a1, 24
; RV64I-NEXT: sb a0, 3(a2)
; RV64I-NEXT: srli a0, a1, 16
; RV64I-NEXT: sb a0, 2(a2)
; RV64I-NEXT: sb a0, 8(a2)
; RV64I-NEXT: srli a3, a1, 56
; RV64I-NEXT: sb a3, 7(a2)
; RV64I-NEXT: srli a3, a1, 48
; RV64I-NEXT: sb a3, 6(a2)
; RV64I-NEXT: srli a3, a1, 40
; RV64I-NEXT: sb a3, 5(a2)
; RV64I-NEXT: srli a3, a1, 32
; RV64I-NEXT: sb a3, 4(a2)
; RV64I-NEXT: srli a3, a1, 24
; RV64I-NEXT: sb a3, 3(a2)
; RV64I-NEXT: srli a3, a1, 16
; RV64I-NEXT: sb a3, 2(a2)
; RV64I-NEXT: srli a1, a1, 8
; RV64I-NEXT: sb a1, 1(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: sb a1, 15(a2)
; RV64I-NEXT: srli a1, a0, 48
; RV64I-NEXT: sb a1, 14(a2)
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: sb a1, 13(a2)
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: sb a1, 12(a2)
; RV64I-NEXT: srli a1, a0, 24
; RV64I-NEXT: sb a1, 11(a2)
; RV64I-NEXT: srli a1, a0, 16
; RV64I-NEXT: sb a1, 10(a2)
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: sb a0, 9(a2)
; RV64I-NEXT: ret
;
; RV32I-LABEL: shl_16bytes:

100
llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
View File

@ -296,17 +296,16 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sll a3, a3, a5
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: slti a3, a4, 0
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: sb a1, 4(a2)
; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: srli a3, a1, 16
; RV32I-NEXT: sb a3, 6(a2)
; RV32I-NEXT: srli a3, a1, 24
; RV32I-NEXT: sb a3, 7(a2)
; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: sb a1, 5(a2)
; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: sb a1, 2(a2)
; RV32I-NEXT: srli a1, a0, 24
@ -430,23 +429,22 @@ define void @shl_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: srl a3, a3, a5
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: .LBB4_3:
; RV32I-NEXT: slti a3, a4, 0
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: sb a0, 4(a2)
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: sb a1, 0(a2)
; RV32I-NEXT: srli a3, a0, 16
; RV32I-NEXT: sb a3, 6(a2)
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: sb a3, 7(a2)
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: srli a0, a1, 16
; RV32I-NEXT: sb a0, 2(a2)
; RV32I-NEXT: srli a0, a1, 24
; RV32I-NEXT: sb a0, 3(a2)
; RV32I-NEXT: sb a0, 4(a2)
; RV32I-NEXT: srli a3, a1, 16
; RV32I-NEXT: sb a3, 2(a2)
; RV32I-NEXT: srli a3, a1, 24
; RV32I-NEXT: sb a3, 3(a2)
; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: sb a1, 1(a2)
; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: sb a1, 6(a2)
; RV32I-NEXT: srli a1, a0, 24
; RV32I-NEXT: sb a1, 7(a2)
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: sb a0, 5(a2)
; RV32I-NEXT: ret
%src = load i64, ptr %src.ptr, align 1
%bitOff = load i64, ptr %bitOff.ptr, align 1
@ -670,11 +668,9 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sll a3, a3, a5
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: .LBB6_3:
; RV64I-NEXT: slti a3, a4, 0
; RV64I-NEXT: neg a3, a3
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srai a4, a4, 63
; RV64I-NEXT: and a1, a4, a1
; RV64I-NEXT: sb a1, 8(a2)
; RV64I-NEXT: sb a0, 0(a2)
; RV64I-NEXT: srli a3, a1, 56
; RV64I-NEXT: sb a3, 15(a2)
; RV64I-NEXT: srli a3, a1, 48
@ -689,6 +685,7 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sb a3, 10(a2)
; RV64I-NEXT: srli a1, a1, 8
; RV64I-NEXT: sb a1, 9(a2)
; RV64I-NEXT: sb a0, 0(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: sb a1, 7(a2)
; RV64I-NEXT: srli a1, a0, 48
@ -954,39 +951,38 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: srl a3, a3, a5
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: .LBB7_3:
; RV64I-NEXT: slti a3, a4, 0
; RV64I-NEXT: neg a3, a3
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: sb a0, 8(a2)
; RV64I-NEXT: srai a4, a4, 63
; RV64I-NEXT: and a1, a4, a1
; RV64I-NEXT: sb a1, 0(a2)
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: sb a3, 15(a2)
; RV64I-NEXT: srli a3, a0, 48
; RV64I-NEXT: sb a3, 14(a2)
; RV64I-NEXT: srli a3, a0, 40
; RV64I-NEXT: sb a3, 13(a2)
; RV64I-NEXT: srli a3, a0, 32
; RV64I-NEXT: sb a3, 12(a2)
; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: sb a3, 11(a2)
; RV64I-NEXT: srli a3, a0, 16
; RV64I-NEXT: sb a3, 10(a2)
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: sb a0, 9(a2)
; RV64I-NEXT: srli a0, a1, 56
; RV64I-NEXT: sb a0, 7(a2)
; RV64I-NEXT: srli a0, a1, 48
; RV64I-NEXT: sb a0, 6(a2)
; RV64I-NEXT: srli a0, a1, 40
; RV64I-NEXT: sb a0, 5(a2)
; RV64I-NEXT: srli a0, a1, 32
; RV64I-NEXT: sb a0, 4(a2)
; RV64I-NEXT: srli a0, a1, 24
; RV64I-NEXT: sb a0, 3(a2)
; RV64I-NEXT: srli a0, a1, 16
; RV64I-NEXT: sb a0, 2(a2)
; RV64I-NEXT: sb a0, 8(a2)
; RV64I-NEXT: srli a3, a1, 56
; RV64I-NEXT: sb a3, 7(a2)
; RV64I-NEXT: srli a3, a1, 48
; RV64I-NEXT: sb a3, 6(a2)
; RV64I-NEXT: srli a3, a1, 40
; RV64I-NEXT: sb a3, 5(a2)
; RV64I-NEXT: srli a3, a1, 32
; RV64I-NEXT: sb a3, 4(a2)
; RV64I-NEXT: srli a3, a1, 24
; RV64I-NEXT: sb a3, 3(a2)
; RV64I-NEXT: srli a3, a1, 16
; RV64I-NEXT: sb a3, 2(a2)
; RV64I-NEXT: srli a1, a1, 8
; RV64I-NEXT: sb a1, 1(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: sb a1, 15(a2)
; RV64I-NEXT: srli a1, a0, 48
; RV64I-NEXT: sb a1, 14(a2)
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: sb a1, 13(a2)
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: sb a1, 12(a2)
; RV64I-NEXT: srli a1, a0, 24
; RV64I-NEXT: sb a1, 11(a2)
; RV64I-NEXT: srli a1, a0, 16
; RV64I-NEXT: sb a1, 10(a2)
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: sb a0, 9(a2)
; RV64I-NEXT: ret
;
; RV32I-LABEL: shl_16bytes: