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[WebAssembly] Rematerialize constants rather than hold them live in registers.

Browse Source 
Teach the register stackifier to rematerialize constants that have multiple
uses instead of leaving them in registers. In the WebAssembly encoding, it's
the same code size to materialize most constants as it is to read a value
from a register.

llvm-svn: 258142
This commit is contained in:
Dan Gohman 2016-01-19 16:59:23 +00:00
parent 1a7e8b4bc1
commit b6fd39a3a7
12 changed files with 157 additions and 99 deletions
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26
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
View File

@ -32,6 +32,21 @@ WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
WebAssembly::ADJCALLSTACKUP),
RI(STI.getTargetTriple()) {}
bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
const MachineInstr *MI, AliasAnalysis *AA) const {
switch (MI->getOpcode()) {
case WebAssembly::CONST_I32:
case WebAssembly::CONST_I64:
case WebAssembly::CONST_F32:
case WebAssembly::CONST_F64:
// isReallyTriviallyReMaterializableGeneric misses these because of the
// ARGUMENTS implicit def, so we manualy override it here.
return true;
default:
return false;
}
}
void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
DebugLoc DL, unsigned DestReg,
@ -39,9 +54,10 @@ void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// This method is called by post-RA expansion, which expects only pregs to
// exist. However we need to handle both here.
auto &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(DestReg) ?
MRI.getRegClass(DestReg) :
MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(SrcReg);
const TargetRegisterClass *RC =
TargetRegisterInfo::isVirtualRegister(DestReg)
? MRI.getRegClass(DestReg)
: MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(SrcReg);
unsigned CopyLocalOpcode;
if (RC == &WebAssembly::I32RegClass)
@ -145,9 +161,7 @@ unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
assert(Cond.size() == 2 && "Expected a flag and a successor block");
if (Cond[0].getImm()) {
BuildMI(&MBB, DL, get(WebAssembly::BR_IF))
.addOperand(Cond[1])
.addMBB(TBB);
BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addOperand(Cond[1]).addMBB(TBB);
} else {
BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
.addOperand(Cond[1])

3
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
View File

@ -34,6 +34,9 @@ public:
const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
AliasAnalysis *AA) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
DebugLoc DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;

4
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
View File

@ -123,7 +123,7 @@ defm : LOCAL<I64>;
defm : LOCAL<F32>;
defm : LOCAL<F64>;
let isMoveImm = 1 in {
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm),
[(set I32:$res, imm:$imm)],
"i32.const\t$res, $imm">;
@ -136,7 +136,7 @@ def CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
def CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
[(set F64:$res, fpimm:$imm)],
"f64.const\t$res, $imm">;
} // isMoveImm = 1
} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
} // Defs = [ARGUMENTS]

82
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
View File

@ -23,6 +23,7 @@
#include "WebAssembly.h"
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" // for WebAssembly::ARGUMENT_*
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
@ -116,9 +117,9 @@ static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert,
// Ask LiveIntervals whether moving this virtual register use or def to
// Insert will change value numbers are seen.
const LiveInterval &LI = LIS.getInterval(Reg);
VNInfo *DefVNI = MO.isDef() ?
LI.getVNInfoAt(LIS.getInstructionIndex(Def).getRegSlot()) :
LI.getVNInfoBefore(LIS.getInstructionIndex(Def));
VNInfo *DefVNI =
MO.isDef() ? LI.getVNInfoAt(LIS.getInstructionIndex(Def).getRegSlot())
: LI.getVNInfoBefore(LIS.getInstructionIndex(Def));
assert(DefVNI && "Instruction input missing value number");
VNInfo *InsVNI = LI.getVNInfoBefore(LIS.getInstructionIndex(Insert));
if (InsVNI && DefVNI != InsVNI)
@ -140,6 +141,8 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
MachineRegisterInfo &MRI = MF.getRegInfo();
WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
const auto *TRI = MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
AliasAnalysis &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
LiveIntervals &LIS = getAnalysis<LiveIntervals>();
@ -176,10 +179,6 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
if (!Def)
continue;
// There's no use in nesting implicit defs inside anything.
if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF)
continue;
// Don't nest an INLINE_ASM def into anything, because we don't have
// constraints for $pop outputs.
if (Def->getOpcode() == TargetOpcode::INLINEASM)
@ -197,30 +196,51 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
Def->getOpcode() == WebAssembly::ARGUMENT_F64)
continue;
// Single-use expression trees require defs that have one use.
// TODO: Eventually we'll relax this, to take advantage of set_local
// returning its result.
if (!MRI.hasOneUse(Reg))
continue;
if (MRI.hasOneUse(Reg) && Def->getParent() == &MBB &&
IsSafeToMove(Def, Insert, AA, LIS, MRI)) {
// A single-use def in the same block with no intervening memory or
// register dependencies; move the def down and nest it with the
// current instruction.
// TODO: Stackify multiple-use values, taking advantage of set_local
// returning its result.
Changed = true;
AnyStackified = true;
MBB.splice(Insert, &MBB, Def);
LIS.handleMove(Def);
MFI.stackifyVReg(Reg);
ImposeStackOrdering(Def);
Insert = Def;
} else if (Def->isAsCheapAsAMove() &&
TII->isTriviallyReMaterializable(Def, &AA)) {
// A trivially cloneable instruction; clone it and nest the new copy
// with the current instruction.
Changed = true;
AnyStackified = true;
unsigned OldReg = Def->getOperand(0).getReg();
unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI);
Op.setReg(NewReg);
MachineInstr *Clone =
&*std::prev(MachineBasicBlock::instr_iterator(Insert));
LIS.InsertMachineInstrInMaps(Clone);
LIS.createAndComputeVirtRegInterval(NewReg);
MFI.stackifyVReg(NewReg);
ImposeStackOrdering(Clone);
Insert = Clone;
// For now, be conservative and don't look across block boundaries.
// TODO: Be more aggressive?
if (Def->getParent() != &MBB)
continue;
// Don't move instructions that have side effects or memory dependencies
// or other complications.
if (!IsSafeToMove(Def, Insert, AA, LIS, MRI))
continue;
Changed = true;
AnyStackified = true;
// Move the def down and nest it in the current instruction.
MBB.splice(Insert, &MBB, Def);
LIS.handleMove(Def);
MFI.stackifyVReg(Reg);
ImposeStackOrdering(Def);
Insert = Def;
// If that was the last use of the original, delete the original.
// Otherwise shrink the LiveInterval.
if (MRI.use_empty(OldReg)) {
SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
LIS.removeVRegDefAt(LIS.getInterval(OldReg), Idx);
LIS.removeInterval(OldReg);
LIS.RemoveMachineInstrFromMaps(Def);
Def->eraseFromParent();
} else {
LIS.shrinkToUses(&LIS.getInterval(OldReg));
}
}
}
if (AnyStackified)
ImposeStackOrdering(&*MII);
@ -236,7 +256,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
}
#ifndef NDEBUG
// Verify that pushes and pops are performed in FIFO order.
// Verify that pushes and pops are performed in LIFO order.
SmallVector<unsigned, 0> Stack;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {

49
llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
View File

@ -147,7 +147,8 @@ for.end:
; CHECK-NEXT: end_block{{$}}
; CHECK: .LBB3_5:
; CHECK-NEXT: end_block{{$}}
; CHECK: return ${{[0-9]+}}{{$}}
; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
; OPT-LABEL: doublediamond:
; OPT: block{{$}}
; OPT-NEXT: block{{$}}
@ -157,7 +158,8 @@ for.end:
; OPT: br 1{{$}}
; OPT: .LBB3_4:
; OPT: .LBB3_5:
; OPT: return ${{[0-9]+}}{{$}}
; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
define i32 @doublediamond(i32 %a, i32 %b, i32* %p) {
entry:
%c = icmp eq i32 %a, 0
@ -211,7 +213,8 @@ exit:
; CHECK: br 1{{$}}
; CHECK: .LBB5_2:
; CHECK: .LBB5_3:
; CHECK: return ${{[0-9]+}}{{$}}
; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
; OPT-LABEL: diamond:
; OPT: block{{$}}
; OPT: block{{$}}
@ -219,7 +222,8 @@ exit:
; OPT: br 1{{$}}
; OPT: .LBB5_2:
; OPT: .LBB5_3:
; OPT: return ${{[0-9]+}}{{$}}
; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
define i32 @diamond(i32* %p, i32 %a) {
entry:
%c = icmp eq i32 %a, 0
@ -275,14 +279,16 @@ loop:
; CHECK: loop{{$}}
; CHECK: br_if $pop{{[0-9]+}}, 0{{$}}
; CHECK-NEXT: end_loop{{$}}
; CHECK: return ${{[0-9]+}}{{$}}
; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
; OPT-LABEL: simple_loop:
; OPT-NOT: br
; OPT: .LBB8_1:
; OPT: loop{{$}}
; OPT: br_if {{[^,]*}}, 0{{$}}
; OPT-NEXT: end_loop{{$}}
; OPT: return ${{[0-9]+}}{{$}}
; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
define i32 @simple_loop(i32* %p, i32 %a) {
entry:
%c = icmp eq i32 %a, 0
@ -340,7 +346,8 @@ exit:
; CHECK: .LBB10_2:
; CHECK: br_if $1, 0{{$}}
; CHECK: .LBB10_4:
; CHECK: return ${{[0-9]+}}{{$}}
; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
; OPT-LABEL: ifelse_earlyexits:
; OPT: block{{$}}
; OPT: block{{$}}
@ -349,7 +356,8 @@ exit:
; OPT: br 1{{$}}
; OPT: .LBB10_3:
; OPT: .LBB10_4:
; OPT: return ${{[0-9]+}}{{$}}
; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
define i32 @ifelse_earlyexits(i32 %a, i32 %b, i32* %p) {
entry:
%c = icmp eq i32 %a, 0
@ -733,6 +741,7 @@ u1:
; CHECK-NEXT: .LBB17_3:
; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: loop{{$}}
; CHECK-NEXT: i32.const $push{{[^,]*}}, 0{{$}}
; CHECK-NEXT: br_if {{[^,]*}}, 0{{$}}
; CHECK-NEXT: br 2{{$}}
; CHECK-NEXT: .LBB17_4:
@ -747,6 +756,7 @@ u1:
; OPT-NEXT: .LBB17_3:
; OPT-NEXT: end_block{{$}}
; OPT-NEXT: loop{{$}}
; OPT-NEXT: i32.const $push{{[^,]*}}, 0{{$}}
; OPT-NEXT: br_if {{[^,]*}}, 0{{$}}
; OPT-NEXT: br 2{{$}}
; OPT-NEXT: .LBB17_4:
@ -938,7 +948,7 @@ bb6:
; CHECK-NEXT: block{{$}}
; CHECK-NEXT: block{{$}}
; CHECK-NEXT: block{{$}}
; CHECK-NEXT: br_if {{[^,]*}}, 0{{$}}
; CHECK: br_if {{[^,]*}}, 0{{$}}
; CHECK-NEXT: block{{$}}
; CHECK-NOT: block
; CHECK: br_if {{[^,]*}}, 0{{$}}
@ -969,12 +979,12 @@ bb6:
; OPT-LABEL: test11:
; OPT: block{{$}}
; OPT-NEXT: block{{$}}
; OPT-NEXT: br_if $0, 0{{$}}
; OPT: br_if $0, 0{{$}}
; OPT-NEXT: block{{$}}
; OPT-NOT: block
; OPT: br_if $0, 0{{$}}
; OPT-NOT: block
; OPT: br_if $0, 2{{$}}
; OPT: br_if {{[^,]*}}, 2{{$}}
; OPT-NEXT: .LBB20_3:
; OPT-NEXT: end_block{{$}}
; OPT-NOT: block
@ -984,13 +994,13 @@ bb6:
; OPT-NOT: block
; OPT: block{{$}}
; OPT-NOT: block
; OPT: br_if $pop9, 0{{$}}
; OPT: br_if $pop{{[0-9]+}}, 0{{$}}
; OPT-NOT: block
; OPT: return{{$}}
; OPT-NEXT: .LBB20_6:
; OPT-NEXT: end_block{{$}}
; OPT-NOT: block
; OPT: br_if $0, 0{{$}}
; OPT: br_if $pop{{[0-9]+}}, 0{{$}}
; OPT-NOT: block
; OPT: return{{$}}
; OPT-NEXT: .LBB20_8:
@ -1109,7 +1119,7 @@ bb7:
; optnone to disable optimizations to test this case.
; CHECK-LABEL: test13:
; CHECK-NEXT: local i32{{$}}
; CHECK-NEXT: .local i32{{$}}
; CHECK: block{{$}}
; CHECK: br_if $pop4, 0{{$}}
; CHECK-NEXT: return{{$}}
@ -1124,7 +1134,7 @@ bb7:
; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: unreachable{{$}}
; OPT-LABEL: test13:
; OPT-NEXT: local i32{{$}}
; OPT-NEXT: .local i32{{$}}
; OPT: block{{$}}
; OPT: br_if $pop4, 0{{$}}
; OPT-NEXT: return{{$}}
@ -1159,15 +1169,16 @@ bb5:
; before the loop for the second.
; CHECK-LABEL: test14:
; CHECK-NEXT: local i32{{$}}
; CHECK-NEXT: i32.const $0=, 0{{$}}
; CHECK-NEXT: .LBB23_1:{{$}}
; CHECK-NEXT: loop{{$}}
; CHECK-NEXT: br_if $0, 0{{$}}
; CHECK-NEXT: i32.const $push0=, 0{{$}}
; CHECK-NEXT: br_if $pop0, 0{{$}}
; CHECK-NEXT: .LBB23_2:{{$}}
; CHECK-NEXT: end_loop{{$}}
; CHECK-NEXT: loop{{$}}
; CHECK-NEXT: br_if $0, 0{{$}}
; CHECK-NEXT: i32.const $push1=, 0{{$}}
; CHECK-NEXT: i32.const $push2=, 0{{$}}
; CHECK-NEXT: br_if $pop2, 0{{$}}
; CHECK-NEXT: end_loop{{$}}
; CHECK-NEXT: return{{$}}
define void @test14() {

2
llvm/test/CodeGen/WebAssembly/dead-vreg.ll
View File

@ -8,7 +8,7 @@ target triple = "wasm32-unknown-unknown"
define void @foo(i32* nocapture %a, i32 %w, i32 %h) {
; CHECK-LABEL: foo:
; CHECK-NEXT: .param i32, i32, i32{{$}}
; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32, i32{{$}}
; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32{{$}}
entry:
%cmp.19 = icmp sgt i32 %h, 0
br i1 %cmp.19, label %for.cond.1.preheader.lr.ph, label %for.end.7

3
llvm/test/CodeGen/WebAssembly/func.ll
View File

@ -44,7 +44,8 @@ define void @f3(i32 %p1, float %p2) {
; CHECK-LABEL: f4:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
; CHECK-NEXT: local
; CHECK-NOT: local
; CHECK: .size f4,
define i32 @f4(i32 %x) {
entry:
%c = trunc i32 %x to i1

18
llvm/test/CodeGen/WebAssembly/load-store-i1.ll
View File

@ -15,10 +15,11 @@ define i32 @load_u_i1_i32(i1* %p) {
}
; CHECK-LABEL: load_s_i1_i32:
; CHECK: i32.const $[[NUM1:[0-9]+]]=, 31{{$}}
; CHECK-NEXT: i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $[[NUM1]]{{$}}
; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM1]]{{$}}
; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: i32.const $push[[NUM1:[0-9]+]]=, 31{{$}}
; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM4:[0-9]+]]=, 31{{$}}
; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $pop[[NUM4]]{{$}}
; CHECK-NEXT: return $pop[[NUM3]]{{$}}
define i32 @load_s_i1_i32(i1* %p) {
%v = load i1, i1* %p
@ -36,10 +37,11 @@ define i64 @load_u_i1_i64(i1* %p) {
}
; CHECK-LABEL: load_s_i1_i64:
; CHECK: i64.const $[[NUM1:[0-9]+]]=, 63{{$}}
; CHECK-NEXT: i64.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $[[NUM1]]{{$}}
; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM1]]{{$}}
; CHECK: i64.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: i64.const $push[[NUM1:[0-9]+]]=, 63{{$}}
; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: i64.const $push[[NUM4:[0-9]+]]=, 63{{$}}
; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $pop[[NUM4]]{{$}}
; CHECK-NEXT: return $pop[[NUM3]]{{$}}
define i64 @load_s_i1_i64(i1* %p) {
%v = load i1, i1* %p

10
llvm/test/CodeGen/WebAssembly/offset.ll
View File

@ -266,8 +266,9 @@ define i32 @load_i32_from_global_address() {
}
; CHECK-LABEL: store_i32_to_numeric_address:
; CHECK: i32.const $0=, 0{{$}}
; CHECK: i32.store $discard=, 42($0), $0{{$}}
; CHECK-NEXT: i32.const $push0=, 0{{$}}
; CHECK-NEXT: i32.const $push1=, 0{{$}}
; CHECK-NEXT: i32.store $discard=, 42($pop0), $pop1{{$}}
define void @store_i32_to_numeric_address() {
%s = inttoptr i32 42 to i32*
store i32 0, i32* %s
@ -275,8 +276,9 @@ define void @store_i32_to_numeric_address() {
}
; CHECK-LABEL: store_i32_to_global_address:
; CHECK: i32.const $0=, 0{{$}}
; CHECK: i32.store $discard=, gv($0), $0{{$}}
; CHECK: i32.const $push0=, 0{{$}}
; CHECK: i32.const $push1=, 0{{$}}
; CHECK: i32.store $discard=, gv($pop0), $pop1{{$}}
define void @store_i32_to_global_address() {
store i32 0, i32* @gv
ret void

33
llvm/test/CodeGen/WebAssembly/reg-stackify.ll
View File

@ -52,24 +52,27 @@ define i32 @yes1(i32* %q) {
; CHECK-LABEL: stack_uses:
; CHECK-NEXT: .param i32, i32, i32, i32{{$}}
; CHECK-NEXT: .result i32{{$}}
; CHECK-NEXT: .local i32, i32{{$}}
; CHECK-NEXT: i32.const $5=, 2{{$}}
; CHECK-NEXT: i32.const $4=, 1{{$}}
; CHECK-NEXT: block{{$}}
; CHECK-NEXT: i32.lt_s $push0=, $0, $4{{$}}
; CHECK-NEXT: i32.lt_s $push1=, $1, $5{{$}}
; CHECK-NEXT: i32.xor $push4=, $pop0, $pop1{{$}}
; CHECK-NEXT: i32.lt_s $push2=, $2, $4{{$}}
; CHECK-NEXT: i32.lt_s $push3=, $3, $5{{$}}
; CHECK-NEXT: i32.xor $push5=, $pop2, $pop3{{$}}
; CHECK-NEXT: i32.xor $push6=, $pop4, $pop5{{$}}
; CHECK-NEXT: i32.ne $push7=, $pop6, $4{{$}}
; CHECK-NEXT: br_if $pop7, 0{{$}}
; CHECK-NEXT: i32.const $push8=, 0{{$}}
; CHECK-NEXT: return $pop8{{$}}
; CHECK-NEXT: i32.const $push13=, 1{{$}}
; CHECK-NEXT: i32.lt_s $push0=, $0, $pop13{{$}}
; CHECK-NEXT: i32.const $push1=, 2{{$}}
; CHECK-NEXT: i32.lt_s $push2=, $1, $pop1{{$}}
; CHECK-NEXT: i32.xor $push5=, $pop0, $pop2{{$}}
; CHECK-NEXT: i32.const $push12=, 1{{$}}
; CHECK-NEXT: i32.lt_s $push3=, $2, $pop12{{$}}
; CHECK-NEXT: i32.const $push11=, 2{{$}}
; CHECK-NEXT: i32.lt_s $push4=, $3, $pop11{{$}}
; CHECK-NEXT: i32.xor $push6=, $pop3, $pop4{{$}}
; CHECK-NEXT: i32.xor $push7=, $pop5, $pop6{{$}}
; CHECK-NEXT: i32.const $push10=, 1{{$}}
; CHECK-NEXT: i32.ne $push8=, $pop7, $pop10{{$}}
; CHECK-NEXT: br_if $pop8, 0{{$}}
; CHECK-NEXT: i32.const $push9=, 0{{$}}
; CHECK-NEXT: return $pop9{{$}}
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: return $4{{$}}
; CHECK-NEXT: i32.const $push14=, 1{{$}}
; CHECK-NEXT: return $pop14{{$}}
define i32 @stack_uses(i32 %x, i32 %y, i32 %z, i32 %w) {
entry:
%c = icmp sle i32 %x, 0

22
llvm/test/CodeGen/WebAssembly/signext-zeroext.ll
View File

@ -8,10 +8,10 @@ target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: z2s_func:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
; CHECK-NEXT: .local i32{{$}}
; CHECK-NEXT: i32.const $[[NUM0:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shl $push[[NUM2:[0-9]+]]=, $0, $[[NUM0]]{{$}}
; CHECK-NEXT: i32.shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM0]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM0:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shl $push[[NUM2:[0-9]+]]=, $0, $pop[[NUM0]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM1:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: return $pop[[NUM3]]{{$}}
define signext i8 @z2s_func(i8 zeroext %t) {
ret i8 %t
@ -44,13 +44,15 @@ define i32 @z2s_call(i32 %t) {
; CHECK-LABEL: s2z_call:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
; CHECK-NEXT: .local i32{{$}}
; CHECK-NEXT: i32.const $[[NUM0:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shl $push[[NUM1:[0-9]+]]=, $0, $[[NUM0]]{{$}}
; CHECK-NEXT: i32.shr_s $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $[[NUM0]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM0:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shl $push[[NUM1:[0-9]+]]=, $0, $pop[[NUM0]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM6:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shr_s $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM6]]{{$}}
; CHECK-NEXT: call $push[[NUM3:[0-9]]]=, s2z_func@FUNCTION, $pop[[NUM2]]{{$}}
; CHECK-NEXT: i32.shl $push[[NUM4:[0-9]+]]=, $pop[[NUM3]], $[[NUM0]]{{$}}
; CHECK-NEXT: i32.shr_s $push[[NUM5:[0-9]+]]=, $pop[[NUM4]], $[[NUM0]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM7:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shl $push[[NUM4:[0-9]+]]=, $pop[[NUM3]], $pop[[NUM7]]{{$}}
; CHECK-NEXT: i32.const $push[[NUM8:[0-9]+]]=, 24{{$}}
; CHECK-NEXT: i32.shr_s $push[[NUM5:[0-9]+]]=, $pop[[NUM4]], $pop[[NUM8]]{{$}}
; CHECK-NEXT: return $pop[[NUM5]]{{$}}
define i32 @s2z_call(i32 %t) {
%s = trunc i32 %t to i8

4
llvm/test/CodeGen/WebAssembly/store-results.ll
View File

@ -26,7 +26,7 @@ entry:
@pos = global %class.Vec3 zeroinitializer, align 4
; CHECK-LABEL: foo:
; CHECK: i32.store $discard=, pos($0), $0{{$}}
; CHECK: i32.store $discard=, pos($pop{{[0-9]+}}), $pop{{[0-9]+}}{{$}}
define void @foo() {
for.body.i:
br label %for.body5.i
@ -44,7 +44,7 @@ for.cond.cleanup4.i:
}
; CHECK-LABEL: bar:
; CHECK: i32.store $discard=, pos($0), $0{{$}}
; CHECK: i32.store $discard=, pos($pop{{[0-9]+}}), $pop{{[0-9]+}}{{$}}
define void @bar() {
for.body.i:
br label %for.body5.i