From b94c5e097b4c69e58140d494bbb21265fc0df1a6 Mon Sep 17 00:00:00 2001 From: vangthao95 Date: Fri, 23 Jan 2026 10:49:14 -0800 Subject: [PATCH] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525) --- .../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +- llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll | 102 +++++++++++++++--- llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll | 35 +++++- llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll | 48 +++++++-- 4 files changed, 159 insertions(+), 28 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index b238d55def8c..54ac3789ca02 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1058,7 +1058,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}); - addRulesForGOpcs({G_FLDEXP}, Standard) + addRulesForGOpcs({G_FLDEXP, G_STRICT_FLDEXP}, Standard) .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}}) .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}) diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll index 98d0a6281054..fd313a76fc67 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll @@ -6,11 +6,11 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s -; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s +; XUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s ; define half @test_ldexp_f16_i16(ptr addrspace(1) %out, half %a, i16 %b) #0 { ; %result = call half @llvm.experimental.constrained.ldexp.f16.i16(half %a, i16 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") @@ -287,11 +287,12 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a, ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff ; GFX9-GISEL-NEXT: v_med3_i32 v4, v4, v0, v1 ; GFX9-GISEL-NEXT: v_med3_i32 v5, v5, v0, v1 +; GFX9-GISEL-NEXT: v_med3_i32 v0, v6, v0, v1 ; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v4, v2, v4 ; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-GISEL-NEXT: v_med3_i32 v0, v6, v0, v1 ; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v3, v0 ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v4 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-GISEL-TRUE16-LABEL: test_ldexp_v3f16_v3i32: @@ -312,18 +313,21 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a, ; GFX11-GISEL-FAKE16: ; %bb.0: ; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff -; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v4, v0 -; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v5, 0xffff8000, v5, v0 -; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v2, v1 -; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v2, v4, v5 ; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v4, 0xffff8000, v6, v0 +; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v5, v0 +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v2, v1 +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v2, v3, v4 +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v6, v0 +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v1 -; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v4 +; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 ; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] %result = call <3 x half> @llvm.experimental.constrained.ldexp.v3f16.v3i32(<3 x half> %a, <3 x i32> %b, metadata !"round.dynamic", metadata !"fpexcept.strict") ret <3 x half> %result @@ -482,6 +486,74 @@ define <4 x half> @test_ldexp_v4f16_v4i32(ptr addrspace(1) %out, <4 x half> %a, ret <4 x half> %result } +define amdgpu_ps half @s_test_ldexp_f16_i32(half inreg %a, i32 inreg %b) #0 { +; GFX8-SDAG-LABEL: s_test_ldexp_f16_i32: +; GFX8-SDAG: ; %bb.0: +; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0xffff8000 +; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX8-SDAG-NEXT: v_med3_i32 v0, s1, v0, v1 +; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, s0, v0 +; GFX8-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-SDAG-LABEL: s_test_ldexp_f16_i32: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0xffff8000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX9-SDAG-NEXT: v_med3_i32 v0, s1, v0, v1 +; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, s0, v0 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX11-SDAG-TRUE16-LABEL: s_test_ldexp_f16_i32: +; GFX11-SDAG-TRUE16: ; %bb.0: +; GFX11-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, 0x7fff +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, s1, v0 +; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, s0, v0.l +; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog +; +; GFX11-SDAG-FAKE16-LABEL: s_test_ldexp_f16_i32: +; GFX11-SDAG-FAKE16: ; %bb.0: +; GFX11-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff +; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, s1, v0 +; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, s0, v0 +; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog +; +; GFX8-GISEL-LABEL: s_test_ldexp_f16_i32: +; GFX8-GISEL: ; %bb.0: +; GFX8-GISEL-NEXT: s_max_i32 s1, s1, 0xffff8000 +; GFX8-GISEL-NEXT: s_min_i32 s1, s1, 0x7fff +; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, s0, v0 +; GFX8-GISEL-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: s_test_ldexp_f16_i32: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_max_i32 s1, s1, 0xffff8000 +; GFX9-GISEL-NEXT: s_min_i32 s1, s1, 0x7fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, s0, v0 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX11-GISEL-TRUE16-LABEL: s_test_ldexp_f16_i32: +; GFX11-GISEL-TRUE16: ; %bb.0: +; GFX11-GISEL-TRUE16-NEXT: s_max_i32 s1, s1, 0xffff8000 +; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-TRUE16-NEXT: s_min_i32 s1, s1, 0x7fff +; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, s0, s1 +; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog +; +; GFX11-GISEL-FAKE16-LABEL: s_test_ldexp_f16_i32: +; GFX11-GISEL-FAKE16: ; %bb.0: +; GFX11-GISEL-FAKE16-NEXT: s_max_i32 s1, s1, 0xffff8000 +; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-FAKE16-NEXT: s_min_i32 s1, s1, 0x7fff +; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, s0, s1 +; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog + %result = call half @llvm.experimental.constrained.ldexp.f16.i32(half %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret half %result +} + declare half @llvm.experimental.constrained.ldexp.f16.i16(half, i16, metadata, metadata) #1 declare half @llvm.experimental.constrained.ldexp.f16.i32(half, i32, metadata, metadata) #1 declare <2 x half> @llvm.experimental.constrained.ldexp.v2f16.v2i16(<2 x half>, <2 x i16>, metadata, metadata) #1 diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll index 456f0bd2434f..7bf8e8954bd1 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll @@ -4,10 +4,10 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s ; define float @test_ldexp_f32_i16(ptr addrspace(1) %out, float %a, i16 %b) #0 { ; %result = call float @llvm.experimental.constrained.ldexp.f32.i16(float %a, i16 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") @@ -236,6 +236,33 @@ define <4 x float> @test_ldexp_v4f32_v4i32(ptr addrspace(1) %out, <4 x float> %a ret <4 x float> %result } +define amdgpu_ps float @s_test_ldexp_f32_i32(float inreg %a, i32 inreg %b) #0 { +; GFX6-LABEL: s_test_ldexp_f32_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: v_mov_b32_e32 v0, s1 +; GFX6-NEXT: v_ldexp_f32_e32 v0, s0, v0 +; GFX6-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: s_test_ldexp_f32_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX9-LABEL: s_test_ldexp_f32_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_test_ldexp_f32_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_ldexp_f32 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog + %result = call float @llvm.experimental.constrained.ldexp.f32.i32(float %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret float %result +} + declare float @llvm.experimental.constrained.ldexp.f32.i16(float, i16, metadata, metadata) #1 declare float @llvm.experimental.constrained.ldexp.f32.i32(float, i32, metadata, metadata) #1 declare <2 x float> @llvm.experimental.constrained.ldexp.v2f32.v2i16(<2 x float>, <2 x i16>, metadata, metadata) #1 diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll index b31625f8f707..e72083e4b356 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll @@ -4,10 +4,10 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s ; define double @test_ldexp_f64_i16(ptr addrspace(1) %out, double %a, i16 %b) #0 { ; %result = call double @llvm.experimental.constrained.ldexp.f64.i16(double %a, i16 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") @@ -65,6 +65,42 @@ define <4 x double> @test_ldexp_v4f64_v4i32(ptr addrspace(1) %out, <4 x double> ret <4 x double> %result } +define amdgpu_ps double @s_test_ldexp_f64_i32(double inreg %a, i32 inreg %b) #0 { +; GFX6-LABEL: s_test_ldexp_f64_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: v_mov_b32_e32 v0, s2 +; GFX6-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0 +; GFX6-NEXT: v_readfirstlane_b32 s0, v0 +; GFX6-NEXT: v_readfirstlane_b32 s1, v1 +; GFX6-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: s_test_ldexp_f64_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX9-LABEL: s_test_ldexp_f64_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_test_ldexp_f64_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_ldexp_f64 v[0:1], s[0:1], s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; GFX11-NEXT: v_readfirstlane_b32 s1, v1 +; GFX11-NEXT: ; return to shader part epilog + %result = call double @llvm.experimental.constrained.ldexp.f64.i32(double %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret double %result +} + declare double @llvm.experimental.constrained.ldexp.f64.i16(double, i16, metadata, metadata) #1 declare double @llvm.experimental.constrained.ldexp.f64.i32(double, i32, metadata, metadata) #1 declare <2 x double> @llvm.experimental.constrained.ldexp.v2f64.v2i16(<2 x double>, <2 x i16>, metadata, metadata) #1 @@ -75,15 +111,11 @@ declare <4 x double> @llvm.experimental.constrained.ldexp.v4f64.v4i32(<4 x doubl attributes #0 = { strictfp } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX11: {{.*}} ; GFX11-GISEL: {{.*}} ; GFX11-SDAG: {{.*}} -; GFX6: {{.*}} ; GFX6-GISEL: {{.*}} ; GFX6-SDAG: {{.*}} -; GFX8: {{.*}} ; GFX8-GISEL: {{.*}} ; GFX8-SDAG: {{.*}} -; GFX9: {{.*}} ; GFX9-GISEL: {{.*}} ; GFX9-SDAG: {{.*}}