[TableGen] Combine the two separate OperandMapping loops in PseudoLoweringEmitter. (#136007)
Previously we had one loop over the DAG for immediates and registers and
another loop over the destination operands for mapping from the source.
Now we have a single loop over the destination operands that handles immediates,
registers, and named operands. A helper method is added so we can handle
operands and sub-operands specified by a sub-dag.
My goal is to allow a named operand to appear in a sub-dag which wasn't
supported before. This will allow the destination instruction to have an
operand with sub-operands when the source does not have sub operands.
For RISC-V, I'm looking into using an operand with sub-operands to
represent an reg+offset memory address. I need to be able to lower a
pseudo instruction that only has a register operand to an instruction
that has a reg+offset operand. The offset will be filled in with 0
during expansion and the register will be copied from the source.
The expansion would look like this:
def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
[(riscv_call GPRJALR:$rs1)]>,
PseudoInstExpansion<(JALR X1, (ops GPR:$rs1, 0))>;
This commit is contained in:
Craig Topper
GitHub
parent
d35bf17e8a
commit
b9f1de04f6
@ -51,10 +51,11 @@ class PseudoLoweringEmitter {
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SmallVector<PseudoExpansion, 64> Expansions;
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unsigned addDagOperandMapping(const Record *Rec, const DagInit *Dag,
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const CodeGenInstruction &Insn,
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IndexedMap<OpData> &OperandMap,
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unsigned BaseIdx);
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void addOperandMapping(unsigned MIOpNo, unsigned NumOps, const Record *Rec,
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const DagInit *Dag, unsigned DagIdx,
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const Record *OpRec, IndexedMap<OpData> &OperandMap,
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const StringMap<unsigned> &SourceOperands,
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const CodeGenInstruction &SourceInsn);
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void evaluateExpansion(const Record *Pseudo);
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void emitLoweringEmitter(raw_ostream &o);
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@ -66,64 +67,67 @@ public:
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};
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} // End anonymous namespace
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// FIXME: This pass currently can only expand a pseudo to a single instruction.
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// The pseudo expansion really should take a list of dags, not just
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// a single dag, so we can do fancier things.
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unsigned PseudoLoweringEmitter::addDagOperandMapping(
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const Record *Rec, const DagInit *Dag, const CodeGenInstruction &Insn,
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IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
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unsigned OpsAdded = 0;
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for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
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if (const DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
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// Physical register reference. Explicit check for the special case
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// "zero_reg" definition.
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if (DI->getDef()->isSubClassOf("Register") ||
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DI->getDef()->getName() == "zero_reg") {
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auto &Entry = OperandMap[BaseIdx + i];
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Entry.Kind = OpData::Reg;
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Entry.Data.Reg = DI->getDef();
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++OpsAdded;
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continue;
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}
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void PseudoLoweringEmitter::addOperandMapping(
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unsigned MIOpNo, unsigned NumOps, const Record *Rec, const DagInit *Dag,
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unsigned DagIdx, const Record *OpRec, IndexedMap<OpData> &OperandMap,
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const StringMap<unsigned> &SourceOperands,
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const CodeGenInstruction &SourceInsn) {
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const Init *DagArg = Dag->getArg(DagIdx);
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if (const DefInit *DI = dyn_cast<DefInit>(DagArg)) {
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// Physical register reference. Explicit check for the special case
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// "zero_reg" definition.
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if (DI->getDef()->isSubClassOf("Register") ||
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DI->getDef()->getName() == "zero_reg") {
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auto &Entry = OperandMap[MIOpNo];
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Entry.Kind = OpData::Reg;
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Entry.Data.Reg = DI->getDef();
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return;
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}
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// Normal operands should always have the same type, or we have a
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// problem.
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// FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
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assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
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if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', operand type '" + DI->getDef()->getName() +
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"' does not match expansion operand type '" +
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Insn.Operands[BaseIdx + i].Rec->getName() +
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"'");
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// Source operand maps to destination operand. The Data element
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// will be filled in later, just set the Kind for now. Do it
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// for each corresponding MachineInstr operand, not just the first.
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for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
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OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
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OpsAdded += Insn.Operands[i].MINumOperands;
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} else if (const IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
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auto &Entry = OperandMap[BaseIdx + i];
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Entry.Kind = OpData::Imm;
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Entry.Data.Imm = II->getValue();
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++OpsAdded;
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} else if (const auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) {
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auto &Entry = OperandMap[BaseIdx + i];
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Entry.Kind = OpData::Imm;
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Entry.Data.Imm = *BI->convertInitializerToInt();
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++OpsAdded;
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} else if (const DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
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// Just add the operands recursively. This is almost certainly
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// a constant value for a complex operand (> 1 MI operand).
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unsigned NewOps =
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addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
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OpsAdded += NewOps;
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// Since we added more than one, we also need to adjust the base.
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BaseIdx += NewOps - 1;
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} else
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llvm_unreachable("Unhandled pseudo-expansion argument type!");
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}
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return OpsAdded;
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if (DI->getDef() != OpRec)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', operand type '" + DI->getDef()->getName() +
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"' does not match expansion operand type '" +
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OpRec->getName() + "'");
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StringMap<unsigned>::const_iterator SourceOp =
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SourceOperands.find(Dag->getArgNameStr(DagIdx));
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if (SourceOp == SourceOperands.end())
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', output operand '" +
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Dag->getArgNameStr(DagIdx) +
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"' has no matching source operand");
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const auto &SrcOpnd = SourceInsn.Operands[SourceOp->getValue()];
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if (NumOps != SrcOpnd.MINumOperands)
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PrintFatalError(
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Rec,
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"In pseudo instruction '" + Rec->getName() + "', output operand '" +
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OpRec->getName() +
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"' has a different number of sub operands than source operand '" +
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SrcOpnd.Rec->getName() + "'");
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// Source operand maps to destination operand. Do it for each corresponding
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// MachineInstr operand, not just the first.
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for (unsigned I = 0, E = NumOps; I != E; ++I) {
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auto &Entry = OperandMap[MIOpNo + I];
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Entry.Kind = OpData::Operand;
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Entry.Data.Operand = SrcOpnd.MIOperandNo + I;
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}
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LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << DagIdx
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<< "\n");
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} else if (const auto *II = dyn_cast<IntInit>(DagArg)) {
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assert(NumOps == 1);
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auto &Entry = OperandMap[MIOpNo];
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Entry.Kind = OpData::Imm;
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Entry.Data.Imm = II->getValue();
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} else if (const auto *BI = dyn_cast<BitsInit>(DagArg)) {
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assert(NumOps == 1);
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auto &Entry = OperandMap[MIOpNo];
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Entry.Kind = OpData::Imm;
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Entry.Data.Imm = *BI->convertInitializerToInt();
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} else
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llvm_unreachable("Unhandled pseudo-expansion argument type!");
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}
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void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
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@ -157,14 +161,6 @@ void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
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"', result operator '" + Operator->getName() +
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"' has the wrong number of operands");
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unsigned NumMIOperands = 0;
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for (const auto &Op : Insn.Operands)
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NumMIOperands += Op.MINumOperands;
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IndexedMap<OpData> OperandMap;
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OperandMap.grow(NumMIOperands);
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addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
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// If there are more operands that weren't in the DAG, they have to
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// be operands that have default values, or we have an error. Currently,
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// Operands that are a subclass of OperandWithDefaultOp have default values.
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@ -180,37 +176,43 @@ void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
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for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands))
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SourceOperands[SrcOp.Name] = Idx;
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unsigned NumMIOperands = 0;
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for (const auto &Op : Insn.Operands)
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NumMIOperands += Op.MINumOperands;
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IndexedMap<OpData> OperandMap;
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OperandMap.grow(NumMIOperands);
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// FIXME: This pass currently can only expand a pseudo to a single
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// instruction. The pseudo expansion really should take a list of dags, not
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// just a single dag, so we can do fancier things.
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LLVM_DEBUG(dbgs() << " Operand mapping:\n");
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for (const auto &[Idx, Opnd] : enumerate(Insn.Operands)) {
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// We've already handled constant values. Just map instruction operands
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// here.
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if (OperandMap[Opnd.MIOperandNo].Kind != OpData::Operand)
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continue;
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StringMap<unsigned>::iterator SourceOp =
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SourceOperands.find(Dag->getArgNameStr(Idx));
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if (SourceOp == SourceOperands.end())
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', output operand '" + Dag->getArgNameStr(Idx) +
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"' has no matching source operand");
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const auto &SrcOpnd = SourceInsn.Operands[SourceOp->getValue()];
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if (Opnd.MINumOperands != SrcOpnd.MINumOperands)
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PrintFatalError(
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Rec,
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"In pseudo instruction '" + Rec->getName() + "', output operand '" +
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Opnd.Rec->getName() +
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"' has a different number of sub operands than source operand '" +
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SrcOpnd.Rec->getName() + "'");
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for (const auto &[Idx, DstOp] : enumerate(Insn.Operands)) {
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unsigned MIOpNo = DstOp.MIOperandNo;
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// Map the source operand to the destination operand index for each
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// MachineInstr operand.
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for (unsigned I = 0, E = Opnd.MINumOperands; I != E; ++I)
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OperandMap[Opnd.MIOperandNo + I].Data.Operand = SrcOpnd.MIOperandNo + I;
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LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << Idx
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<< "\n");
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if (const auto *SubDag = dyn_cast<DagInit>(Dag->getArg(Idx))) {
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if (!DstOp.MIOperandInfo || DstOp.MIOperandInfo->getNumArgs() == 0)
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PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
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"', operand '" + DstOp.Rec->getName() +
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"' does not have suboperands");
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if (DstOp.MINumOperands != SubDag->getNumArgs()) {
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PrintFatalError(
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Rec, "In pseudo instruction '" + Rec->getName() + "', '" +
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SubDag->getAsString() +
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"' has wrong number of operands for operand type '" +
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DstOp.Rec->getName() + "'");
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}
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for (unsigned I = 0, E = DstOp.MINumOperands; I != E; ++I) {
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auto *OpndRec = cast<DefInit>(DstOp.MIOperandInfo->getArg(I))->getDef();
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addOperandMapping(MIOpNo + I, 1, Rec, SubDag, I, OpndRec, OperandMap,
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SourceOperands, SourceInsn);
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}
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} else {
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addOperandMapping(MIOpNo, DstOp.MINumOperands, Rec, Dag, Idx, DstOp.Rec,
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OperandMap, SourceOperands, SourceInsn);
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}
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}
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Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
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Expansions.emplace_back(SourceInsn, Insn, OperandMap);
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}
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void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
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