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[AVR] Fix codegen after getConstant assertions got enabled (#152269)

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This fixes https://github.com/llvm/llvm-project/issues/152097

This commit fixes two instances of a (somewhat) recently enabled
assertion. One with a test, the other I can't reproduce (might be dead
code) but certainly looks like an instance of the same problem.

The PR that introduced the regression:
https://github.com/llvm/llvm-project/pull/117558

With this patch, the AVR backend is usable again for TinyGo.

(cherry picked from commit aeeb9b507750553f0e85584bda20b8d2373b3bda)
This commit is contained in:
Ayke 2025-08-07 11:40:33 +02:00 committed by Tobias Hieta
parent 7be867f19d
commit ba87d05c55
No known key found for this signature in database
GPG Key ID: 44F2485E45D59042
2 changed files with 20 additions and 2 deletions
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7
llvm/lib/Target/AVR/AVRISelLowering.cpp
View File

@ -669,7 +669,7 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
default: { default: {
// Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
// us to fold the constant into the cmp instruction. // us to fold the constant into the cmp instruction.
RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); RHS = DAG.getSignedConstant(C->getSExtValue() + 1, DL, VT);
CC = ISD::SETGE; CC = ISD::SETGE;
break; break;
} }
@ -713,7 +713,10 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
// Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
// fold the constant into the cmp instruction. // fold the constant into the cmp instruction.
if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); // Doing a "icmp ugt i16 65535, %0" comparison should have been converted
// already to something else. Assert to make sure this assumption holds.
assert((!C->isAllOnes()) && "integer overflow in comparison transform");
RHS = DAG.getConstant(C->getZExtValue() + 1, DL, VT);
CC = ISD::SETUGE; CC = ISD::SETUGE;
break; break;
} }

15
llvm/test/CodeGen/AVR/cmp.ll
View File

@ -298,3 +298,18 @@ define i16 @cmp_i16_gt_1023(i16 %0) {
%3 = zext i1 %2 to i16 %3 = zext i1 %2 to i16
ret i16 %3 ret i16 %3
} }
define void @cmp_issue152097(i16 %a) addrspace(1) {
; See: https://github.com/llvm/llvm-project/issues/152097
; CHECK-LABEL: cmp_issue152097
; CHECK: ldi r18, -1
; CHECK-NEXT: cpi r24, -2
; CHECK-NEXT: cpc r25, r18
; CHECK-NEXT: ret
%cmp = icmp ugt i16 -2, %a
br i1 %cmp, label %if.then, label %if.else
if.then:
ret void
if.else:
ret void
}