diff --git a/llvm/include/llvm/Target/TargetMacroFusion.td b/llvm/include/llvm/Target/TargetMacroFusion.td index 3913a6f92015..1f070853c308 100644 --- a/llvm/include/llvm/Target/TargetMacroFusion.td +++ b/llvm/include/llvm/Target/TargetMacroFusion.td @@ -104,7 +104,7 @@ def OneUse : OneUsePred; // // `IsCommutable` means whether we should handle commutable operands. class Fusion predicates> - : SubtargetFeature { + : SubtargetFeature<"fusion-" # name, fieldName, "true", desc> { list Predicates = predicates; bit IsCommutable = 0; } diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.td b/llvm/lib/Target/RISCV/RISCVMacroFusion.td index d2c1fc11831d..84064785f793 100644 --- a/llvm/lib/Target/RISCV/RISCVMacroFusion.td +++ b/llvm/lib/Target/RISCV/RISCVMacroFusion.td @@ -14,7 +14,7 @@ // lui rd, imm[31:12] // addi(w) rd, rd, imm[11:0] def TuneLUIADDIFusion - : SimpleFusion<"lui-addi-fusion", "HasLUIADDIFusion", + : SimpleFusion<"lui-addi", "HasLUIADDIFusion", "Enable LUI+ADDI macro fusion", CheckOpcode<[LUI]>, CheckOpcode<[ADDI, ADDIW]>>; @@ -23,7 +23,7 @@ def TuneLUIADDIFusion // auipc rd, imm20 // addi rd, rd, imm12 def TuneAUIPCADDIFusion - : SimpleFusion<"auipc-addi-fusion", "HasAUIPCADDIFusion", + : SimpleFusion<"auipc-addi", "HasAUIPCADDIFusion", "Enable AUIPC+ADDI macrofusion", CheckOpcode<[AUIPC]>, CheckOpcode<[ADDI]>>; @@ -32,7 +32,7 @@ def TuneAUIPCADDIFusion // slli rd, rs1, 48 // srli rd, rd, 48 def TuneZExtHFusion - : SimpleFusion<"zexth-fusion", "HasZExtHFusion", + : SimpleFusion<"zexth", "HasZExtHFusion", "Enable SLLI+SRLI to be fused to zero extension of halfword", CheckAll<[ CheckOpcode<[SLLI]>, @@ -49,7 +49,7 @@ def TuneZExtHFusion // slli rd, rs1, 32 // srli rd, rd, 32 def TuneZExtWFusion - : SimpleFusion<"zextw-fusion", "HasZExtWFusion", + : SimpleFusion<"zextw", "HasZExtWFusion", "Enable SLLI+SRLI to be fused to zero extension of word", CheckAll<[ CheckOpcode<[SLLI]>, @@ -67,7 +67,7 @@ def TuneZExtWFusion // srli rd, rd, x // where 0 <= x < 32 def TuneShiftedZExtWFusion - : SimpleFusion<"shifted-zextw-fusion", "HasShiftedZExtWFusion", + : SimpleFusion<"shifted-zextw", "HasShiftedZExtWFusion", "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension", CheckAll<[ CheckOpcode<[SLLI]>, @@ -84,7 +84,7 @@ def TuneShiftedZExtWFusion // add rd, rs1, rs2 // ld rd, 0(rd) def TuneLDADDFusion - : SimpleFusion<"ld-add-fusion", "HasLDADDFusion", "Enable LD+ADD macrofusion", + : SimpleFusion<"ld-add", "HasLDADDFusion", "Enable LD+ADD macrofusion", CheckOpcode<[ADD]>, CheckAll<[ CheckOpcode<[LD]>, @@ -106,7 +106,7 @@ defvar ShiftRight = [SRLI, SRLIW, SRAI, SRAIW]; // add(.uw) rd, rs1, rs2 // load rd, imm12(rd) def TuneADDLoadFusion - : SimpleFusion<"add-load-fusion", "HasADDLoadFusion", "Enable ADD(.UW) + load macrofusion", + : SimpleFusion<"add-load", "HasADDLoadFusion", "Enable ADD(.UW) + load macrofusion", CheckOpcode<[ADD, ADD_UW]>, CheckOpcode>; @@ -114,7 +114,7 @@ def TuneADDLoadFusion // auipc rd, imm20 // load rd, imm12(rd) def TuneAUIPCLoadFusion - : SimpleFusion<"auipc-load-fusion", "HasAUIPCLoadFusion", + : SimpleFusion<"auipc-load", "HasAUIPCLoadFusion", "Enable AUIPC + load macrofusion", CheckOpcode<[AUIPC]>, CheckOpcode>; @@ -123,7 +123,7 @@ def TuneAUIPCLoadFusion // lui rd, imm[31:12] // load rd, imm12(rd) def TuneLUILoadFusion - : SimpleFusion<"lui-load-fusion", "HasLUILoadFusion", + : SimpleFusion<"lui-load", "HasLUILoadFusion", "Enable LUI + load macrofusion", CheckOpcode<[LUI]>, CheckOpcode>; @@ -133,7 +133,7 @@ def TuneLUILoadFusion // slli rd, rs1, imm12 // srli rd, rd, imm12 def TuneBFExtFusion - : SimpleFusion<"bfext-fusion", "HasBFExtFusion", + : SimpleFusion<"bfext", "HasBFExtFusion", "Enable SLLI+SRLI (bitfield extract) macrofusion", CheckOpcode<[SLLI]>, CheckOpcode<[SRLI]>>; @@ -142,7 +142,7 @@ def TuneBFExtFusion // addi rd, rs1, imm12 // load rd, imm12(rd) def TuneADDILoadFusion - : SimpleFusion<"addi-load-fusion", "HasADDILoadFusion", + : SimpleFusion<"addi-load", "HasADDILoadFusion", "Enable ADDI + load macrofusion", CheckOpcode<[ADDI]>, CheckOpcode>; @@ -151,7 +151,7 @@ def TuneADDILoadFusion // shXadd(.uw) rd, rs1, rs2 // load rd, imm12(rd) def TuneSHXADDLoadFusion - : SimpleFusion<"shxadd-load-fusion", "HasSHXADDLoadFusion", + : SimpleFusion<"shxadd-load", "HasSHXADDLoadFusion", "Enable SH(1|2|3)ADD(.UW) + load macrofusion", CheckOpcode<[SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW]>, CheckOpcode>; @@ -161,7 +161,7 @@ def TuneSHXADDLoadFusion // and/or/xor rd, rd, rs3 let IsCommutable = 1 in def TuneFusionLogicRegReg - : SimpleFusion<"fusion-logic-reg-reg", "HasFusionLogicRegReg", + : SimpleFusion<"logic-reg-reg", "HasFusionLogicRegReg", "Enable AND/OR/XOR+AND/OR/XOR macrofusion", CheckOpcode, CheckOpcode>; @@ -170,7 +170,7 @@ def TuneFusionLogicRegReg // and/or/xor rd, rs1, rs2 // andi/ori/xori rd, rd, imm def TuneFusionLogicRegImm - : SimpleFusion<"fusion-logic-reg-imm", "HasFusionLogicRegImm", + : SimpleFusion<"logic-reg-imm", "HasFusionLogicRegImm", "Enable AND/OR/XOR+ANDI/ORI/XORI macrofusion", CheckOpcode, CheckOpcode>; @@ -180,7 +180,7 @@ def TuneFusionLogicRegImm // and/or/xor rd, rd, rs2 let IsCommutable = 1 in def TuneFusionLogicImmReg - : SimpleFusion<"fusion-logic-imm-reg", "HasFusionLogicImmReg", + : SimpleFusion<"logic-imm-reg", "HasFusionLogicImmReg", "Enable ANDI/ORI/XORI+AND/OR/XOR macrofusion", CheckOpcode, CheckOpcode>; @@ -189,7 +189,7 @@ def TuneFusionLogicImmReg // mul(w) rd, rs1, rs2 // add(w) rd, rd, rs3 def TuneFusionMulAdd - : SimpleFusion<"fusion-mul-add", "HasFusionMulAdd", + : SimpleFusion<"mul-add", "HasFusionMulAdd", "Enable MUL+ADD macrofusion", CheckOpcode<[MUL, MULW]>, CheckOpcode<[ADD, ADDW]>, @@ -209,7 +209,7 @@ def TuneFusionMulAdd // add rd, rs1, rs2 // load/store rt, 0(rd) def TuneFusionAddMem - : Fusion<"fusion-add-mem", "HasFusionAddMem", + : Fusion<"add-mem", "HasFusionAddMem", "Enable ADD+LOAD/STORE macrofusion", [ SecondFusionPredicateWithMCInstPredicate< @@ -235,7 +235,7 @@ def TuneFusionAddMem // srli(w)/srai(w) rd, rd, imm2 // where imm1 <= imm2 def TuneFusionShiftBitExtract - : SimpleFusion<"fusion-shift-bit-extract", "HasFusionShiftBitExtract", + : SimpleFusion<"shift-bit-extract", "HasFusionShiftBitExtract", "Enable SLLI+SRLI/SRAI macrofusion", CheckOpcode, CheckOpcode, diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 05c932aa359e..c55283f6512e 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -6,13 +6,8 @@ ; CHECK-NEXT: 32bit - Implements RV32. ; CHECK-NEXT: 64bit - Implements RV64. ; CHECK-NEXT: a - 'A' (Atomic Instructions). -; CHECK-NEXT: add-load-fusion - Enable ADD(.UW) + load macrofusion. -; CHECK-NEXT: addi-load-fusion - Enable ADDI + load macrofusion. ; CHECK-NEXT: andes45 - Andes 45-Series processors. -; CHECK-NEXT: auipc-addi-fusion - Enable AUIPC+ADDI macrofusion. -; CHECK-NEXT: auipc-load-fusion - Enable AUIPC + load macrofusion. ; CHECK-NEXT: b - 'B' (the collection of the Zba, Zbb, Zbs extensions). -; CHECK-NEXT: bfext-fusion - Enable SLLI+SRLI (bitfield extract) macrofusion. ; CHECK-NEXT: c - 'C' (Compressed Instructions). ; CHECK-NEXT: conditional-cmv-fusion - Enable branch+c.mv fusion. ; CHECK-NEXT: d - 'D' (Double-Precision Floating-Point). @@ -47,18 +42,27 @@ ; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography). ; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point). ; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available. +; CHECK-NEXT: fusion-add-load - Enable ADD(.UW) + load macrofusion. ; CHECK-NEXT: fusion-add-mem - Enable ADD+LOAD/STORE macrofusion. +; CHECK-NEXT: fusion-addi-load - Enable ADDI + load macrofusion. +; CHECK-NEXT: fusion-auipc-addi - Enable AUIPC+ADDI macrofusion. +; CHECK-NEXT: fusion-auipc-load - Enable AUIPC + load macrofusion. +; CHECK-NEXT: fusion-bfext - Enable SLLI+SRLI (bitfield extract) macrofusion. +; CHECK-NEXT: fusion-ld-add - Enable LD+ADD macrofusion. ; CHECK-NEXT: fusion-logic-imm-reg - Enable ANDI/ORI/XORI+AND/OR/XOR macrofusion. ; CHECK-NEXT: fusion-logic-reg-imm - Enable AND/OR/XOR+ANDI/ORI/XORI macrofusion. ; CHECK-NEXT: fusion-logic-reg-reg - Enable AND/OR/XOR+AND/OR/XOR macrofusion. +; CHECK-NEXT: fusion-lui-addi - Enable LUI+ADDI macro fusion. +; CHECK-NEXT: fusion-lui-load - Enable LUI + load macrofusion. ; CHECK-NEXT: fusion-mul-add - Enable MUL+ADD macrofusion. ; CHECK-NEXT: fusion-shift-bit-extract - Enable SLLI+SRLI/SRAI macrofusion. +; CHECK-NEXT: fusion-shifted-zextw - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. +; CHECK-NEXT: fusion-shxadd-load - Enable SH(1|2|3)ADD(.UW) + load macrofusion. +; CHECK-NEXT: fusion-zexth - Enable SLLI+SRLI to be fused to zero extension of halfword. +; CHECK-NEXT: fusion-zextw - Enable SLLI+SRLI to be fused to zero extension of word. ; CHECK-NEXT: h - 'H' (Hypervisor). ; CHECK-NEXT: i - 'I' (Base Integer Instruction Set). -; CHECK-NEXT: ld-add-fusion - Enable LD+ADD macrofusion. ; CHECK-NEXT: log-vrgather - Has vrgather.vv with LMUL*log2(LMUL) latency -; CHECK-NEXT: lui-addi-fusion - Enable LUI+ADDI macro fusion. -; CHECK-NEXT: lui-load-fusion - Enable LUI + load macrofusion. ; CHECK-NEXT: m - 'M' (Integer Multiplication and Division). ; CHECK-NEXT: mips-p8700 - MIPS p8700 processor. ; CHECK-NEXT: no-default-unroll - Disable default unroll preference.. @@ -125,7 +129,6 @@ ; CHECK-NEXT: sha - 'Sha' (Augmented Hypervisor). ; CHECK-NEXT: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero). ; CHECK-NEXT: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). -; CHECK-NEXT: shifted-zextw-fusion - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. ; CHECK-NEXT: shlcofideleg - 'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode). ; CHECK-NEXT: short-forward-branch-ialu - Enable short forward branch optimization for RVI base instructions. ; CHECK-NEXT: short-forward-branch-iload - Enable short forward branch optimization for load instructions. @@ -135,7 +138,6 @@ ; CHECK-NEXT: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp). ; CHECK-NEXT: shvstvala - 'Shvstvala' (vstval provides all needed values). ; CHECK-NEXT: shvstvecd - 'Shvstvecd' (vstvec supports Direct mode). -; CHECK-NEXT: shxadd-load-fusion - Enable SH(1|2|3)ADD(.UW) + load macrofusion. ; CHECK-NEXT: sifive7 - SiFive 7-Series processors. ; CHECK-NEXT: single-element-vec-fp64 - Certain vector FP64 operations produce a single result element per cycle. ; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level). @@ -200,7 +202,7 @@ ; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU). ; CHECK-NEXT: xmipscbop - 'XMIPSCBOP' (MIPS Software Prefetch). ; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)). -; CHECK-NEXT: mipsexectl - 'XMIPSEXECTL' (MIPS execution control). +; CHECK-NEXT: xmipsexectl - 'XMIPSEXECTL' (MIPS execution control). ; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding). ; CHECK-NEXT: xqccmp - 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves). ; CHECK-NEXT: xqci - 'Xqci' (Qualcomm uC Extension). @@ -286,8 +288,6 @@ ; CHECK-NEXT: zcmp - 'Zcmp' (sequenced instructions for code-size reduction). ; CHECK-NEXT: zcmt - 'Zcmt' (table jump instructions for code-size reduction). ; CHECK-NEXT: zdinx - 'Zdinx' (Double in Integer). -; CHECK-NEXT: zexth-fusion - Enable SLLI+SRLI to be fused to zero extension of halfword. -; CHECK-NEXT: zextw-fusion - Enable SLLI+SRLI to be fused to zero extension of word. ; CHECK-NEXT: zfa - 'Zfa' (Additional Floating-Point). ; CHECK-NEXT: zfbfmin - 'Zfbfmin' (Scalar BF16 Converts). ; CHECK-NEXT: zfh - 'Zfh' (Half-Precision Floating-Point). diff --git a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll index 2a1ba2f77ede..664041cca768 100644 --- a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll +++ b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll @@ -4,9 +4,9 @@ ; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64I,RV64NOFUSION %s ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \ -; RUN: -mattr=+auipc-addi-fusion | FileCheck -check-prefixes=RV32I,RV32FUSION %s +; RUN: -mattr=+fusion-auipc-addi | FileCheck -check-prefixes=RV32I,RV32FUSION %s ; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \ -; RUN: -mattr=+auipc-addi-fusion | FileCheck -check-prefixes=RV64I,RV64FUSION %s +; RUN: -mattr=+fusion-auipc-addi | FileCheck -check-prefixes=RV64I,RV64FUSION %s ; Verifies that MachineLICM can hoist address generation pseudos out of loops. diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll index ed99e6030ebd..e10bb0e6588c 100644 --- a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll +++ b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll @@ -1,18 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ;RUN: llc < %s -mtriple=riscv64 -mattr=+f -mcpu=sifive-u74 -target-abi=lp64f \ ;RUN: | FileCheck %s --check-prefix=NOFUSION -;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion -mcpu=sifive-u74 \ +;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+fusion-lui-addi -mcpu=sifive-u74 \ ;RUN: -target-abi=lp64f | FileCheck %s --check-prefix=FUSION -;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion,+use-postra-scheduler -mcpu=sifive-u74 \ +;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+fusion-lui-addi,+use-postra-scheduler -mcpu=sifive-u74 \ ;RUN: -misched-postra-direction=topdown -target-abi=lp64f \ ;RUN: | FileCheck %s --check-prefixes=FUSION-POSTRA,FUSION-POSTRA-TOPDOWN -;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion,+use-postra-scheduler -mcpu=sifive-u74 \ +;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+fusion-lui-addi,+use-postra-scheduler -mcpu=sifive-u74 \ ;RUN: -misched-postra-direction=bottomup -target-abi=lp64f \ ;RUN: | FileCheck %s --check-prefixes=FUSION-POSTRA,FUSION-POSTRA-BOTTOMUP -;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion,+use-postra-scheduler -mcpu=sifive-u74 \ +;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+fusion-lui-addi,+use-postra-scheduler -mcpu=sifive-u74 \ ;RUN: -misched-postra-direction=bidirectional -target-abi=lp64f \ ;RUN: | FileCheck %s --check-prefixes=FUSION-POSTRA,FUSION-POSTRA-BIDIRECTIONAL -;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion -target-abi=lp64f \ +;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+fusion-lui-addi -target-abi=lp64f \ ;RUN: | FileCheck %s --check-prefix=FUSION-GENERIC @.str = private constant [4 x i8] c"%f\0A\00", align 1 diff --git a/llvm/test/CodeGen/RISCV/macro-fusions.mir b/llvm/test/CodeGen/RISCV/macro-fusions.mir index ae5b52da2ac1..77fc03c4237f 100644 --- a/llvm/test/CodeGen/RISCV/macro-fusions.mir +++ b/llvm/test/CodeGen/RISCV/macro-fusions.mir @@ -1,13 +1,13 @@ # REQUIRES: asserts # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ # RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ -# RUN: -mattr=+lui-addi-fusion,+auipc-addi-fusion,+zexth-fusion,+zextw-fusion,+shifted-zextw-fusion,+ld-add-fusion \ -# RUN: -mattr=+add-load-fusion,+auipc-load-fusion,+lui-load-fusion,+addi-load-fusion \ -# RUN: -mattr=+zba,+shxadd-load-fusion \ +# RUN: -mattr=+fusion-lui-addi,+fusion-auipc-addi,+fusion-zexth,+fusion-zextw,+fusion-shifted-zextw,+fusion-ld-add \ +# RUN: -mattr=+fusion-add-load,+fusion-auipc-load,+fusion-lui-load,+fusion-addi-load \ +# RUN: -mattr=+zba,+fusion-shxadd-load \ # RUN: | FileCheck %s # RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ # RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ -# RUN: -mattr=+zba,+bfext-fusion | FileCheck --check-prefixes=CHECK-BFEXT %s +# RUN: -mattr=+zba,+fusion-bfext | FileCheck --check-prefixes=CHECK-BFEXT %s # CHECK: lui_addi:%bb.0 # CHECK: Macro fuse: {{.*}}LUI - ADDI diff --git a/llvm/test/TableGen/MacroFusion.td b/llvm/test/TableGen/MacroFusion.td index ca795efd141e..fd6e902c24da 100644 --- a/llvm/test/TableGen/MacroFusion.td +++ b/llvm/test/TableGen/MacroFusion.td @@ -41,7 +41,7 @@ def TestBothFusionPredicate: Fusion<"test-both-fusion-predicate", "HasBothFusion "Test BothFusionPredicate", [BothFusionPredicate]>; -def TestFusion: SimpleFusion<"test-fusion", "HasTestFusion", "Test Fusion", +def TestFusion: SimpleFusion<"test", "HasTestFusion", "Test Fusion", CheckOpcode<[Inst0, Inst1]>, CheckAll<[ CheckOpcode<[Inst1]>, @@ -49,7 +49,7 @@ def TestFusion: SimpleFusion<"test-fusion", "HasTestFusion", "Test Fusion", ]>>; let IsCommutable = 1 in -def TestCommutableFusion: SimpleFusion<"test-commutable-fusion", "HasTestCommutableFusion", +def TestCommutableFusion: SimpleFusion<"test-commutable", "HasTestCommutableFusion", "Test Commutable Fusion", CheckOpcode<[Inst0]>, CheckAll<[ @@ -57,12 +57,12 @@ def TestCommutableFusion: SimpleFusion<"test-commutable-fusion", "HasTestCommuta CheckRegOperand<0, X0> ]>>; -def TestSingleFusion: SingleFusion<"test-single-fusion", "HasTestSingleFusion", +def TestSingleFusion: SingleFusion<"test-single", "HasTestSingleFusion", "Test SingleFusion", Inst0, Inst2, secondInstPred=CheckRegOperand<0, X0>>; -def TestFirstSameRegFusion: Fusion<"test-first-same-reg-fusion", "HasTestFirstSameRegFusion", +def TestFirstSameRegFusion: Fusion<"test-first-same-reg", "HasTestFirstSameRegFusion", "Test FirstSameReg", [FirstInstHasSameReg<0, 1>]> { bit IsCommutable = 1; @@ -265,11 +265,11 @@ def TestFirstSameRegFusion: Fusion<"test-first-same-reg-fusion", "HasTestFirstSa // CHECK-PREDICATOR-NEXT: #endif // GET_Test_MACRO_FUSION_PRED_IMPL // Check that we have generated target subfeature. -// CHECK-SUBTARGET: { "test-both-fusion-predicate", "Test BothFusionPredicate", Test::TestBothFusionPredicate -// CHECK-SUBTARGET: { "test-commutable-fusion", "Test Commutable Fusion", Test::TestCommutableFusion -// CHECK-SUBTARGET: { "test-first-same-reg-fusion", "Test FirstSameReg", Test::TestFirstSameRegFusion -// CHECK-SUBTARGET: { "test-fusion", "Test Fusion", Test::TestFusion -// CHECK-SUBTARGET: { "test-single-fusion", "Test SingleFusion", Test::TestSingleFusion +// CHECK-SUBTARGET: { "fusion-test", "Test Fusion", Test::TestFusion, +// CHECK-SUBTARGET: { "fusion-test-both-fusion-predicate", "Test BothFusionPredicate", Test::TestBothFusionPredicate, +// CHECK-SUBTARGET: { "fusion-test-commutable", "Test Commutable Fusion", Test::TestCommutableFusion, +// CHECK-SUBTARGET: { "fusion-test-first-same-reg", "Test FirstSameReg", Test::TestFirstSameRegFusion, +// CHECK-SUBTARGET: { "fusion-test-single", "Test SingleFusion", Test::TestSingleFusion, // Check that we have generated `getMacroFusions()` function. // CHECK-SUBTARGET: std::vector getMacroFusions() const final;