diff --git a/llvm/test/CodeGen/PowerPC/vec_revb.ll b/llvm/test/CodeGen/PowerPC/vec_revb.ll
index 00c08a1204fe..fc19c849a58c 100644
--- a/llvm/test/CodeGen/PowerPC/vec_revb.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_revb.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
 
@@ -52,3 +53,20 @@ entry:
   %2 = bitcast <16 x i8> %1 to <1 x i128>
   ret <1 x i128> %2
 }
+
+define <4 x i32> @testXXBRD_With_LogicalOp(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: testXXBRD_With_LogicalOp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxbrw 0, 34
+; CHECK-NEXT:    xxbrw 1, 35
+; CHECK-NEXT:    xxland 34, 0, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  %3 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %b)
+  %4 = and <4 x i32> %2, %3
+  ret <4 x i32> %4
+}
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)