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[BOLT] Refactor instruction creation interface. NFCI (#85292)

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Refactor MCPlusBuilder's create{Instruction}() functions that used to
return bool. We almost never check the return value as we rely on
llvm_unreachable() to detect unimplemented functionality. There were a
couple of cases that checked the return value, but they would hit the
unreachable condition first (at least in debug builds) before the return
value gets checked.
This commit is contained in:
Maksim Panchenko 2024-03-14 13:17:17 -07:00 committed by GitHub
parent ea429e19f5
commit bba790db47
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
7 changed files with 70 additions and 133 deletions
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52
bolt/include/bolt/Core/MCPlusBuilder.h
View File

@ -487,10 +487,9 @@ public:
llvm_unreachable("not implemented");
}
virtual bool createDirectCall(MCInst &Inst, const MCSymbol *Target,
virtual void createDirectCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx, bool IsTailCall) {
llvm_unreachable("not implemented");
return false;
}
virtual MCPhysReg getX86R11() const { llvm_unreachable("not implemented"); }
@ -1534,15 +1533,13 @@ public:
}
/// Create a no-op instruction.
virtual bool createNoop(MCInst &Inst) const {
virtual void createNoop(MCInst &Inst) const {
llvm_unreachable("not implemented");
return false;
}
/// Create a return instruction.
virtual bool createReturn(MCInst &Inst) const {
virtual void createReturn(MCInst &Inst) const {
llvm_unreachable("not implemented");
return false;
}
/// Store \p Target absolute address to \p RegName
@ -1556,32 +1553,23 @@ public:
/// Creates a new unconditional branch instruction in Inst and set its operand
/// to TBB.
///
/// Returns true on success.
virtual bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
virtual void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
return false;
}
/// Creates a new call instruction in Inst and sets its operand to
/// Target.
///
/// Returns true on success.
virtual bool createCall(MCInst &Inst, const MCSymbol *Target,
virtual void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) {
llvm_unreachable("not implemented");
return false;
}
/// Creates a new tail call instruction in Inst and sets its operand to
/// Target.
///
/// Returns true on success.
virtual bool createTailCall(MCInst &Inst, const MCSymbol *Target,
virtual void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) {
llvm_unreachable("not implemented");
return false;
}
virtual void createLongTailCall(InstructionListType &Seq,
@ -1590,43 +1578,36 @@ public:
}
/// Creates a trap instruction in Inst.
///
/// Returns true on success.
virtual bool createTrap(MCInst &Inst) const {
virtual void createTrap(MCInst &Inst) const {
llvm_unreachable("not implemented");
return false;
}
/// Creates an instruction to bump the stack pointer just like a call.
virtual bool createStackPointerIncrement(MCInst &Inst, int Size = 8,
virtual void createStackPointerIncrement(MCInst &Inst, int Size = 8,
bool NoFlagsClobber = false) const {
llvm_unreachable("not implemented");
return false;
}
/// Creates an instruction to move the stack pointer just like a ret.
virtual bool createStackPointerDecrement(MCInst &Inst, int Size = 8,
virtual void createStackPointerDecrement(MCInst &Inst, int Size = 8,
bool NoFlagsClobber = false) const {
llvm_unreachable("not implemented");
return false;
}
/// Create a store instruction using \p StackReg as the base register
/// and \p Offset as the displacement.
virtual bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg,
virtual void createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg,
int Offset, const MCPhysReg &SrcReg,
int Size) const {
llvm_unreachable("not implemented");
return false;
}
virtual bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
virtual void createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
const MCPhysReg &IndexReg, int64_t Offset,
const MCExpr *OffsetExpr,
const MCPhysReg &AddrSegmentReg,
const MCPhysReg &DstReg, int Size) const {
llvm_unreachable("not implemented");
return false;
}
virtual InstructionListType createLoadImmediate(const MCPhysReg Dest,
@ -1636,32 +1617,27 @@ public:
/// Create a fragment of code (sequence of instructions) that load a 32-bit
/// address from memory, zero-extends it to 64 and jump to it (indirect jump).
virtual bool
virtual void
createIJmp32Frag(SmallVectorImpl<MCInst> &Insts, const MCOperand &BaseReg,
const MCOperand &Scale, const MCOperand &IndexReg,
const MCOperand &Offset, const MCOperand &TmpReg) const {
llvm_unreachable("not implemented");
return false;
}
/// Create a load instruction using \p StackReg as the base register
/// and \p Offset as the displacement.
virtual bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
virtual void createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
int Offset, const MCPhysReg &DstReg,
int Size) const {
llvm_unreachable("not implemented");
return false;
}
/// Creates a call frame pseudo instruction. A single operand identifies which
/// MCCFIInstruction this MCInst is referring to.
///
/// Returns true on success.
virtual bool createCFI(MCInst &Inst, int64_t Offset) const {
virtual void createCFI(MCInst &Inst, int64_t Offset) const {
Inst.clear();
Inst.setOpcode(TargetOpcode::CFI_INSTRUCTION);
Inst.addOperand(MCOperand::createImm(Offset));
return true;
}
/// Create an inline version of memcpy(dest, src, 1).

7
bolt/lib/Passes/BinaryPasses.cpp
View File

@ -1056,10 +1056,9 @@ void Peepholes::addTailcallTraps(BinaryFunction &Function) {
MCInst *Inst = BB.getLastNonPseudoInstr();
if (Inst && MIB->isTailCall(*Inst) && MIB->isIndirectBranch(*Inst)) {
MCInst Trap;
if (MIB->createTrap(Trap)) {
BB.addInstruction(Trap);
++TailCallTraps;
}
MIB->createTrap(Trap);
BB.addInstruction(Trap);
++TailCallTraps;
}
}
}

44
bolt/lib/Passes/ShrinkWrapping.cpp
View File

@ -680,16 +680,15 @@ void StackLayoutModifier::performChanges() {
if (StackPtrReg != BC.MIB->getFramePointer())
Adjustment = -Adjustment;
if (IsLoad)
Success = BC.MIB->createRestoreFromStack(
Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size);
BC.MIB->createRestoreFromStack(Inst, StackPtrReg,
StackOffset + Adjustment, Reg, Size);
else if (IsStore)
Success = BC.MIB->createSaveToStack(
Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size);
BC.MIB->createSaveToStack(Inst, StackPtrReg, StackOffset + Adjustment,
Reg, Size);
LLVM_DEBUG({
dbgs() << "Adjusted instruction: ";
Inst.dump();
});
assert(Success);
}
}
}
@ -1653,19 +1652,13 @@ Expected<MCInst> ShrinkWrapping::createStackAccess(int SPVal, int FPVal,
if (SPVal != StackPointerTracking::SUPERPOSITION &&
SPVal != StackPointerTracking::EMPTY) {
if (FIE.IsLoad) {
if (!BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getStackPointer(),
FIE.StackOffset - SPVal, FIE.RegOrImm,
FIE.Size)) {
return createFatalBOLTError(
"createRestoreFromStack: not supported on this platform\n");
}
} else {
if (!BC.MIB->createSaveToStack(NewInst, BC.MIB->getStackPointer(),
BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getStackPointer(),
FIE.StackOffset - SPVal, FIE.RegOrImm,
FIE.Size)) {
return createFatalBOLTError(
"createSaveToStack: not supported on this platform\n");
}
FIE.Size);
} else {
BC.MIB->createSaveToStack(NewInst, BC.MIB->getStackPointer(),
FIE.StackOffset - SPVal, FIE.RegOrImm,
FIE.Size);
}
if (CreatePushOrPop)
BC.MIB->changeToPushOrPop(NewInst);
@ -1675,19 +1668,12 @@ Expected<MCInst> ShrinkWrapping::createStackAccess(int SPVal, int FPVal,
FPVal != StackPointerTracking::EMPTY);
if (FIE.IsLoad) {
if (!BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getFramePointer(),
FIE.StackOffset - FPVal, FIE.RegOrImm,
FIE.Size)) {
return createFatalBOLTError(
"createRestoreFromStack: not supported on this platform\n");
}
} else {
if (!BC.MIB->createSaveToStack(NewInst, BC.MIB->getFramePointer(),
BC.MIB->createRestoreFromStack(NewInst, BC.MIB->getFramePointer(),
FIE.StackOffset - FPVal, FIE.RegOrImm,
FIE.Size)) {
return createFatalBOLTError(
"createSaveToStack: not supported on this platform\n");
}
FIE.Size);
} else {
BC.MIB->createSaveToStack(NewInst, BC.MIB->getFramePointer(),
FIE.StackOffset - FPVal, FIE.RegOrImm, FIE.Size);
}
return NewInst;
}

23
bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
View File

@ -1026,7 +1026,7 @@ public:
return Code;
}
bool createTailCall(MCInst &Inst, const MCSymbol *Target,
void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true);
}
@ -1036,11 +1036,10 @@ public:
createShortJmp(Seq, Target, Ctx, /*IsTailCall*/ true);
}
bool createTrap(MCInst &Inst) const override {
void createTrap(MCInst &Inst) const override {
Inst.clear();
Inst.setOpcode(AArch64::BRK);
Inst.addOperand(MCOperand::createImm(1));
return true;
}
bool convertJmpToTailCall(MCInst &Inst) override {
@ -1068,16 +1067,15 @@ public:
Inst.getOperand(0).getImm() == 0;
}
bool createNoop(MCInst &Inst) const override {
void createNoop(MCInst &Inst) const override {
Inst.setOpcode(AArch64::HINT);
Inst.clear();
Inst.addOperand(MCOperand::createImm(0));
return true;
}
bool mayStore(const MCInst &Inst) const override { return false; }
bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
bool IsTailCall) override {
Inst.setOpcode(IsTailCall ? AArch64::B : AArch64::BL);
Inst.clear();
@ -1086,7 +1084,6 @@ public:
*Ctx, 0)));
if (IsTailCall)
convertJmpToTailCall(Inst);
return true;
}
bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
@ -1293,14 +1290,13 @@ public:
return true;
}
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
Inst.setOpcode(AArch64::B);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx),
*Ctx, 0)));
return true;
}
bool shouldRecordCodeRelocation(uint64_t RelType) const override {
@ -1353,14 +1349,13 @@ public:
return StringRef("\0\0\0\0", 4);
}
bool createReturn(MCInst &Inst) const override {
void createReturn(MCInst &Inst) const override {
Inst.setOpcode(AArch64::RET);
Inst.clear();
Inst.addOperand(MCOperand::createReg(AArch64::LR));
return true;
}
bool createStackPointerIncrement(
void createStackPointerIncrement(
MCInst &Inst, int Size,
bool NoFlagsClobber = false /*unused for AArch64*/) const override {
Inst.setOpcode(AArch64::SUBXri);
@ -1369,10 +1364,9 @@ public:
Inst.addOperand(MCOperand::createReg(AArch64::SP));
Inst.addOperand(MCOperand::createImm(Size));
Inst.addOperand(MCOperand::createImm(0));
return true;
}
bool createStackPointerDecrement(
void createStackPointerDecrement(
MCInst &Inst, int Size,
bool NoFlagsClobber = false /*unused for AArch64*/) const override {
Inst.setOpcode(AArch64::ADDXri);
@ -1381,7 +1375,6 @@ public:
Inst.addOperand(MCOperand::createReg(AArch64::SP));
Inst.addOperand(MCOperand::createImm(Size));
Inst.addOperand(MCOperand::createImm(0));
return true;
}
void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg,

13
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
View File

@ -219,46 +219,43 @@ public:
return true;
}
bool createReturn(MCInst &Inst) const override {
void createReturn(MCInst &Inst) const override {
// TODO "c.jr ra" when RVC is enabled
Inst.setOpcode(RISCV::JALR);
Inst.clear();
Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(MCOperand::createReg(RISCV::X1));
Inst.addOperand(MCOperand::createImm(0));
return true;
}
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
Inst.setOpcode(RISCV::JAL);
Inst.clear();
Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
return true;
}
StringRef getTrapFillValue() const override {
return StringRef("\0\0\0\0", 4);
}
bool createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
void createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) {
Inst.setOpcode(Opcode);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(RISCVMCExpr::create(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx),
RISCVMCExpr::VK_RISCV_CALL, *Ctx)));
return true;
}
bool createCall(MCInst &Inst, const MCSymbol *Target,
void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createCall(RISCV::PseudoCALL, Inst, Target, Ctx);
}
bool createTailCall(MCInst &Inst, const MCSymbol *Target,
void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createCall(RISCV::PseudoTAIL, Inst, Target, Ctx);
}

54
bolt/lib/Target/X86/X86MCPlusBuilder.cpp
View File

@ -2230,7 +2230,7 @@ public:
return true;
}
bool createStackPointerIncrement(MCInst &Inst, int Size,
void createStackPointerIncrement(MCInst &Inst, int Size,
bool NoFlagsClobber) const override {
if (NoFlagsClobber) {
Inst.setOpcode(X86::LEA64r);
@ -2241,17 +2241,16 @@ public:
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.addOperand(MCOperand::createImm(-Size)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
return true;
return;
}
Inst.setOpcode(X86::SUB64ri8);
Inst.clear();
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createImm(Size));
return true;
}
bool createStackPointerDecrement(MCInst &Inst, int Size,
void createStackPointerDecrement(MCInst &Inst, int Size,
bool NoFlagsClobber) const override {
if (NoFlagsClobber) {
Inst.setOpcode(X86::LEA64r);
@ -2262,22 +2261,22 @@ public:
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.addOperand(MCOperand::createImm(Size)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
return true;
return;
}
Inst.setOpcode(X86::ADD64ri8);
Inst.clear();
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createReg(X86::RSP));
Inst.addOperand(MCOperand::createImm(Size));
return true;
}
bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset,
void createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset,
const MCPhysReg &SrcReg, int Size) const override {
unsigned NewOpcode;
switch (Size) {
default:
return false;
llvm_unreachable("Invalid operand size");
return;
case 2: NewOpcode = X86::MOV16mr; break;
case 4: NewOpcode = X86::MOV32mr; break;
case 8: NewOpcode = X86::MOV64mr; break;
@ -2290,10 +2289,9 @@ public:
Inst.addOperand(MCOperand::createImm(Offset)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
Inst.addOperand(MCOperand::createReg(SrcReg));
return true;
}
bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
void createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg,
int Offset, const MCPhysReg &DstReg,
int Size) const override {
return createLoad(Inst, StackReg, /*Scale=*/1, /*IndexReg=*/X86::NoRegister,
@ -2301,14 +2299,15 @@ public:
DstReg, Size);
}
bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
void createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
const MCPhysReg &IndexReg, int64_t Offset,
const MCExpr *OffsetExpr, const MCPhysReg &AddrSegmentReg,
const MCPhysReg &DstReg, int Size) const override {
unsigned NewOpcode;
switch (Size) {
default:
return false;
llvm_unreachable("Invalid operand size");
return;
case 2: NewOpcode = X86::MOV16rm; break;
case 4: NewOpcode = X86::MOV32rm; break;
case 8: NewOpcode = X86::MOV64rm; break;
@ -2324,7 +2323,6 @@ public:
else
Inst.addOperand(MCOperand::createImm(Offset)); // Displacement
Inst.addOperand(MCOperand::createReg(AddrSegmentReg)); // AddrSegmentReg
return true;
}
InstructionListType createLoadImmediate(const MCPhysReg Dest,
@ -2338,7 +2336,7 @@ public:
return Insts;
}
bool createIJmp32Frag(SmallVectorImpl<MCInst> &Insts,
void createIJmp32Frag(SmallVectorImpl<MCInst> &Insts,
const MCOperand &BaseReg, const MCOperand &Scale,
const MCOperand &IndexReg, const MCOperand &Offset,
const MCOperand &TmpReg) const override {
@ -2362,19 +2360,16 @@ public:
Insts.push_back(Load);
Insts.push_back(IJmp);
return true;
}
bool createNoop(MCInst &Inst) const override {
void createNoop(MCInst &Inst) const override {
Inst.setOpcode(X86::NOOP);
Inst.clear();
return true;
}
bool createReturn(MCInst &Inst) const override {
void createReturn(MCInst &Inst) const override {
Inst.setOpcode(X86::RET64);
Inst.clear();
return true;
}
InstructionListType createInlineMemcpy(bool ReturnEnd) const override {
@ -2731,25 +2726,23 @@ public:
return FoundOne;
}
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
Inst.setOpcode(X86::JMP_1);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
return true;
}
bool createCall(MCInst &Inst, const MCSymbol *Target,
void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
Inst.setOpcode(X86::CALL64pcrel32);
Inst.clear();
Inst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx)));
return true;
}
bool createTailCall(MCInst &Inst, const MCSymbol *Target,
void createTailCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override {
return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true);
}
@ -2761,10 +2754,9 @@ public:
createDirectCall(Seq.back(), Target, Ctx, /*IsTailCall*/ true);
}
bool createTrap(MCInst &Inst) const override {
void createTrap(MCInst &Inst) const override {
Inst.clear();
Inst.setOpcode(X86::TRAP);
return true;
}
bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
@ -2866,7 +2858,7 @@ public:
Inst.setOpcode(X86::LFENCE);
}
bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
bool IsTailCall) override {
Inst.clear();
Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32);
@ -2874,7 +2866,6 @@ public:
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx)));
if (IsTailCall)
setTailCall(Inst);
return true;
}
void createShortJmp(InstructionListType &Seq, const MCSymbol *Target,
@ -3546,7 +3537,7 @@ public:
}
private:
bool createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
void createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
MCContext *Ctx) const {
Inst.setOpcode(X86::MOV64rm);
Inst.clear();
@ -3558,11 +3549,9 @@ private:
MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None,
*Ctx))); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
return true;
}
bool createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
void createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg,
MCContext *Ctx) const {
Inst.setOpcode(X86::LEA64r);
Inst.clear();
@ -3574,7 +3563,6 @@ private:
MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None,
*Ctx))); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
return true;
}
};

10
bolt/unittests/Core/MCPlusBuilder.cpp
View File

@ -134,9 +134,8 @@ TEST_P(MCPlusBuilderTester, ReplaceRegWithImm) {
TEST_P(MCPlusBuilderTester, Annotation) {
MCInst Inst;
bool Success = BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
BC->Ctx.get());
ASSERT_TRUE(Success);
BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
BC->Ctx.get());
MCSymbol *LPSymbol = BC->Ctx->createNamedTempSymbol("LP");
uint64_t Value = INT32_MIN;
// Test encodeAnnotationImm using this indirect way
@ -151,9 +150,8 @@ TEST_P(MCPlusBuilderTester, Annotation) {
// Large int64 should trigger an out of range assertion
Value = 0x1FF'FFFF'FFFF'FFFFULL;
Inst.clear();
Success = BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
BC->Ctx.get());
ASSERT_TRUE(Success);
BC->MIB->createTailCall(Inst, BC->Ctx->createNamedTempSymbol(),
BC->Ctx.get());
ASSERT_DEATH(BC->MIB->addEHInfo(Inst, MCPlus::MCLandingPad(LPSymbol, Value)),
"annotation value out of range");
}