shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

Revert "[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types"

Browse Source 
This reverts commit 770be43f6782dab84d215d01b37396d63a9c2b6e.

Forgot to remove from my tree while experimenting.
This commit is contained in:
Craig Topper 2023-08-18 11:59:59 -07:00
parent 0a5347f40d
commit bbbb93eb48
30 changed files with 7585 additions and 7932 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -25597,25 +25597,10 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
return N0;
// If this is an insert of an extracted vector into an undef vector, we can
// just use the input to the extract if the types match, and can simplify
// in some cases even if they don't..
// just use the input to the extract.
if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
N1.getOperand(1) == N2) {
EVT SrcVT = N1.getOperand(0).getValueType();
if (SrcVT == VT)
return N1.getOperand(0);
// TODO: To remove the zero check, need to adjust the offset to
// a multiple of the new src type.
if (isNullConstant(N2) &&
VT.isScalableVector() == SrcVT.isScalableVector()) {
if (VT.getVectorMinNumElements() >= SrcVT.getVectorMinNumElements())
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N),
VT, N0, N1.getOperand(0), N2);
else
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
VT, N1.getOperand(0), N2);
}
}
N1.getOperand(1) == N2 && N1.getOperand(0).getValueType() == VT)
return N1.getOperand(0);
// Simplify scalar inserts into an undef vector:
// insert_subvector undef, (splat X), N2 -> splat X

24
llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
View File

@ -103,15 +103,15 @@ define <8 x i1> @fv8(ptr %p, i64 %index, i64 %tc) {
define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: ret
@ -122,15 +122,15 @@ define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {
define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
@ -157,15 +157,15 @@ define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {
define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv128:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: lui a0, %hi(.LCPI10_1)

9
llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
View File

@ -469,14 +469,13 @@ define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in)
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v13, v10, a0
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v12, v9, a0
; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v12, v10, a0
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslidedown.vx v9, v10, a0
; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
ret <vscale x 6 x half> %res

472
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
View File

@ -141,12 +141,13 @@ define <4 x i64> @sextload_v4i8_v4i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v4i8_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v8
; LMULMAX1-NEXT: vsext.vf8 v8, v10
; LMULMAX1-NEXT: vsext.vf8 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v4i8_v4i64:
@ -164,12 +165,13 @@ define <4 x i64> @zextload_v4i8_v4i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v4i8_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v8
; LMULMAX1-NEXT: vzext.vf8 v8, v10
; LMULMAX1-NEXT: vzext.vf8 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v4i8_v4i64:
@ -211,12 +213,13 @@ define <8 x i32> @sextload_v8i8_v8i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i8_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v8
; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i8_v8i32:
@ -234,12 +237,13 @@ define <8 x i32> @zextload_v8i8_v8i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i8_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v8
; LMULMAX1-NEXT: vzext.vf4 v8, v10
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i8_v8i32:
@ -265,13 +269,13 @@ define <8 x i64> @sextload_v8i8_v8i64(ptr %x) {
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i8_v8i64:
@ -297,13 +301,13 @@ define <8 x i64> @zextload_v8i8_v8i64(ptr %x) {
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i8_v8i64:
@ -321,12 +325,13 @@ define <16 x i16> @sextload_v16i8_v16i16(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8
; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i8_v16i16:
@ -344,12 +349,13 @@ define <16 x i16> @zextload_v16i8_v16i16(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8
; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i8_v16i16:
@ -375,13 +381,13 @@ define <16 x i32> @sextload_v16i8_v16i32(ptr %x) {
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i8_v16i32:
@ -407,13 +413,13 @@ define <16 x i32> @zextload_v16i8_v16i32(ptr %x) {
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i8_v16i32:
@ -442,37 +448,38 @@ define <16 x i64> @sextload_v16i8_v16i64(ptr %x) {
; LMULMAX1-NEXT: vslidedown.vi v13, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v10, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v14, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v13, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v11, 4
; LMULMAX1-NEXT: vslidedown.vi v16, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v14, v11
; LMULMAX1-NEXT: vsext.vf8 v14, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v11, 2
; LMULMAX1-NEXT: vslidedown.vi v15, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v15, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v10, v11
; LMULMAX1-NEXT: vsext.vf8 v11, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v11, 2
; LMULMAX1-NEXT: vslidedown.vi v16, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v11, v16
; LMULMAX1-NEXT: vsext.vf8 v15, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i8_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX4-NEXT: vle8.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf8 v12, v8
; LMULMAX4-NEXT: vsext.vf8 v8, v16
; LMULMAX4-NEXT: vsext.vf8 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf8 v12, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x
%z = sext <16 x i8> %y to <16 x i64>
@ -494,37 +501,38 @@ define <16 x i64> @zextload_v16i8_v16i64(ptr %x) {
; LMULMAX1-NEXT: vslidedown.vi v13, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v10, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v14, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v13, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v11, 4
; LMULMAX1-NEXT: vslidedown.vi v16, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v14, v11
; LMULMAX1-NEXT: vzext.vf8 v14, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v11, 2
; LMULMAX1-NEXT: vslidedown.vi v15, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v15, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v10, v11
; LMULMAX1-NEXT: vzext.vf8 v11, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v11, 2
; LMULMAX1-NEXT: vslidedown.vi v16, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v11, v16
; LMULMAX1-NEXT: vzext.vf8 v15, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i8_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX4-NEXT: vle8.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf8 v12, v8
; LMULMAX4-NEXT: vzext.vf8 v8, v16
; LMULMAX4-NEXT: vzext.vf8 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf8 v12, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x
%z = zext <16 x i8> %y to <16 x i64>
@ -652,12 +660,13 @@ define <4 x i64> @sextload_v4i16_v4i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v4i16_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v8
; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v4i16_v4i64:
@ -675,12 +684,13 @@ define <4 x i64> @zextload_v4i16_v4i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v4i16_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v8
; LMULMAX1-NEXT: vzext.vf4 v8, v10
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v4i16_v4i64:
@ -710,12 +720,13 @@ define <8 x i32> @sextload_v8i16_v8i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i16_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i16_v8i32:
@ -733,12 +744,13 @@ define <8 x i32> @zextload_v8i16_v8i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i16_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i16_v8i32:
@ -764,13 +776,13 @@ define <8 x i64> @sextload_v8i16_v8i64(ptr %x) {
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i16_v8i64:
@ -796,13 +808,13 @@ define <8 x i64> @zextload_v8i16_v8i64(ptr %x) {
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i16_v8i64:
@ -842,19 +854,20 @@ define <16 x i32> @sextload_v16i16_v16i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i16_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vle16.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v12, 4
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i16_v16i32:
@ -872,19 +885,20 @@ define <16 x i32> @zextload_v16i16_v16i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i16_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vle16.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v12, 4
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i16_v16i32:
@ -911,38 +925,39 @@ define <16 x i64> @sextload_v16i16_v16i64(ptr %x) {
; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: vsext.vf4 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v13, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vslidedown.vi v16, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v15, v16
; LMULMAX1-NEXT: vsext.vf4 v9, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v13, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v15, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i16_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf4 v12, v8
; LMULMAX4-NEXT: vsext.vf4 v8, v16
; LMULMAX4-NEXT: vsext.vf4 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf4 v12, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i16>, ptr %x
%z = sext <16 x i16> %y to <16 x i64>
@ -962,38 +977,39 @@ define <16 x i64> @zextload_v16i16_v16i64(ptr %x) {
; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v12
; LMULMAX1-NEXT: vzext.vf4 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v13, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vslidedown.vi v16, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v15, v16
; LMULMAX1-NEXT: vzext.vf4 v9, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v13, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v15, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i16_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf4 v12, v8
; LMULMAX4-NEXT: vzext.vf4 v8, v16
; LMULMAX4-NEXT: vzext.vf4 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf4 v12, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i16>, ptr %x
%z = zext <16 x i16> %y to <16 x i64>
@ -1080,12 +1096,13 @@ define <4 x i64> @sextload_v4i32_v4i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v4i32_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v4i32_v4i64:
@ -1103,12 +1120,13 @@ define <4 x i64> @zextload_v4i32_v4i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v4i32_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v4i32_v4i64:
@ -1177,19 +1195,20 @@ define <8 x i64> @sextload_v8i32_v8i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i32_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v12, 2
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i32_v8i64:
@ -1207,19 +1226,20 @@ define <8 x i64> @zextload_v8i32_v8i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i32_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v12, 2
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i32_v8i64:
@ -1308,43 +1328,45 @@ define <16 x i64> @sextload_v16i32_v16i64(ptr %x) {
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v16, (a1)
; LMULMAX1-NEXT: vle32.v v15, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vle32.v v14, (a1)
; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vle32.v v13, (a1)
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v12, 2
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v10
; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v14, 2
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v13, v10
; LMULMAX1-NEXT: vsext.vf2 v11, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2
; LMULMAX1-NEXT: vslidedown.vi v14, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v15, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v14
; LMULMAX1-NEXT: vsext.vf2 v14, v16
; LMULMAX1-NEXT: vsext.vf2 v13, v14
; LMULMAX1-NEXT: vsext.vf2 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v15, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i32_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle32.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf2 v12, v8
; LMULMAX4-NEXT: vsext.vf2 v8, v16
; LMULMAX4-NEXT: vsext.vf2 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf2 v12, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i32>, ptr %x
%z = sext <16 x i32> %y to <16 x i64>
@ -1356,43 +1378,45 @@ define <16 x i64> @zextload_v16i32_v16i64(ptr %x) {
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v16, (a1)
; LMULMAX1-NEXT: vle32.v v15, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vle32.v v14, (a1)
; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vle32.v v13, (a1)
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v12, 2
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v10
; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v14, 2
; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v13, v10
; LMULMAX1-NEXT: vzext.vf2 v11, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2
; LMULMAX1-NEXT: vslidedown.vi v14, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v15, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v14
; LMULMAX1-NEXT: vzext.vf2 v14, v16
; LMULMAX1-NEXT: vzext.vf2 v13, v14
; LMULMAX1-NEXT: vzext.vf2 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v15, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i32_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle32.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf2 v12, v8
; LMULMAX4-NEXT: vzext.vf2 v8, v16
; LMULMAX4-NEXT: vzext.vf2 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf2 v12, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i32>, ptr %x
%z = zext <16 x i32> %y to <16 x i64>

32
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
View File

@ -84,27 +84,27 @@ define void @fpext_v8f16_v8f64(ptr %x, ptr %y) {
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v8
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v10
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v12
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v11, (a1)
; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a1, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a1)
; LMULMAX1-NEXT: ret

28
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
View File

@ -493,20 +493,20 @@ define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) {
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v10, v8
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v11, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v12, v8
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v11, v8
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v9, v8
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v12, v9
; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v11, (a1)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: ret
@ -533,20 +533,20 @@ define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v11, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v11, v8
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v12, v9
; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v11, (a1)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: ret

50
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
View File

@ -449,23 +449,22 @@ define void @si2fp_v8i16_v8f64(ptr %x, ptr %y) {
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v10, v9
; LMULMAX1-NEXT: vfwcvt.f.x.v v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v8
; LMULMAX1-NEXT: vfwcvt.f.x.v v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v10, v8
; LMULMAX1-NEXT: vfwcvt.f.x.v v12, v10
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v10, v8
; LMULMAX1-NEXT: vfwcvt.f.x.v v8, v10
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: vsext.vf2 v12, v11
; LMULMAX1-NEXT: vfwcvt.f.x.v v11, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v8
; LMULMAX1-NEXT: vfwcvt.f.x.v v8, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v10
; LMULMAX1-NEXT: vfwcvt.f.x.v v10, v12
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v11, (a1)
; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a1, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a1)
; LMULMAX1-NEXT: ret
@ -494,23 +493,22 @@ define void @ui2fp_v8i16_v8f64(ptr %x, ptr %y) {
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v10, v9
; LMULMAX1-NEXT: vfwcvt.f.xu.v v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v8
; LMULMAX1-NEXT: vfwcvt.f.xu.v v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v10, v8
; LMULMAX1-NEXT: vfwcvt.f.xu.v v12, v10
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v10, v8
; LMULMAX1-NEXT: vfwcvt.f.xu.v v8, v10
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: vzext.vf2 v12, v11
; LMULMAX1-NEXT: vfwcvt.f.xu.v v11, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v8
; LMULMAX1-NEXT: vfwcvt.f.xu.v v8, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v10
; LMULMAX1-NEXT: vfwcvt.f.xu.v v10, v12
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v11, (a1)
; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a1, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a1)
; LMULMAX1-NEXT: ret

65
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
View File

@ -90,20 +90,19 @@ define void @sext_v32i8_v32i32(ptr %x, ptr %z) {
; LMULMAX2-NEXT: vslidedown.vi v10, v8, 8
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vsext.vf4 v12, v10
; LMULMAX2-NEXT: vsext.vf4 v10, v8
; LMULMAX2-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; LMULMAX2-NEXT: vslidedown.vi v8, v8, 16
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vsext.vf4 v14, v8
; LMULMAX2-NEXT: vslidedown.vi v10, v8, 16
; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX2-NEXT: vslidedown.vi v8, v8, 8
; LMULMAX2-NEXT: vslidedown.vi v9, v10, 8
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vsext.vf4 v14, v9
; LMULMAX2-NEXT: vsext.vf4 v16, v8
; LMULMAX2-NEXT: addi a0, a1, 96
; LMULMAX2-NEXT: vse32.v v16, (a0)
; LMULMAX2-NEXT: vsext.vf4 v8, v10
; LMULMAX2-NEXT: addi a0, a1, 64
; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: vse32.v v16, (a1)
; LMULMAX2-NEXT: addi a0, a1, 96
; LMULMAX2-NEXT: vse32.v v14, (a0)
; LMULMAX2-NEXT: vse32.v v10, (a1)
; LMULMAX2-NEXT: addi a0, a1, 32
; LMULMAX2-NEXT: vse32.v v12, (a0)
; LMULMAX2-NEXT: ret
@ -118,41 +117,39 @@ define void @sext_v32i8_v32i32(ptr %x, ptr %z) {
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v12, v10
; LMULMAX1-NEXT: vsext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v13, v8
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vslidedown.vi v12, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v14, v8
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsext.vf4 v13, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v14, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v9, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v15, v9
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v9, v9, 4
; LMULMAX1-NEXT: vslidedown.vi v15, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v16, v9
; LMULMAX1-NEXT: vsext.vf4 v16, v15
; LMULMAX1-NEXT: vsext.vf4 v15, v8
; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: vsext.vf4 v10, v9
; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: addi a0, a1, 96
; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a1, 64
; LMULMAX1-NEXT: vse32.v v15, (a0)
; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse32.v v15, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 112
; LMULMAX1-NEXT: vse32.v v14, (a0)
; LMULMAX1-NEXT: addi a0, a1, 96
; LMULMAX1-NEXT: vse32.v v13, (a0)
; LMULMAX1-NEXT: addi a0, a1, 64
; LMULMAX1-NEXT: vse32.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse32.v v12, (a0)
; LMULMAX1-NEXT: vse32.v v14, (a0)
; LMULMAX1-NEXT: addi a0, a1, 112
; LMULMAX1-NEXT: vse32.v v13, (a0)
; LMULMAX1-NEXT: addi a0, a1, 80
; LMULMAX1-NEXT: vse32.v v11, (a0)
; LMULMAX1-NEXT: ret

100
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
View File

@ -780,19 +780,19 @@ define void @sdiv_v6i16(ptr %x, ptr %y) {
; CHECK-LABEL: sdiv_v6i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vslidedown.vi v11, v9, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdiv.vv v10, v11, v10
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vdiv.vv v8, v9, v8
; CHECK-NEXT: vdiv.vv v10, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v9, 4
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: vslideup.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x
%b = load <6 x i16>, ptr %y
@ -869,19 +869,19 @@ define void @srem_v6i16(ptr %x, ptr %y) {
; CHECK-LABEL: srem_v6i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vslidedown.vi v11, v9, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vrem.vv v10, v11, v10
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vrem.vv v8, v9, v8
; CHECK-NEXT: vrem.vv v10, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v9, 4
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vrem.vv v8, v8, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: vslideup.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x
%b = load <6 x i16>, ptr %y
@ -958,19 +958,19 @@ define void @udiv_v6i16(ptr %x, ptr %y) {
; CHECK-LABEL: udiv_v6i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vslidedown.vi v11, v9, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdivu.vv v10, v11, v10
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vdivu.vv v8, v9, v8
; CHECK-NEXT: vdivu.vv v10, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v9, 4
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: vslideup.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x
%b = load <6 x i16>, ptr %y
@ -1047,19 +1047,19 @@ define void @urem_v6i16(ptr %x, ptr %y) {
; CHECK-LABEL: urem_v6i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vslidedown.vi v11, v9, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vremu.vv v10, v11, v10
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vremu.vv v8, v9, v8
; CHECK-NEXT: vremu.vv v10, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v9, 4
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vremu.vv v8, v8, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: vslideup.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x
%b = load <6 x i16>, ptr %y
@ -1244,22 +1244,22 @@ define void @mulhu_v6i16(ptr %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vadd.vi v9, v9, 12
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdivu.vv v9, v10, v9
; CHECK-NEXT: lui a1, %hi(.LCPI67_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI67_0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vdivu.vv v9, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vadd.vi v10, v10, 12
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x
%b = udiv <6 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13>

3500
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
View File

File diff suppressed because it is too large Load Diff

3236
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
View File

File diff suppressed because it is too large Load Diff

96
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
View File

@ -541,6 +541,57 @@ define <8 x i1> @fcmp_uno_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
declare <128 x i1> @llvm.vp.fcmp.v128f16(<128 x half>, <128 x half>, metadata, <128 x i1>, i32)
define <128 x i1> @fcmp_oeq_vv_v128f16(<128 x half> %va, <128 x half> %vb, <128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_oeq_vv_v128f16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: addi a0, a2, -64
; CHECK-NEXT: sltu a3, a2, a0
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 8
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v1, v16, v8, v0.t
; CHECK-NEXT: bltu a2, a1, .LBB43_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: .LBB43_2:
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vslideup.vi v16, v1, 8
; CHECK-NEXT: vmv.v.v v0, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%v = call <128 x i1> @llvm.vp.fcmp.v128f16(<128 x half> %va, <128 x half> %vb, metadata !"oeq", <128 x i1> %m, i32 %evl)
ret <128 x i1> %v
}
@ -1109,45 +1160,44 @@ define <32 x i1> @fcmp_oeq_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: bltu a2, a1, .LBB87_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB87_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v2, v8, v24, v0.t
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmfeq.vv v1, v16, v8, v0.t
; CHECK-NEXT: bltu a2, a0, .LBB87_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB87_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v24, v16, v8, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v2, v24, 2
; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: vslideup.vi v16, v1, 2
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0

214
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
View File

@ -1315,109 +1315,57 @@ define <8 x i1> @icmp_sle_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext
declare <64 x i1> @llvm.vp.icmp.v64i32(<64 x i32>, <64 x i32>, metadata, <64 x i1>, i32)
define <64 x i1> @icmp_eq_vv_v64i32(<64 x i32> %va, <64 x i32> %vb, <64 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vv_v64i32:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vle32.v v24, (a1)
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vle32.v v24, (a0)
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v1, v0, 4
; RV32-NEXT: mv a0, a2
; RV32-NEXT: bltu a2, a3, .LBB99_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 32
; RV32-NEXT: .LBB99_2:
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmseq.vv v2, v8, v24, v0.t
; RV32-NEXT: addi a0, a2, -32
; RV32-NEXT: sltu a1, a2, a0
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmseq.vv v24, v16, v8, v0.t
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vi v2, v24, 4
; RV32-NEXT: vmv1r.v v0, v2
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: icmp_eq_vv_v64i32:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vle32.v v24, (a0)
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64-NEXT: mv a0, a2
; RV64-NEXT: vslidedown.vi v1, v0, 4
; RV64-NEXT: bltu a2, a3, .LBB99_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 32
; RV64-NEXT: .LBB99_2:
; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV64-NEXT: vmseq.vv v2, v8, v24, v0.t
; RV64-NEXT: addi a0, a2, -32
; RV64-NEXT: sltu a1, a2, a0
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a0, a1, a0
; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-NEXT: vmseq.vv v24, v16, v8, v0.t
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vi v2, v24, 4
; RV64-NEXT: vmv1r.v v0, v2
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
; CHECK-LABEL: icmp_eq_vv_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: addi a0, a2, -32
; CHECK-NEXT: sltu a3, a2, a0
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vv v1, v16, v8, v0.t
; CHECK-NEXT: bltu a2, a1, .LBB99_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB99_2:
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmseq.vv v16, v8, v24, v0.t
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v16, v1, 4
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%v = call <64 x i1> @llvm.vp.icmp.v64i32(<64 x i32> %va, <64 x i32> %vb, metadata !"eq", <64 x i1> %m, i32 %evl)
ret <64 x i1> %v
}
@ -1425,26 +1373,26 @@ define <64 x i1> @icmp_eq_vv_v64i32(<64 x i32> %va, <64 x i32> %vb, <64 x i1> %m
define <64 x i1> @icmp_eq_vx_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vx_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vslidedown.vi v24, v0, 4
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB100_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB100_2:
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vslidedown.vi v0, v0, 4
; CHECK-NEXT: addi a2, a1, -32
; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: sltu a3, a1, a2
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB100_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB100_2:
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmseq.vx v8, v16, a0, v0.t
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v25, v8, 4
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vslideup.vi v16, v25, 4
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <64 x i32> poison, i32 %b, i32 0
%vb = shufflevector <64 x i32> %elt.head, <64 x i32> poison, <64 x i32> zeroinitializer
@ -1455,26 +1403,26 @@ define <64 x i1> @icmp_eq_vx_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 ze
define <64 x i1> @icmp_eq_vx_swap_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vx_swap_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vslidedown.vi v24, v0, 4
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB101_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB101_2:
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vslidedown.vi v0, v0, 4
; CHECK-NEXT: addi a2, a1, -32
; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: sltu a3, a1, a2
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB101_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB101_2:
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmseq.vx v8, v16, a0, v0.t
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v25, v8, 4
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vslideup.vi v16, v25, 4
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <64 x i32> poison, i32 %b, i32 0
%vb = shufflevector <64 x i32> %elt.head, <64 x i32> poison, <64 x i32> zeroinitializer

73
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
View File

@ -91,37 +91,26 @@ define <64 x float> @vfwadd_v64f16(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vfwadd.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwadd.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwadd.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -203,36 +192,24 @@ define <32 x double> @vfwadd_v32f32(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vfwadd.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwadd.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwadd.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwadd.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -398,10 +375,10 @@ define <32 x double> @vfwadd_vf_v32f32(ptr %x, float %y) {
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: vfwadd.wv v16, v8, v0
; CHECK-NEXT: vfwadd.wv v8, v8, v24
; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vfwadd.wv v8, v16, v24
; CHECK-NEXT: vfwadd.wv v16, v16, v0
; CHECK-NEXT: ret
%a = load <32 x float>, ptr %x
%b = insertelement <32 x float> poison, float %y, i32 0

78
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
View File

@ -91,37 +91,26 @@ define <64 x float> @vfwmul_v64f16(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vfwmul.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwmul.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwmul.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -203,36 +192,24 @@ define <32 x double> @vfwmul_v32f32(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vfwmul.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwmul.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwmul.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwmul.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -394,18 +371,17 @@ define <32 x double> @vfwmul_vf_v32f32(ptr %x, float %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v16, 16
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v24, v16
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v0, v16
; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: vfwcvt.f.f.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmul.vv v8, v16, v0
; CHECK-NEXT: vfmul.vv v16, v24, v0
; CHECK-NEXT: vfmul.vv v8, v8, v0
; CHECK-NEXT: ret
%a = load <32 x float>, ptr %x
%b = insertelement <32 x float> poison, float %y, i32 0

78
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
View File

@ -91,37 +91,26 @@ define <64 x float> @vfwsub_v64f16(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vfwsub.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwsub.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwsub.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -203,36 +192,24 @@ define <32 x double> @vfwsub_v32f32(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vfwsub.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwsub.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwsub.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfwsub.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -394,18 +371,17 @@ define <32 x double> @vfwsub_vf_v32f32(ptr %x, float %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v16, 16
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v24, v16
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v0, v16
; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: vfwcvt.f.f.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfsub.vv v8, v16, v0
; CHECK-NEXT: vfsub.vv v16, v24, v0
; CHECK-NEXT: vfsub.vv v8, v8, v0
; CHECK-NEXT: ret
%a = load <32 x float>, ptr %x
%b = insertelement <32 x float> poison, float %y, i32 0

29
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
View File

@ -2468,32 +2468,31 @@ define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32>
define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32f64:
; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v24, v16, 0
; RV32-NEXT: vnsrl.wi v16, v8, 0
; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vslideup.vi v16, v24, 16
; RV32-NEXT: vsll.vi v24, v16, 3
; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB96_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB96_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2
; RV32-NEXT: addi a3, a3, -1
; RV32-NEXT: and a2, a3, a2
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB96_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB96_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v32f64:

90
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
View File

@ -250,36 +250,25 @@ define <128 x i16> @vwadd_v128i16(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwadd.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwadd.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwadd.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -296,36 +285,25 @@ define <64 x i32> @vwadd_v64i32(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwadd.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwadd.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwadd.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -342,35 +320,23 @@ define <32 x i64> @vwadd_v32i64(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwadd.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwadd.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwadd.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwadd.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

90
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
View File

@ -250,36 +250,25 @@ define <128 x i16> @vwaddu_v128i16(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwaddu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwaddu.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwaddu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -296,36 +285,25 @@ define <64 x i32> @vwaddu_v64i32(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwaddu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwaddu.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwaddu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -342,35 +320,23 @@ define <32 x i64> @vwaddu_v32i64(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwaddu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwaddu.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwaddu.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwaddu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

96
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
View File

@ -275,37 +275,26 @@ define <128 x i16> @vwmul_v128i16(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmul.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmul.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmul.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -323,37 +312,26 @@ define <64 x i32> @vwmul_v64i32(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmul.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmul.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmul.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -371,36 +349,24 @@ define <32 x i64> @vwmul_v32i64(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmul.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmul.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwmul.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmul.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

96
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
View File

@ -267,37 +267,26 @@ define <128 x i16> @vwmulsu_v128i16(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmulsu.vv v8, v24, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulsu.vv v8, v0, v16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulsu.vv v16, v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -315,37 +304,26 @@ define <64 x i32> @vwmulsu_v64i32(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmulsu.vv v8, v24, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulsu.vv v8, v0, v16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulsu.vv v16, v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -363,36 +341,24 @@ define <32 x i64> @vwmulsu_v32i64(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmulsu.vv v8, v24, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulsu.vv v8, v0, v16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwmulsu.vv v8, v24, v16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulsu.vv v16, v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

96
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
View File

@ -251,37 +251,26 @@ define <128 x i16> @vwmulu_v128i16(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmulu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulu.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -299,37 +288,26 @@ define <64 x i32> @vwmulu_v64i32(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmulu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulu.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -347,36 +325,24 @@ define <32 x i64> @vwmulu_v32i64(ptr %x, ptr %y) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwmulu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulu.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwmulu.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwmulu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

90
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
View File

@ -250,36 +250,25 @@ define <128 x i16> @vwsub_v128i16(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwsub.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsub.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsub.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -296,36 +285,25 @@ define <64 x i32> @vwsub_v64i32(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwsub.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsub.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsub.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -342,35 +320,23 @@ define <32 x i64> @vwsub_v32i64(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwsub.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsub.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwsub.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsub.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

90
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
View File

@ -250,36 +250,25 @@ define <128 x i16> @vwsubu_v128i16(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle8.v v0, (a1)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwsubu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsubu.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsubu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -296,36 +285,25 @@ define <64 x i32> @vwsubu_v64i32(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle16.v v0, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vx v0, v24, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwsubu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsubu.vv v8, v16, v0
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsubu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@ -342,35 +320,23 @@ define <32 x i64> @vwsubu_v32i64(ptr %x, ptr %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle32.v v0, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vslidedown.vi v8, v0, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vwsubu.vv v8, v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsubu.vv v8, v16, v0
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vslidedown.vi v0, v24, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vwsubu.vv v8, v16, v24
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vwsubu.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret

20
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
View File

@ -258,16 +258,16 @@ define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vmv2r.v v20, v10
; RV32-NEXT: vmv2r.v v12, v8
; RV32-NEXT: vrgather.vv v8, v12, v16
; RV32-NEXT: vid.v v12
; RV32-NEXT: vrsub.vi v12, v12, 15
; RV32-NEXT: vrgather.vv v12, v8, v16
; RV32-NEXT: vid.v v8
; RV32-NEXT: vrsub.vi v8, v8, 15
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV32-NEXT: vrgather.vv v8, v20, v12, v0.t
; RV32-NEXT: vrgather.vv v12, v20, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: v16i16_2:
@ -278,16 +278,16 @@ define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; RV64-NEXT: vle16.v v16, (a0)
; RV64-NEXT: vmv2r.v v20, v10
; RV64-NEXT: vmv2r.v v12, v8
; RV64-NEXT: vrgather.vv v8, v12, v16
; RV64-NEXT: vid.v v12
; RV64-NEXT: vrsub.vi v12, v12, 15
; RV64-NEXT: vrgather.vv v12, v8, v16
; RV64-NEXT: vid.v v8
; RV64-NEXT: vrsub.vi v8, v8, 15
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV64-NEXT: vrgather.vv v8, v20, v12, v0.t
; RV64-NEXT: vrgather.vv v12, v20, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret
%v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i16> %v32i16

15
llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
View File

@ -159,10 +159,8 @@ define <vscale x 1 x i32> @extract_vector_multiuse2(ptr %p, ptr %p2, i32 %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a2
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0
%splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@ -177,10 +175,8 @@ define void @extract_vector_mixed1(ptr %p, ptr %p2, i32 %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a2
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
@ -200,8 +196,6 @@ define void @extract_vector_mixed2(ptr %p, ptr %p2, i32 %v) {
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a2
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v8, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
@ -219,12 +213,9 @@ define void @extract_vector_mixed3(ptr %p, ptr %p2, i32 %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a2
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v9, (a1)
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0
%splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer

8
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
View File

@ -107,10 +107,10 @@ ret {<4 x i32>, <4 x i32>} %retval
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
@ -194,10 +194,10 @@ ret {<4 x float>, <4 x float>} %retval
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t

28
llvm/test/CodeGen/X86/pr33349.ll
View File

@ -10,20 +10,20 @@ target triple = "x86_64-unknown-linux-gnu"
; KNL: # %bb.0: # %bb
; KNL-NEXT: vpslld $31, %xmm0, %xmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kshiftrw $1, %k0, %k1
; KNL-NEXT: kmovw %k1, %eax
; KNL-NEXT: kshiftrw $2, %k0, %k1
; KNL-NEXT: kshiftrw $1, %k1, %k2
; KNL-NEXT: kmovw %k1, %eax
; KNL-NEXT: kmovw %k1, %ecx
; KNL-NEXT: testb $1, %al
; KNL-NEXT: fld1
; KNL-NEXT: fldz
; KNL-NEXT: fld %st(0)
; KNL-NEXT: fcmovne %st(2), %st
; KNL-NEXT: kmovw %k2, %eax
; KNL-NEXT: testb $1, %al
; KNL-NEXT: testb $1, %cl
; KNL-NEXT: fld %st(1)
; KNL-NEXT: fcmovne %st(3), %st
; KNL-NEXT: kshiftrw $1, %k0, %k1
; KNL-NEXT: kmovw %k1, %eax
; KNL-NEXT: kmovw %k2, %eax
; KNL-NEXT: testb $1, %al
; KNL-NEXT: fld %st(2)
; KNL-NEXT: fcmovne %st(4), %st
@ -35,10 +35,10 @@ target triple = "x86_64-unknown-linux-gnu"
; KNL-NEXT: fxch %st(3)
; KNL-NEXT: fstpt (%rdi)
; KNL-NEXT: fxch %st(1)
; KNL-NEXT: fstpt 10(%rdi)
; KNL-NEXT: fxch %st(1)
; KNL-NEXT: fstpt 30(%rdi)
; KNL-NEXT: fxch %st(1)
; KNL-NEXT: fstpt 20(%rdi)
; KNL-NEXT: fstpt 10(%rdi)
; KNL-NEXT: vzeroupper
; KNL-NEXT: retq
;
@ -46,20 +46,20 @@ target triple = "x86_64-unknown-linux-gnu"
; SKX: # %bb.0: # %bb
; SKX-NEXT: vpslld $31, %xmm0, %xmm0
; SKX-NEXT: vpmovd2m %xmm0, %k0
; SKX-NEXT: kshiftrb $1, %k0, %k1
; SKX-NEXT: kmovd %k1, %eax
; SKX-NEXT: kshiftrb $2, %k0, %k1
; SKX-NEXT: kshiftrb $1, %k1, %k2
; SKX-NEXT: kmovd %k1, %eax
; SKX-NEXT: kmovd %k1, %ecx
; SKX-NEXT: testb $1, %al
; SKX-NEXT: fld1
; SKX-NEXT: fldz
; SKX-NEXT: fld %st(0)
; SKX-NEXT: fcmovne %st(2), %st
; SKX-NEXT: kmovd %k2, %eax
; SKX-NEXT: testb $1, %al
; SKX-NEXT: testb $1, %cl
; SKX-NEXT: fld %st(1)
; SKX-NEXT: fcmovne %st(3), %st
; SKX-NEXT: kshiftrb $1, %k0, %k1
; SKX-NEXT: kmovd %k1, %eax
; SKX-NEXT: kmovd %k2, %eax
; SKX-NEXT: testb $1, %al
; SKX-NEXT: fld %st(2)
; SKX-NEXT: fcmovne %st(4), %st
@ -71,10 +71,10 @@ target triple = "x86_64-unknown-linux-gnu"
; SKX-NEXT: fxch %st(3)
; SKX-NEXT: fstpt (%rdi)
; SKX-NEXT: fxch %st(1)
; SKX-NEXT: fstpt 10(%rdi)
; SKX-NEXT: fxch %st(1)
; SKX-NEXT: fstpt 30(%rdi)
; SKX-NEXT: fxch %st(1)
; SKX-NEXT: fstpt 20(%rdi)
; SKX-NEXT: fstpt 10(%rdi)
; SKX-NEXT: retq
bb:
%tmp = select <4 x i1> %m, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer

14
llvm/test/CodeGen/X86/pr34177.ll
View File

@ -49,20 +49,20 @@ define void @test(<4 x i64> %a, <4 x x86_fp80> %b, ptr %c) local_unnamed_addr {
; AVX512VL-LABEL: test:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
; AVX512VL-NEXT: kshiftrb $1, %k0, %k1
; AVX512VL-NEXT: kshiftrb $2, %k0, %k2
; AVX512VL-NEXT: kshiftrb $2, %k0, %k1
; AVX512VL-NEXT: kshiftrb $1, %k0, %k2
; AVX512VL-NEXT: kmovd %k0, %eax
; AVX512VL-NEXT: testb $1, %al
; AVX512VL-NEXT: fld1
; AVX512VL-NEXT: fldz
; AVX512VL-NEXT: fld %st(0)
; AVX512VL-NEXT: fcmovne %st(2), %st
; AVX512VL-NEXT: kmovd %k1, %eax
; AVX512VL-NEXT: kshiftrb $1, %k1, %k0
; AVX512VL-NEXT: kmovd %k0, %eax
; AVX512VL-NEXT: testb $1, %al
; AVX512VL-NEXT: fld %st(1)
; AVX512VL-NEXT: fcmovne %st(3), %st
; AVX512VL-NEXT: kshiftrb $1, %k2, %k0
; AVX512VL-NEXT: kmovd %k0, %eax
; AVX512VL-NEXT: kmovd %k1, %eax
; AVX512VL-NEXT: testb $1, %al
; AVX512VL-NEXT: fld %st(2)
; AVX512VL-NEXT: fcmovne %st(4), %st
@ -83,11 +83,11 @@ define void @test(<4 x i64> %a, <4 x x86_fp80> %b, ptr %c) local_unnamed_addr {
; AVX512VL-NEXT: fadd %st, %st(0)
; AVX512VL-NEXT: fstpt (%rdi)
; AVX512VL-NEXT: fadd %st, %st(0)
; AVX512VL-NEXT: fstpt 20(%rdi)
; AVX512VL-NEXT: fadd %st, %st(0)
; AVX512VL-NEXT: fstpt 60(%rdi)
; AVX512VL-NEXT: fadd %st, %st(0)
; AVX512VL-NEXT: fstpt 40(%rdi)
; AVX512VL-NEXT: fadd %st, %st(0)
; AVX512VL-NEXT: fstpt 20(%rdi)
%1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, %a
%2 = select <4 x i1> %1, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer
%3 = fadd <4 x x86_fp80> %2, %2

6679
llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
View File

File diff suppressed because it is too large Load Diff