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[DAG] SimplifyDemandedBits - ensure we have simplified the shift operands before folding to AVG

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Pulled out of #92096 - ensure we have completed a topological simplification of the SRA/SRL shift operands before we try to combine to a AVG node, as its difficult to later simplify through AVG nodes.
This commit is contained in:
Simon Pilgrim 2024-05-22 11:53:59 +01:00
parent 8619054fb7
commit bbc4c2e047
2 changed files with 13 additions and 11 deletions
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22
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1908,11 +1908,6 @@ bool TargetLowering::SimplifyDemandedBits(
SDValue Op1 = Op.getOperand(1);
EVT ShiftVT = Op1.getValueType();
// Try to match AVG patterns.
if (SDValue AVG = combineShiftToAVG(Op, TLO.DAG, *this, DemandedBits,
DemandedElts, Depth + 1))
return TLO.CombineTo(Op, AVG);
KnownBits KnownSA = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1);
if (KnownSA.isConstant() && KnownSA.getConstant().ult(BitWidth)) {
unsigned ShAmt = KnownSA.getConstant().getZExtValue();
@ -1994,6 +1989,12 @@ bool TargetLowering::SimplifyDemandedBits(
// shift amounts.
Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
}
// Try to match AVG patterns (after shift simplification).
if (SDValue AVG = combineShiftToAVG(Op, TLO.DAG, *this, DemandedBits,
DemandedElts, Depth + 1))
return TLO.CombineTo(Op, AVG);
break;
}
case ISD::SRA: {
@ -2015,11 +2016,6 @@ bool TargetLowering::SimplifyDemandedBits(
if (DemandedBits.isOne())
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
// Try to match AVG patterns.
if (SDValue AVG = combineShiftToAVG(Op, TLO.DAG, *this, DemandedBits,
DemandedElts, Depth + 1))
return TLO.CombineTo(Op, AVG);
KnownBits KnownSA = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1);
if (KnownSA.isConstant() && KnownSA.getConstant().ult(BitWidth)) {
unsigned ShAmt = KnownSA.getConstant().getZExtValue();
@ -2106,6 +2102,12 @@ bool TargetLowering::SimplifyDemandedBits(
}
}
}
// Try to match AVG patterns (after shift simplification).
if (SDValue AVG = combineShiftToAVG(Op, TLO.DAG, *this, DemandedBits,
DemandedElts, Depth + 1))
return TLO.CombineTo(Op, AVG);
break;
}
case ISD::FSHL:

2
llvm/test/CodeGen/AArch64/arm64-vhadd.ll
View File

@ -1379,7 +1379,7 @@ define <8 x i8> @sextmask2v8i8(<8 x i16> %src1, <8 x i8> %src2) {
define <8 x i8> @sextmask3v8i8(<8 x i16> %src1, <8 x i8> %src2) {
; CHECK-LABEL: sextmask3v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sshr.8h v0, v0, #7
; CHECK-NEXT: ushr.8h v0, v0, #7
; CHECK-NEXT: sshll.8h v1, v1, #0
; CHECK-NEXT: shadd.8h v0, v0, v1
; CHECK-NEXT: xtn.8b v0, v0