[PowerPC] vector shift word/double by element size - 1 use all ones (#139794)
Vector shift word or double requires a shift amount vector of 31 or 63 which is too big for splat immediate and requires a multi-instruction sequence. However the PPC instructions only use 5 or 6 bits of the shift amount vector elements so an all ones mask, which we can generate efficiently, works.
This commit is contained in:
RolandF77
GitHub
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3c9812eeea
commit
bbca78fbcb
@ -18456,36 +18456,80 @@ static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,
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return SDValue();
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}
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SDValue PPCTargetLowering::combineVectorSHL(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SDValue PPCTargetLowering::combineVectorShift(SDNode *N,
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DAGCombinerInfo &DCI) const {
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EVT VT = N->getValueType(0);
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assert(VT.isVector() && "Vector type expected.");
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unsigned Opc = N->getOpcode();
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assert((Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
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"Unexpected opcode.");
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if (!isOperationLegal(Opc, VT))
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return SDValue();
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EVT EltTy = VT.getScalarType();
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unsigned EltBits = EltTy.getSizeInBits();
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if (EltTy != MVT::i64 && EltTy != MVT::i32)
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return SDValue();
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SDValue N1 = N->getOperand(1);
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if (!Subtarget.hasP8Altivec() || N1.getOpcode() != ISD::BUILD_VECTOR ||
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!isOperationLegal(ISD::ADD, VT))
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uint64_t SplatBits = 0;
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bool AddSplatCase = false;
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unsigned OpcN1 = N1.getOpcode();
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if (OpcN1 == PPCISD::VADD_SPLAT &&
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N1.getConstantOperandVal(1) == VT.getVectorNumElements()) {
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AddSplatCase = true;
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SplatBits = N1.getConstantOperandVal(0);
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}
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if (!AddSplatCase) {
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if (OpcN1 != ISD::BUILD_VECTOR)
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return SDValue();
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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APInt APSplatBits, APSplatUndef;
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BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(N1);
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bool BVNIsConstantSplat =
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BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs, 0, !Subtarget.isLittleEndian());
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if (!BVNIsConstantSplat || SplatBitSize != EltBits)
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return SDValue();
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SplatBits = APSplatBits.getZExtValue();
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}
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SDLoc DL(N);
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SDValue N0 = N->getOperand(0);
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// PPC vector shifts by word/double look at only the low 5/6 bits of the
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// shift vector, which means the max value is 31/63. A shift vector of all
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// 1s will be truncated to 31/63, which is useful as vspltiw is limited to
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// -16 to 15 range.
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if (SplatBits == (EltBits - 1)) {
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unsigned NewOpc;
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switch (Opc) {
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case ISD::SHL:
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NewOpc = PPCISD::SHL;
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break;
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case ISD::SRL:
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NewOpc = PPCISD::SRL;
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break;
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case ISD::SRA:
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NewOpc = PPCISD::SRA;
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break;
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}
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SDValue SplatOnes = getCanonicalConstSplat(255, 1, VT, DCI.DAG, DL);
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return DCI.DAG.getNode(NewOpc, DL, VT, N0, SplatOnes);
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}
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if (Opc != ISD::SHL || !isOperationLegal(ISD::ADD, VT))
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return SDValue();
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// For 64-bit there is no splat immediate so we want to catch shift by 1 here
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// before the BUILD_VECTOR is replaced by a load.
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EVT EltTy = VT.getScalarType();
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if (EltTy != MVT::i64)
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if (EltTy != MVT::i64 || SplatBits != 1)
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return SDValue();
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BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(N1);
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APInt APSplatBits, APSplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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bool BVNIsConstantSplat =
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BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs, 0, !Subtarget.isLittleEndian());
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if (!BVNIsConstantSplat || SplatBitSize != EltTy.getSizeInBits())
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return SDValue();
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uint64_t SplatBits = APSplatBits.getZExtValue();
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if (SplatBits != 1)
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return SDValue();
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SDValue N0 = N->getOperand(0);
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return DCI.DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
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}
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@ -18494,7 +18538,7 @@ SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const {
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return Value;
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if (N->getValueType(0).isVector())
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return combineVectorSHL(N, DCI);
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return combineVectorShift(N, DCI);
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SDValue N0 = N->getOperand(0);
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ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1));
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@ -18526,6 +18570,9 @@ SDValue PPCTargetLowering::combineSRA(SDNode *N, DAGCombinerInfo &DCI) const {
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if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
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return Value;
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if (N->getValueType(0).isVector())
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return combineVectorShift(N, DCI);
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return SDValue();
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}
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@ -18533,6 +18580,9 @@ SDValue PPCTargetLowering::combineSRL(SDNode *N, DAGCombinerInfo &DCI) const {
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if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
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return Value;
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if (N->getValueType(0).isVector())
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return combineVectorShift(N, DCI);
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return SDValue();
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}
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@ -1441,7 +1441,7 @@ namespace llvm {
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SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineVectorSHL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineVectorShift(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
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@ -252,23 +252,19 @@ define <4 x i32> @test7_v4i32(<4 x i32> %a) {
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test7_v4i32:
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; CHECK-DAG: vspltisw v[[REG2:[0-9]+]], -16
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; CHECK-DAG: vspltisw v[[REG3:[0-9]+]], 15
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; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v[[REG2]]
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; CHECK: xxleqv v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], v[[REG2]]
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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; CHECK-NEXT: vslw v[[REG3:[0-9]+]], v2, v[[REG1]]
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define <4 x i32> @test8_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test8_v4i32:
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; CHECK-DAG: vspltisw v[[REG2:[0-9]+]], -16
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; CHECK-DAG: vspltisw v[[REG3:[0-9]+]], 15
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; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v[[REG2]]
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; CHECK: xxleqv v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], v[[REG2]]
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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; CHECK-NEXT: vsubuwm v[[REG6:[0-9]+]], v[[REG5]], v2
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; CHECK-NEXT: vslw v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v2
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define <2 x i64> @test1_v2i64(<2 x i64> %a) {
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%tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1]
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@ -356,8 +352,7 @@ define <2 x i64> @test7_v2i64(<2 x i64> %a) {
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}
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; CHECK-LABEL: test7_v2i64:
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; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
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; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
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; CHECK: xxleqv v[[REG2:[0-9]+]], v[[REG1:[0-9]+]], v[[REG1]]
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; CHECK-NOT: vmul
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; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]
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@ -367,8 +362,7 @@ define <2 x i64> @test8_v2i64(<2 x i64> %a) {
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}
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; CHECK-LABEL: test8_v2i64:
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; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
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; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
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; CHECK: xxleqv v[[REG2:[0-9]+]], v[[REG1:[0-9]+]], v[[REG1]]
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; CHECK-NOT: vmul
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; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
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; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
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@ -7,13 +7,11 @@
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define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
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; CHECK-LABEL: poly2_lshift1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r6, r2, .LCPI0_0@toc@ha
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; CHECK-NEXT: ld r6, 0(r3)
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; CHECK-NEXT: li r4, 72
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; CHECK-NEXT: ld r5, 64(r3)
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; CHECK-NEXT: addi r6, r6, .LCPI0_0@toc@l
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; CHECK-NEXT: xxleqv v4, v4, v4
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; CHECK-NEXT: lxvd2x vs0, r3, r4
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; CHECK-NEXT: lxvd2x v4, 0, r6
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; CHECK-NEXT: ld r6, 0(r3)
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; CHECK-NEXT: sldi r7, r6, 1
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; CHECK-NEXT: rotldi r6, r6, 1
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; CHECK-NEXT: std r7, 0(r3)
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@ -35,11 +33,11 @@ define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
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; CHECK-NEXT: std r7, 32(r3)
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; CHECK-NEXT: ld r7, 40(r3)
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; CHECK-NEXT: rldimi r6, r7, 1, 0
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; CHECK-NEXT: xxswapd v2, vs0
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; CHECK-NEXT: mtfprd f0, r5
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; CHECK-NEXT: rotldi r7, r7, 1
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; CHECK-NEXT: std r6, 40(r3)
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; CHECK-NEXT: ld r6, 48(r3)
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; CHECK-NEXT: xxswapd v2, vs0
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; CHECK-NEXT: mtfprd f0, r5
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; CHECK-NEXT: rldimi r7, r6, 1, 0
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; CHECK-NEXT: rotldi r6, r6, 1
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; CHECK-NEXT: std r7, 48(r3)
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@ -188,12 +188,10 @@ define i32 @add_lshr_not(i32 %x) {
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define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_lshr_not_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l
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; CHECK-NEXT: xxleqv 35, 35, 35
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l
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; CHECK-NEXT: lxvd2x 35, 0, 3
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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@ -218,12 +216,10 @@ define i32 @sub_lshr_not(i32 %x) {
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define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: sub_lshr_not_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
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; CHECK-NEXT: xxleqv 35, 35, 35
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; CHECK-NEXT: vsrw 2, 2, 3
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; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
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; CHECK-NEXT: lxvd2x 35, 0, 3
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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@ -247,9 +243,7 @@ define i32 @sub_lshr(i32 %x, i32 %y) {
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define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: sub_lshr_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 4, -16
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; CHECK-NEXT: vspltisw 5, 15
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; CHECK-NEXT: vsubuwm 4, 5, 4
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; CHECK-NEXT: xxleqv 36, 36, 36
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; CHECK-NEXT: vsraw 2, 2, 4
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; CHECK-NEXT: vadduwm 2, 3, 2
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; CHECK-NEXT: blr
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@ -272,12 +266,10 @@ define i32 @sub_const_op_lshr(i32 %x) {
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define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
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; CHECK-LABEL: sub_const_op_lshr_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
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; CHECK-NEXT: xxleqv 35, 35, 35
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
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; CHECK-NEXT: lxvd2x 35, 0, 3
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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@ -11,19 +11,17 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_C1_or_C2_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: xxleqv 37, 37, 37
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; CHECK-NEXT: vslw 2, 2, 5
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vsraw 2, 2, 5
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxswapd 37, 0
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 32, 0
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; CHECK-NEXT: xxsel 34, 32, 37, 34
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; CHECK-NEXT: xxswapd 36, 0
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; CHECK-NEXT: xxsel 34, 36, 35, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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@ -82,15 +80,13 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_Cminus1_or_C_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: xxleqv 36, 36, 36
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; CHECK-NEXT: vslw 2, 2, 4
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; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vsraw 2, 2, 4
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxswapd 37, 0
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; CHECK-NEXT: vadduwm 2, 2, 5
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
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ret <4 x i32> %add
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@ -114,9 +110,7 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_minus1_or_0_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: xxleqv 35, 35, 35
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: blr
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