[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)
This patch replaces use of MachineRegisterInfo's liveIn check with the machine basicBlock's liveIn. As the MRI's liveIn is inconsistent with the entry MBB liveIns, when it comes to the machine verifier checks. PS: Its an alternative solution with respect to #126926.
This commit is contained in:
Vikash Gupta
GitHub
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0813c5cf5f
commit
bdb63208b4
@ -101,6 +101,16 @@ INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
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char &llvm::SILowerSGPRSpillsLegacyID = SILowerSGPRSpillsLegacy::ID;
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static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
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const TargetRegisterInfo *TRI) {
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for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
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if (MBB.isLiveIn(*R)) {
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return true;
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}
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}
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return false;
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}
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/// Insert spill code for the callee-saved registers used in the function.
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static void insertCSRSaves(MachineBasicBlock &SaveBlock,
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ArrayRef<CalleeSavedInfo> CSI, SlotIndexes *Indexes,
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@ -114,8 +124,6 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
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MachineBasicBlock::iterator I = SaveBlock.begin();
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if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (const CalleeSavedInfo &CS : CSI) {
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// Insert the spill to the stack frame.
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MCRegister Reg = CS.getReg();
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@ -128,7 +136,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
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// incoming register value, so don't kill at the spill point. This happens
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// since we pass some special inputs (workgroup IDs) in the callee saved
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// range.
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const bool IsLiveIn = MRI.isLiveIn(Reg);
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const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI);
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TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
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RC, TRI, Register());
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@ -1,25 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills %s -o /dev/null 2>&1 | FileCheck -check-prefix=VERIFIER %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
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# FIXME : Currently, MRI's liveIn check for registers does not take the corresponding live-in's sub-registers into account. As a result
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# in SILowerSGPRSpills, the SubReg spill gets marked KILLED even though its SuperReg is in the function Live-ins. This causes machine
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# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
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# VERIFIER: After SI lower SGPR spill instructions
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# VERIFIER: *** Bad machine code: Using an undefined physical register ***
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# VERIFIER: - instruction: S_NOP 0, implicit $sgpr50
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# VERIFIER-NEXT: - operand 1: implicit $sgpr50
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# VERIFIER: *** Bad machine code: Using an undefined physical register ***
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# VERIFIER: - instruction: S_NOP 0, implicit $sgpr52
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# VERIFIER-NEXT: - operand 1: implicit $sgpr52
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# VERIFIER: *** Bad machine code: Using an undefined physical register ***
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# VERIFIER: - instruction: S_NOP 0, implicit $sgpr55
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# VERIFIER-NEXT: - operand 1: implicit $sgpr55
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# VERIFIER: LLVM ERROR: Found 3 machine code errors.
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---
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name: spill_partial_live_csr_sgpr_test
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tracksRegLiveness: true
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@ -31,6 +12,21 @@ body: |
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bb.0:
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liveins: $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
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; CHECK-LABEL: name: spill_partial_live_csr_sgpr_test
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; CHECK: liveins: $sgpr50, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr63, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63
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; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr52, 1, $vgpr63
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; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr53, 2, $vgpr63
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; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr54, 3, $vgpr63
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; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr55, 4, $vgpr63
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; CHECK-NEXT: S_NOP 0, implicit $sgpr50
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; CHECK-NEXT: $sgpr50 = S_MOV_B32 0
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; CHECK-NEXT: S_NOP 0, implicit $sgpr52
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; CHECK-NEXT: $sgpr52_sgpr53 = S_MOV_B64 0
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; CHECK-NEXT: S_NOP 0, implicit $sgpr55
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; CHECK-NEXT: $sgpr54_sgpr55 = S_MOV_B64 0
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; CHECK-NEXT: $sgpr56 = S_MOV_B32 0
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S_NOP 0, implicit $sgpr50
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$sgpr50 = S_MOV_B32 0
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S_NOP 0, implicit $sgpr52
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@ -55,22 +55,22 @@ body: |
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; GCN-LABEL: name: sgpr_spill_lane_crossover
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; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr64, 0, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr65, 1, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr66, 2, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr67, 3, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr68, 4, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr69, 5, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr70, 6, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr71, 7, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr80, 8, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr81, 9, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr82, 10, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr83, 11, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr84, 12, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr85, 13, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr86, 14, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr87, 15, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr67, 3, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr68, 4, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr69, 5, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr70, 6, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr71, 7, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr80, 8, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr81, 9, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr82, 10, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr83, 11, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr84, 12, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr85, 13, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr86, 14, $vgpr63
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; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr87, 15, $vgpr63
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
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