[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
If we only deal with a one part of 64bit value we can just generate merge and unmerge which will be either combined away or selected into copy / mov_b32.
This commit is contained in:
Mirko Brkušanin
GitHub
parent
9824930744
commit
bdec5bf69c
@ -176,6 +176,19 @@ def binop_s64_with_s32_mask_combines : GICombineGroup<[
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combine_or_s64_with_s32_mask, combine_and_s64_with_s32_mask
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]>;
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// (or i64:x, (zext i32:y)) -> i64:(merge (or lo_32(x), i32:y), hi_32(x))
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// (or (zext i32:y), i64:x) -> i64:(merge (or lo_32(x), i32:y), hi_32(x))
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def or_s64_zext_s32_frag : GICombinePatFrag<(outs root:$dst), (ins $src_s64, $src_s32),
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[(pattern (G_OR $dst, i64:$src_s64, i64:$zext_val), (G_ZEXT i64:$zext_val, i32:$src_s32)),
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(pattern (G_OR $dst, i64:$zext_val, i64:$src_s64), (G_ZEXT i64:$zext_val, i32:$src_s32))]>;
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def combine_or_s64_s32 : GICombineRule<
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(defs root:$dst),
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(match (or_s64_zext_s32_frag $dst, i64:$x, i32:$y):$dst),
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(apply (G_UNMERGE_VALUES $x_lo, $x_hi, $x),
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(G_OR $or, $x_lo, $y),
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(G_MERGE_VALUES $dst, $or, $x_hi))>;
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let Predicates = [Has16BitInsts, NotHasMed3_16] in {
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// For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
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// saves one instruction compared to the promotion.
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@ -206,7 +219,7 @@ def AMDGPUPreLegalizerCombiner: GICombiner<
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"AMDGPUPreLegalizerCombinerImpl",
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[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
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foldable_fneg, combine_shuffle_vector_to_build_vector,
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binop_s64_with_s32_mask_combines]> {
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binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
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let CombineAllMethodName = "tryCombineAllImpl";
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}
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@ -215,7 +228,7 @@ def AMDGPUPostLegalizerCombiner: GICombiner<
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[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
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uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
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rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
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binop_s64_with_s32_mask_combines]> {
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binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
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let CombineAllMethodName = "tryCombineAllImpl";
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}
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@ -1778,7 +1778,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
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; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 31
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; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
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; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
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; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v2
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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@ -1790,7 +1790,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
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; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
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; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
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; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
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; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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@ -1802,7 +1802,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
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; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
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; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
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; GFX9-NEXT: v_or_b32_e32 v0, v0, v3
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; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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@ -1815,7 +1815,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
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; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
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; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2
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; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0
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; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v3
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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%result = ashr i65 %value, 33
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ret i65 %result
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@ -1875,21 +1875,19 @@ define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
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; GCN-LABEL: s_ashr_i65_33:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
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; GCN-NEXT: s_lshr_b32 s0, s1, 1
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; GCN-NEXT: s_mov_b32 s1, 0
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; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
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; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
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; GCN-NEXT: s_lshr_b32 s4, s1, 1
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; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
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; GCN-NEXT: s_or_b32 s0, s0, s4
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; GCN-NEXT: s_ashr_i32 s2, s3, 1
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; GCN-NEXT: ; return to shader part epilog
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;
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; GFX10PLUS-LABEL: s_ashr_i65_33:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
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; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1
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; GFX10PLUS-NEXT: s_mov_b32 s1, 0
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; GFX10PLUS-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
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; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
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; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
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; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
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; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
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; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
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; GFX10PLUS-NEXT: ; return to shader part epilog
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%result = ashr i65 %value, 33
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ret i65 %result
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97
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
Normal file
97
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
Normal file
@ -0,0 +1,97 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s
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---
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name: test_combine_or_s64_s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2
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; CHECK-LABEL: name: test_combine_or_s64_s32
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
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; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
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; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s64) = G_ZEXT %1(s32)
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%3:_(s64) = G_OR %0, %2
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$sgpr0_sgpr1 = COPY %3(s64)
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SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
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...
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---
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name: test_combine_or_s64_s32_rhs
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2
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; CHECK-LABEL: name: test_combine_or_s64_s32_rhs
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
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; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
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; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s64) = G_ZEXT %1(s32)
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%3:_(s64) = G_OR %2, %0
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$sgpr0_sgpr1 = COPY %3(s64)
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SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
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...
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---
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name: test_combine_or_s64_s32_merge_unmerge
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-LABEL: name: test_combine_or_s64_s32_merge_unmerge
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; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY2]]
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; CHECK-NEXT: $sgpr0 = COPY [[OR]](s32)
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; CHECK-NEXT: $sgpr1 = COPY [[COPY1]](s32)
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; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
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%4:_(s64) = G_ZEXT %2(s32)
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%5:_(s64) = G_OR %3, %4
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%6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %5(s64)
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$sgpr0 = COPY %6(s32)
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$sgpr1 = COPY %7(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
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...
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---
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name: negative_test_incorrect_types
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
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; CHECK-LABEL: name: negative_test_incorrect_types
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s128) = G_ZEXT [[COPY1]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s128) = G_OR [[COPY]], [[ZEXT]]
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; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[OR]](s128)
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%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s64) = COPY $vgpr4_vgpr5
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%2:_(s128) = G_ZEXT %1
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%3:_(s128) = G_OR %0, %2
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
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...
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@ -227,39 +227,38 @@ exit:
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define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3 x i32> inreg %.WorkgroupId, <3 x i32> %.LocalInvocationId) #0 {
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; GFX10-LABEL: single_lane_execution_attribute:
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; GFX10: ; %bb.0: ; %.entry
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; GFX10-NEXT: s_getpc_b64 s[12:13]
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; GFX10-NEXT: s_mov_b32 s12, 0
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; GFX10-NEXT: s_getpc_b64 s[4:5]
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; GFX10-NEXT: s_mov_b32 s2, s0
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; GFX10-NEXT: s_mov_b32 s3, s12
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; GFX10-NEXT: s_mov_b32 s3, s5
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; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0
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; GFX10-NEXT: s_or_b64 s[2:3], s[12:13], s[2:3]
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; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
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; GFX10-NEXT: v_mbcnt_hi_u32_b32 v1, -1, v1
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; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v1
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; GFX10-NEXT: v_and_b32_e32 v3, 1, v1
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; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
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; GFX10-NEXT: s_xor_b32 s2, vcc_lo, exec_lo
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; GFX10-NEXT: s_and_b32 vcc_lo, s2, exec_lo
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: buffer_load_dword v2, v2, s[4:7], 0 offen
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; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
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; GFX10-NEXT: s_mov_b32 s2, 0
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v2
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; GFX10-NEXT: s_cbranch_vccnz .LBB4_4
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; GFX10-NEXT: ; %bb.1: ; %.preheader.preheader
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; GFX10-NEXT: s_mov_b32 s2, 0
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; GFX10-NEXT: s_mov_b32 s3, 0
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; GFX10-NEXT: .LBB4_2: ; %.preheader
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: v_mov_b32_e32 v3, s12
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; GFX10-NEXT: v_mov_b32_e32 v3, s2
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; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1
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; GFX10-NEXT: s_add_i32 s12, s12, 4
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; GFX10-NEXT: s_add_i32 s2, s2, 4
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; GFX10-NEXT: buffer_load_dword v3, v3, s[4:7], 0 offen
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; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_readfirstlane_b32 s3, v3
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; GFX10-NEXT: s_add_i32 s2, s3, s2
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; GFX10-NEXT: v_readfirstlane_b32 s12, v3
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; GFX10-NEXT: s_add_i32 s3, s12, s3
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; GFX10-NEXT: s_cbranch_vccnz .LBB4_2
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; GFX10-NEXT: ; %bb.3: ; %.preheader._crit_edge
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; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v2
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; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s3, v2
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; GFX10-NEXT: s_or_b32 s2, s0, vcc_lo
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; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
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; GFX10-NEXT: s_branch .LBB4_6
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@ -4934,17 +4934,15 @@ define amdgpu_ps i64 @s_fshl_i64_5(i64 inreg %lhs, i64 inreg %rhs) {
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; GCN: ; %bb.0:
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; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 5
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; GCN-NEXT: s_lshr_b32 s2, s3, 27
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; GCN-NEXT: s_mov_b32 s3, 0
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; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: s_or_b32 s0, s0, s2
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; GCN-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: s_fshl_i64_5:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 5
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; GFX11-NEXT: s_lshr_b32 s2, s3, 27
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; GFX11-NEXT: s_mov_b32 s3, 0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
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; GFX11-NEXT: s_or_b32 s0, s0, s2
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; GFX11-NEXT: ; return to shader part epilog
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%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 5)
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ret i64 %result
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@ -4954,20 +4952,13 @@ define amdgpu_ps i64 @s_fshl_i64_32(i64 inreg %lhs, i64 inreg %rhs) {
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; GCN-LABEL: s_fshl_i64_32:
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; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_mov_b32 s1, s0
|
||||
; GCN-NEXT: s_mov_b32 s0, 0
|
||||
; GCN-NEXT: s_mov_b32 s2, s3
|
||||
; GCN-NEXT: s_mov_b32 s3, s0
|
||||
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GCN-NEXT: s_mov_b32 s0, s3
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-LABEL: s_fshl_i64_32:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: s_mov_b32 s1, s0
|
||||
; GFX11-NEXT: s_mov_b32 s0, 0
|
||||
; GFX11-NEXT: s_mov_b32 s2, s3
|
||||
; GFX11-NEXT: s_mov_b32 s3, s0
|
||||
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GFX11-NEXT: s_mov_b32 s0, s3
|
||||
; GFX11-NEXT: ; return to shader part epilog
|
||||
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 32)
|
||||
ret i64 %result
|
||||
@ -6823,56 +6814,50 @@ define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
|
||||
; GFX6-NEXT: s_lshr_b32 s4, s5, 31
|
||||
; GFX6-NEXT: s_mov_b32 s5, 0
|
||||
; GFX6-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
|
||||
; GFX6-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
|
||||
; GFX6-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX6-NEXT: s_lshr_b32 s4, s7, 31
|
||||
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GFX6-NEXT: s_or_b32 s2, s2, s4
|
||||
; GFX6-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-LABEL: s_fshl_i128_65:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
|
||||
; GFX8-NEXT: s_lshr_b32 s4, s5, 31
|
||||
; GFX8-NEXT: s_mov_b32 s5, 0
|
||||
; GFX8-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
|
||||
; GFX8-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
|
||||
; GFX8-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX8-NEXT: s_lshr_b32 s4, s7, 31
|
||||
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GFX8-NEXT: s_or_b32 s2, s2, s4
|
||||
; GFX8-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: s_fshl_i128_65:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
|
||||
; GFX9-NEXT: s_lshr_b32 s4, s5, 31
|
||||
; GFX9-NEXT: s_mov_b32 s5, 0
|
||||
; GFX9-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
|
||||
; GFX9-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
|
||||
; GFX9-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX9-NEXT: s_lshr_b32 s4, s7, 31
|
||||
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GFX9-NEXT: s_or_b32 s2, s2, s4
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: s_fshl_i128_65:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_lshr_b32 s2, s5, 31
|
||||
; GFX10-NEXT: s_mov_b32 s3, 0
|
||||
; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
|
||||
; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
|
||||
; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
|
||||
; GFX10-NEXT: s_lshr_b32 s2, s7, 31
|
||||
; GFX10-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
|
||||
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
|
||||
; GFX10-NEXT: s_lshr_b32 s4, s5, 31
|
||||
; GFX10-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
|
||||
; GFX10-NEXT: s_lshr_b32 s5, s7, 31
|
||||
; GFX10-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX10-NEXT: s_or_b32 s2, s2, s5
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-LABEL: s_fshl_i128_65:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: s_lshr_b32 s2, s5, 31
|
||||
; GFX11-NEXT: s_mov_b32 s3, 0
|
||||
; GFX11-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
|
||||
; GFX11-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
|
||||
; GFX11-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
|
||||
; GFX11-NEXT: s_lshr_b32 s2, s7, 31
|
||||
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
|
||||
; GFX11-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
|
||||
; GFX11-NEXT: s_lshr_b32 s4, s5, 31
|
||||
; GFX11-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
|
||||
; GFX11-NEXT: s_lshr_b32 s5, s7, 31
|
||||
; GFX11-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX11-NEXT: s_or_b32 s2, s2, s5
|
||||
; GFX11-NEXT: ; return to shader part epilog
|
||||
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
|
||||
ret i128 %result
|
||||
@ -6885,7 +6870,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
|
||||
; GFX6-NEXT: v_lshl_b64 v[2:3], v[0:1], 1
|
||||
; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], 1
|
||||
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v5
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v7
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
@ -6896,7 +6881,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
|
||||
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
|
||||
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
|
||||
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v5
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v7
|
||||
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
@ -6907,7 +6892,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
|
||||
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
|
||||
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
|
||||
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v5
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v7
|
||||
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
@ -6919,7 +6904,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
|
||||
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
|
||||
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v5
|
||||
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v7
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -6931,7 +6916,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v5
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 31, v7
|
||||
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
||||
; GFX11-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
; GFX11-NEXT: v_or_b32_e32 v2, v2, v5
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1750,7 +1750,7 @@ define i65 @v_lshr_i65_33(i65 %value) {
|
||||
; GFX6-NEXT: v_and_b32_e32 v0, 1, v2
|
||||
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31
|
||||
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v3
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1763,7 +1763,7 @@ define i65 @v_lshr_i65_33(i65 %value) {
|
||||
; GFX8-NEXT: v_and_b32_e32 v0, 1, v2
|
||||
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
|
||||
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v3
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1776,7 +1776,7 @@ define i65 @v_lshr_i65_33(i65 %value) {
|
||||
; GFX9-NEXT: v_and_b32_e32 v0, 1, v2
|
||||
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
|
||||
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v3
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1789,7 +1789,7 @@ define i65 @v_lshr_i65_33(i65 %value) {
|
||||
; GFX10-NEXT: v_and_b32_e32 v0, 1, v2
|
||||
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v3
|
||||
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1800,7 +1800,7 @@ define i65 @v_lshr_i65_33(i65 %value) {
|
||||
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 1, v2
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 1, v3
|
||||
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
|
||||
; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
%result = lshr i65 %value, 33
|
||||
@ -1859,21 +1859,19 @@ define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) {
|
||||
; GCN-LABEL: s_lshr_i65_33:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1
|
||||
; GCN-NEXT: s_lshr_b32 s0, s1, 1
|
||||
; GCN-NEXT: s_mov_b32 s1, 0
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 31
|
||||
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GCN-NEXT: s_lshr_b32 s4, s1, 1
|
||||
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
|
||||
; GCN-NEXT: s_or_b32 s0, s0, s4
|
||||
; GCN-NEXT: s_mov_b32 s2, 0
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10PLUS-LABEL: s_lshr_i65_33:
|
||||
; GFX10PLUS: ; %bb.0:
|
||||
; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], 1
|
||||
; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s1, 0
|
||||
; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], 31
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
|
||||
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s2, 0
|
||||
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX10PLUS-NEXT: ; return to shader part epilog
|
||||
%result = lshr i65 %value, 33
|
||||
ret i65 %result
|
||||
|
||||
@ -597,13 +597,13 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
||||
; GFX7-NEXT: s_mov_b32 s5, 0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_load_dword s4, s[2:3], 0x0
|
||||
; GFX7-NEXT: s_load_dword s3, s[2:3], 0x0
|
||||
; GFX7-NEXT: s_mov_b32 s2, -1
|
||||
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_or_b64 s[4:5], s[4:5], 0x50
|
||||
; GFX7-NEXT: s_or_b32 s4, s3, 0x50
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
@ -616,7 +616,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
|
||||
; GFX8-NEXT: s_mov_b32 s3, 0
|
||||
; GFX8-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], 0x50
|
||||
; GFX8-NEXT: s_or_b32 s2, s2, 0x50
|
||||
; GFX8-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
||||
@ -630,7 +630,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
|
||||
; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
|
||||
; GFX9-NEXT: s_mov_b32 s3, 0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], 0x50
|
||||
; GFX9-NEXT: s_or_b32 s2, s2, 0x50
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
||||
@ -644,7 +644,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
|
||||
; GFX10-NEXT: s_load_dword s2, s[2:3], 0x0
|
||||
; GFX10-NEXT: s_mov_b32 s3, 0
|
||||
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], 0x50
|
||||
; GFX10-NEXT: s_or_b32 s2, s2, 0x50
|
||||
; GFX10-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
||||
@ -658,7 +658,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
|
||||
; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
|
||||
; GFX11-NEXT: s_mov_b32 s3, 0
|
||||
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], 0x50
|
||||
; GFX11-NEXT: s_or_b32 s2, s2, 0x50
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
||||
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
; GFX11-NEXT: s_endpgm
|
||||
@ -671,7 +671,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
|
||||
; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0
|
||||
; GFX12-NEXT: s_mov_b32 s3, 0
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: s_or_b64 s[2:3], s[2:3], 0x50
|
||||
; GFX12-NEXT: s_or_b32 s2, s2, 0x50
|
||||
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
||||
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
||||
|
||||
@ -1381,7 +1381,7 @@ define i65 @v_sext_inreg_i65_33(i65 %value) {
|
||||
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
|
||||
; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 31
|
||||
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
|
||||
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v2
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1393,7 +1393,7 @@ define i65 @v_sext_inreg_i65_33(i65 %value) {
|
||||
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
|
||||
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
|
||||
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v3
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
|
||||
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v2
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1405,7 +1405,7 @@ define i65 @v_sext_inreg_i65_33(i65 %value) {
|
||||
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
|
||||
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
|
||||
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v0, v3
|
||||
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -1418,7 +1418,7 @@ define i65 @v_sext_inreg_i65_33(i65 %value) {
|
||||
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1
|
||||
; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
|
||||
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2
|
||||
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v3
|
||||
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
|
||||
%shl = shl i65 %value, 33
|
||||
%ashr = ashr i65 %value, 33
|
||||
@ -1429,29 +1429,27 @@ define amdgpu_ps i65 @s_sext_inreg_i65_18(i65 inreg %value) {
|
||||
; GCN-LABEL: s_sext_inreg_i65_18:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 18
|
||||
; GCN-NEXT: s_lshr_b32 s4, s1, 14
|
||||
; GCN-NEXT: s_mov_b32 s5, 0
|
||||
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GCN-NEXT: s_lshr_b32 s3, s1, 14
|
||||
; GCN-NEXT: s_or_b32 s2, s2, s3
|
||||
; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
|
||||
; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0x2e0000
|
||||
; GCN-NEXT: s_lshl_b32 s7, s2, 14
|
||||
; GCN-NEXT: s_mov_b32 s6, s5
|
||||
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
|
||||
; GCN-NEXT: s_lshl_b32 s5, s2, 14
|
||||
; GCN-NEXT: s_mov_b32 s4, 0
|
||||
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
|
||||
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 18
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10PLUS-LABEL: s_sext_inreg_i65_18:
|
||||
; GFX10PLUS: ; %bb.0:
|
||||
; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], 18
|
||||
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 14
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s5, 0
|
||||
; GFX10PLUS-NEXT: s_lshr_b32 s3, s1, 14
|
||||
; GFX10PLUS-NEXT: s_bfe_u64 s[0:1], s[0:1], 0x2e0000
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s6, s5
|
||||
; GFX10PLUS-NEXT: s_or_b32 s2, s2, s3
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s4, 0
|
||||
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
|
||||
; GFX10PLUS-NEXT: s_lshl_b32 s7, s2, 14
|
||||
; GFX10PLUS-NEXT: s_lshl_b32 s5, s2, 14
|
||||
; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], 18
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
|
||||
; GFX10PLUS-NEXT: ; return to shader part epilog
|
||||
%shl = shl i65 %value, 18
|
||||
%ashr = ashr i65 %shl, 18
|
||||
@ -1464,13 +1462,12 @@ define amdgpu_ps i65 @s_sext_inreg_i65_33(i65 inreg %value) {
|
||||
; GCN-NEXT: s_lshl_b32 s3, s2, 1
|
||||
; GCN-NEXT: s_mov_b32 s2, 0
|
||||
; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], 31
|
||||
; GCN-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]
|
||||
; GCN-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
|
||||
; GCN-NEXT: s_bfe_u32 s0, s0, 0x1f0000
|
||||
; GCN-NEXT: s_mov_b32 s1, s2
|
||||
; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], 31
|
||||
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GCN-NEXT: s_ashr_i32 s2, s5, 1
|
||||
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
|
||||
; GCN-NEXT: s_bfe_u32 s4, s0, 0x1f0000
|
||||
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
|
||||
; GCN-NEXT: s_or_b32 s0, s0, s4
|
||||
; GCN-NEXT: s_ashr_i32 s2, s3, 1
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10PLUS-LABEL: s_sext_inreg_i65_33:
|
||||
@ -1478,13 +1475,12 @@ define amdgpu_ps i65 @s_sext_inreg_i65_33(i65 inreg %value) {
|
||||
; GFX10PLUS-NEXT: s_lshl_b32 s3, s2, 1
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s2, 0
|
||||
; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[0:1], 31
|
||||
; GFX10PLUS-NEXT: s_bfe_u32 s0, s0, 0x1f0000
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]
|
||||
; GFX10PLUS-NEXT: s_mov_b32 s1, s2
|
||||
; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
|
||||
; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[4:5], 31
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
||||
; GFX10PLUS-NEXT: s_ashr_i32 s2, s5, 1
|
||||
; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
|
||||
; GFX10PLUS-NEXT: s_bfe_u32 s4, s0, 0x1f0000
|
||||
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
|
||||
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
|
||||
; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
|
||||
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
|
||||
; GFX10PLUS-NEXT: ; return to shader part epilog
|
||||
%shl = shl i65 %value, 33
|
||||
%ashr = ashr i65 %shl, 33
|
||||
|
||||
@ -415,28 +415,18 @@ define amdgpu_kernel void @memcpy_known(ptr addrspace(7) %src, ptr addrspace(7)
|
||||
; GISEL-GFX942-LABEL: memcpy_known:
|
||||
; GISEL-GFX942: ; %bb.0:
|
||||
; GISEL-GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
||||
; GISEL-GFX942-NEXT: s_load_dword s7, s[4:5], 0x54
|
||||
; GISEL-GFX942-NEXT: s_load_dword s11, s[4:5], 0x34
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s7, 0
|
||||
; GISEL-GFX942-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x44
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s8, s7
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX942-NEXT: s_load_dword s3, s[4:5], 0x54
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s10, s7
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s13
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s4, s7
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s5, s14
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s16, 0
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s15
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s2, s7
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
|
||||
; GISEL-GFX942-NEXT: v_mov_b32_e32 v0, 0x2000
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s8, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s10, s3
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s4, s13
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s5, s14
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s15
|
||||
; GISEL-GFX942-NEXT: v_mov_b32_e32 v1, s16
|
||||
; GISEL-GFX942-NEXT: .LBB0_1: ; %load-store-loop
|
||||
; GISEL-GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
@ -491,25 +481,16 @@ define amdgpu_kernel void @memcpy_known(ptr addrspace(7) %src, ptr addrspace(7)
|
||||
; GISEL-GFX1100-NEXT: s_load_b128 s[8:11], s[4:5], 0x44
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s7, s[4:5], 0x34
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s15, s[4:5], 0x54
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s17, 0
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, 0
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s17
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s6, s17
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, s12
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s14, s17
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, 0
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GISEL-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s5, s2
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s2, s17
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s3
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s3, s10
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[6:7], s[16:17], s[6:7]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s9
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[12:13], s[16:17], s[2:3]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s11
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[14:15], s[16:17], s[14:15]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, s9
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s13, s10
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s14, s11
|
||||
; GISEL-GFX1100-NEXT: .LBB0_1: ; %load-store-loop
|
||||
; GISEL-GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v61, s0, v0
|
||||
@ -960,28 +941,18 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) %src, ptr addrsp
|
||||
; GISEL-GFX942-LABEL: memcpy_known_medium:
|
||||
; GISEL-GFX942: ; %bb.0:
|
||||
; GISEL-GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
||||
; GISEL-GFX942-NEXT: s_load_dword s7, s[4:5], 0x54
|
||||
; GISEL-GFX942-NEXT: s_load_dword s11, s[4:5], 0x34
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s7, 0
|
||||
; GISEL-GFX942-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x44
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s8, s7
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX942-NEXT: s_load_dword s3, s[4:5], 0x54
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s10, s7
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s13
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s4, s7
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s5, s14
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s16, 0
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s15
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s2, s7
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
|
||||
; GISEL-GFX942-NEXT: v_mov_b32_e32 v0, 0x100
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s8, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s10, s3
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s4, s13
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s5, s14
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s15
|
||||
; GISEL-GFX942-NEXT: v_mov_b32_e32 v1, s16
|
||||
; GISEL-GFX942-NEXT: .LBB1_1: ; %load-store-loop
|
||||
; GISEL-GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
@ -1036,25 +1007,16 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) %src, ptr addrsp
|
||||
; GISEL-GFX1100-NEXT: s_load_b128 s[8:11], s[4:5], 0x44
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s7, s[4:5], 0x34
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s15, s[4:5], 0x54
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s17, 0
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, 0
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s17
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s6, s17
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, s12
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s14, s17
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, 0
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GISEL-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s5, s2
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s2, s17
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s3
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s3, s10
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[6:7], s[16:17], s[6:7]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s9
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[12:13], s[16:17], s[2:3]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s16, s11
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[14:15], s[16:17], s[14:15]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, s9
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s13, s10
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s14, s11
|
||||
; GISEL-GFX1100-NEXT: .LBB1_1: ; %load-store-loop
|
||||
; GISEL-GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v61, s0, v0
|
||||
@ -1228,27 +1190,18 @@ define amdgpu_kernel void @memcpy_known_small(ptr addrspace(7) %src, ptr addrspa
|
||||
; GISEL-GFX942: ; %bb.0:
|
||||
; GISEL-GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
||||
; GISEL-GFX942-NEXT: s_load_dword s11, s[4:5], 0x34
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s7, 0
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s8, s7
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s10, s7
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s8, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s10, s3
|
||||
; GISEL-GFX942-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[0:3], v4, s[8:11], 0 offen
|
||||
; GISEL-GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x44
|
||||
; GISEL-GFX942-NEXT: s_load_dword s13, s[4:5], 0x54
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s4, s7
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s12, s7
|
||||
; GISEL-GFX942-NEXT: s_load_dword s7, s[4:5], 0x54
|
||||
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s4, s1
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s5, s2
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GISEL-GFX942-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX942-NEXT: s_or_b64 s[6:7], s[6:7], s[12:13]
|
||||
; GISEL-GFX942-NEXT: v_mov_b32_e32 v5, s0
|
||||
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(0)
|
||||
; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[0:3], v5, s[4:7], 0 offen
|
||||
@ -1261,35 +1214,24 @@ define amdgpu_kernel void @memcpy_known_small(ptr addrspace(7) %src, ptr addrspa
|
||||
; GISEL-GFX1100: ; %bb.0:
|
||||
; GISEL-GFX1100-NEXT: s_clause 0x1
|
||||
; GISEL-GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s7, s[4:5], 0x34
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s13, 0
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s8, s13
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s6, s13
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s11, s[4:5], 0x34
|
||||
; GISEL-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[0:1], s[12:13], s[8:9]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, s3
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[2:3], s[12:13], s[6:7]
|
||||
; GISEL-GFX1100-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s8, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s9, s2
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s10, s3
|
||||
; GISEL-GFX1100-NEXT: buffer_load_b128 v[0:3], v4, s[8:11], 0 offen
|
||||
; GISEL-GFX1100-NEXT: s_clause 0x1
|
||||
; GISEL-GFX1100-NEXT: s_load_b128 s[8:11], s[4:5], 0x44
|
||||
; GISEL-GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x44
|
||||
; GISEL-GFX1100-NEXT: s_load_b32 s7, s[4:5], 0x54
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s13
|
||||
; GISEL-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, s9
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s5, s10
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v5, s8
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5]
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s12, s11
|
||||
; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GISEL-GFX1100-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
|
||||
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v5, s0
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s1
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s5, s2
|
||||
; GISEL-GFX1100-NEXT: s_mov_b32 s6, s3
|
||||
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0)
|
||||
; GISEL-GFX1100-NEXT: buffer_store_b128 v[0:3], v5, s[4:7], 0 offen
|
||||
; GISEL-GFX1100-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:16
|
||||
; GISEL-GFX1100-NEXT: buffer_load_b128 v[0:3], v4, s[8:11], 0 offen offset:16
|
||||
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0)
|
||||
; GISEL-GFX1100-NEXT: buffer_store_b128 v[0:3], v5, s[4:7], 0 offen offset:16
|
||||
; GISEL-GFX1100-NEXT: s_endpgm
|
||||
|
||||
@ -4344,7 +4344,7 @@ define i128 @v_sdiv_i128_v_pow2k(i128 %lhs) {
|
||||
; GFX9-G-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
|
||||
; GFX9-G-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
|
||||
; GFX9-G-NEXT: v_lshrrev_b32_e32 v3, 1, v4
|
||||
; GFX9-G-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX9-G-NEXT: v_or_b32_e32 v0, v0, v3
|
||||
; GFX9-G-NEXT: v_ashrrev_i32_e32 v3, 31, v2
|
||||
; GFX9-G-NEXT: v_ashrrev_i32_e32 v2, 1, v2
|
||||
; GFX9-G-NEXT: s_setpc_b64 s[30:31]
|
||||
@ -4375,14 +4375,12 @@ define i128 @v_sdiv_i128_v_pow2k(i128 %lhs) {
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v4
|
||||
; GFX9-G-O0-NEXT: s_mov_b32 s5, 1
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s5
|
||||
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v0, v0, v1
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[5:6], v2, v[5:6]
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v5
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v3
|
||||
; GFX9-G-O0-NEXT: v_or_b32_e64 v1, v1, v2
|
||||
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v2, v0, v1
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[5:6], v0, v[5:6]
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v5
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v6
|
||||
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v2
|
||||
; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v3, v2, v4
|
||||
@ -4437,7 +4435,7 @@ define i128 @v_udiv_i128_v_pow2k(i128 %lhs) {
|
||||
; GFX9-G-NEXT: v_mov_b32_e32 v4, v1
|
||||
; GFX9-G-NEXT: v_lshlrev_b64 v[0:1], 31, v[2:3]
|
||||
; GFX9-G-NEXT: v_lshrrev_b32_e32 v2, 1, v4
|
||||
; GFX9-G-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX9-G-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX9-G-NEXT: v_lshrrev_b32_e32 v2, 1, v3
|
||||
; GFX9-G-NEXT: v_mov_b32_e32 v3, 0
|
||||
; GFX9-G-NEXT: s_setpc_b64 s[30:31]
|
||||
@ -4450,15 +4448,13 @@ define i128 @v_udiv_i128_v_pow2k(i128 %lhs) {
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v3
|
||||
; GFX9-G-O0-NEXT: s_mov_b32 s4, 1
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v0, v0, v1
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v2, v0, v1
|
||||
; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[5:6], v2, v[4:5]
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v5
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v4
|
||||
; GFX9-G-O0-NEXT: v_or_b32_e64 v1, v1, v2
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[4:5], v0, v[4:5]
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v2
|
||||
; GFX9-G-O0-NEXT: s_mov_b32 s4, 1
|
||||
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v2, v2, v3
|
||||
|
||||
@ -2080,21 +2080,13 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_or_i64_imm_offset_16(ptr addrs
|
||||
}
|
||||
|
||||
define amdgpu_ps float @flat_load_saddr_i8_offset_or_i64_imm_offset_4160(ptr addrspace(6) inreg %sbase, i32 %idx) {
|
||||
; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_or_i64_imm_offset_4160:
|
||||
; GFX1250-SDAG: ; %bb.0:
|
||||
; GFX1250-SDAG-NEXT: v_or_b32_e32 v0, 0x1040, v0
|
||||
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1]
|
||||
; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX1250-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_or_i64_imm_offset_4160:
|
||||
; GFX1250-GISEL: ; %bb.0:
|
||||
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX1250-GISEL-NEXT: v_or_b32_e32 v0, 0x1040, v0
|
||||
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
|
||||
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX1250-GISEL-NEXT: ; return to shader part epilog
|
||||
; GFX1250-LABEL: flat_load_saddr_i8_offset_or_i64_imm_offset_4160:
|
||||
; GFX1250: ; %bb.0:
|
||||
; GFX1250-NEXT: v_or_b32_e32 v0, 0x1040, v0
|
||||
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX1250-NEXT: flat_load_u8 v0, v[0:1]
|
||||
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX1250-NEXT: ; return to shader part epilog
|
||||
%zext.idx = zext i32 %idx to i64
|
||||
%or = or i64 %zext.idx, 4160
|
||||
%addr = inttoptr i64 %or to ptr
|
||||
|
||||
@ -4666,21 +4666,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_or_i64_imm_offset_16(ptr add
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_16:
|
||||
; GFX12-SDAG: ; %bb.0:
|
||||
; GFX12-SDAG-NEXT: v_or_b32_e32 v0, 16, v0
|
||||
; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX12-SDAG-NEXT: global_load_u8 v0, v[0:1], off
|
||||
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_16:
|
||||
; GFX12-GISEL: ; %bb.0:
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX12-GISEL-NEXT: v_or_b32_e32 v0, 16, v0
|
||||
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
|
||||
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-GISEL-NEXT: ; return to shader part epilog
|
||||
; GFX12-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_16:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: v_or_b32_e32 v0, 16, v0
|
||||
; GFX12-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX12-NEXT: global_load_u8 v0, v[0:1], off
|
||||
; GFX12-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-NEXT: ; return to shader part epilog
|
||||
%zext.idx = zext i32 %idx to i64
|
||||
%or = or i64 %zext.idx, 16
|
||||
%addr = inttoptr i64 %or to ptr addrspace(1)
|
||||
@ -4707,21 +4699,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_or_i64_imm_offset_4160(ptr a
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_4160:
|
||||
; GFX12-SDAG: ; %bb.0:
|
||||
; GFX12-SDAG-NEXT: v_or_b32_e32 v0, 0x1040, v0
|
||||
; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX12-SDAG-NEXT: global_load_u8 v0, v[0:1], off
|
||||
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_4160:
|
||||
; GFX12-GISEL: ; %bb.0:
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX12-GISEL-NEXT: v_or_b32_e32 v0, 0x1040, v0
|
||||
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
|
||||
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-GISEL-NEXT: ; return to shader part epilog
|
||||
; GFX12-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_4160:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: v_or_b32_e32 v0, 0x1040, v0
|
||||
; GFX12-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX12-NEXT: global_load_u8 v0, v[0:1], off
|
||||
; GFX12-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-NEXT: ; return to shader part epilog
|
||||
%zext.idx = zext i32 %idx to i64
|
||||
%or = or i64 %zext.idx, 4160
|
||||
%addr = inttoptr i64 %or to ptr addrspace(1)
|
||||
|
||||
@ -1066,13 +1066,13 @@ define double @uitofp_i128_to_f64(i128 %x) {
|
||||
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[8:9], 30, v[2:3]
|
||||
; GISEL-NEXT: v_lshrrev_b32_e32 v5, 2, v1
|
||||
; GISEL-NEXT: v_or_b32_e32 v9, v5, v8
|
||||
; GISEL-NEXT: v_or_b32_e32 v9, v8, v5
|
||||
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; GISEL-NEXT: ; %bb.11: ; %itofp-if-then20
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[2:3], 29, v[2:3]
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[4:5], 3, v[0:1]
|
||||
; GISEL-NEXT: v_lshrrev_b32_e32 v0, 3, v1
|
||||
; GISEL-NEXT: v_or_b32_e32 v9, v0, v2
|
||||
; GISEL-NEXT: v_or_b32_e32 v9, v2, v0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v7, v6
|
||||
; GISEL-NEXT: ; %bb.12: ; %Flow
|
||||
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
|
||||
|
||||
@ -45,27 +45,18 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
|
||||
; GFX9-GISEL: ; %bb.0: ; %entry
|
||||
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
||||
; GFX9-GISEL-NEXT: s_load_dword s7, s[8:9], 0x10
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s11, 0
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s11
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s11
|
||||
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-GISEL-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen glc slc
|
||||
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
|
||||
; GFX9-GISEL-NEXT: s_load_dword s7, s[8:9], 0x30
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s11
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s11
|
||||
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen glc slc
|
||||
@ -105,27 +96,18 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
|
||||
; GFX942-GISEL: ; %bb.0: ; %entry
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
|
||||
; GFX942-GISEL-NEXT: s_load_dword s11, s[4:5], 0x10
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s7, 0
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s8, s7
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s10, s7
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s9, s2
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX942-GISEL-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen nt
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
|
||||
; GFX942-GISEL-NEXT: s_load_dword s9, s[4:5], 0x30
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s4, s7
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s8, s7
|
||||
; GFX942-GISEL-NEXT: s_load_dword s7, s[4:5], 0x30
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX942-GISEL-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen nt
|
||||
@ -168,29 +150,22 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
|
||||
; GFX10-GISEL: ; %bb.0: ; %entry
|
||||
; GFX10-GISEL-NEXT: s_clause 0x1
|
||||
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
||||
; GFX10-GISEL-NEXT: s_load_dword s5, s[8:9], 0x10
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s7, 0
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s10, s7
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s4, s7
|
||||
; GFX10-GISEL-NEXT: s_load_dword s7, s[8:9], 0x10
|
||||
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s11, s2
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[0:1], s[6:7], s[10:11]
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[2:3], s[6:7], s[4:5]
|
||||
; GFX10-GISEL-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen slc
|
||||
; GFX10-GISEL-NEXT: s_clause 0x1
|
||||
; GFX10-GISEL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
|
||||
; GFX10-GISEL-NEXT: s_load_dword s11, s[8:9], 0x30
|
||||
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX10-GISEL-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen slc
|
||||
; GFX10-GISEL-NEXT: s_clause 0x1
|
||||
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
|
||||
; GFX10-GISEL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX10-GISEL-NEXT: s_load_dword s7, s[8:9], 0x30
|
||||
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
|
||||
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-GISEL-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen glc slc
|
||||
; GFX10-GISEL-NEXT: s_endpgm
|
||||
@ -234,32 +209,21 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
|
||||
; GFX11-GISEL: ; %bb.0: ; %entry
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x10
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s9, 0
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s10, s9
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s6, s9
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s11, s[4:5], 0x10
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s11, s2
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11]
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
|
||||
; GFX11-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen slc dlc
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s9, s2
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX11-GISEL-NEXT: buffer_load_b32 v0, v0, s[8:11], 0 offen slc dlc
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x20
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x30
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s4, s9
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-GISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], 0 offen glc slc dlc
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
@ -303,32 +267,21 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
|
||||
; GFX12-GISEL: ; %bb.0: ; %entry
|
||||
; GFX12-GISEL-NEXT: s_clause 0x1
|
||||
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
||||
; GFX12-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x10
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s9, 0
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s10, s9
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s6, s9
|
||||
; GFX12-GISEL-NEXT: s_load_b32 s11, s[4:5], 0x10
|
||||
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s11, s2
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11]
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
|
||||
; GFX12-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen th:TH_LOAD_NT
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s9, s2
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX12-GISEL-NEXT: buffer_load_b32 v0, v0, s[8:11], null offen th:TH_LOAD_NT
|
||||
; GFX12-GISEL-NEXT: s_clause 0x1
|
||||
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x20
|
||||
; GFX12-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x30
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s4, s9
|
||||
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-GISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen th:TH_STORE_NT
|
||||
; GFX12-GISEL-NEXT: s_endpgm
|
||||
@ -374,28 +327,19 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
|
||||
; GFX9-GISEL: ; %bb.0: ; %entry
|
||||
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
||||
; GFX9-GISEL-NEXT: s_load_dword s7, s[8:9], 0x10
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s11, 0
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s11
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s11
|
||||
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-GISEL-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen glc
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
|
||||
; GFX9-GISEL-NEXT: s_load_dword s7, s[8:9], 0x30
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s11
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s11
|
||||
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX9-GISEL-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
|
||||
; GFX9-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
@ -436,28 +380,19 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
|
||||
; GFX942-GISEL: ; %bb.0: ; %entry
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
|
||||
; GFX942-GISEL-NEXT: s_load_dword s11, s[4:5], 0x10
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s7, 0
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s8, s7
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s10, s7
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s9, s2
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX942-GISEL-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen sc0 sc1
|
||||
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
|
||||
; GFX942-GISEL-NEXT: s_load_dword s9, s[4:5], 0x30
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s4, s7
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s8, s7
|
||||
; GFX942-GISEL-NEXT: s_load_dword s7, s[4:5], 0x30
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX942-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX942-GISEL-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen sc0 sc1
|
||||
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
@ -501,30 +436,23 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
|
||||
; GFX10-GISEL: ; %bb.0: ; %entry
|
||||
; GFX10-GISEL-NEXT: s_clause 0x1
|
||||
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
||||
; GFX10-GISEL-NEXT: s_load_dword s5, s[8:9], 0x10
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s7, 0
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s10, s7
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s4, s7
|
||||
; GFX10-GISEL-NEXT: s_load_dword s7, s[8:9], 0x10
|
||||
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s11, s2
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[0:1], s[6:7], s[10:11]
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[2:3], s[6:7], s[4:5]
|
||||
; GFX10-GISEL-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc dlc
|
||||
; GFX10-GISEL-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen glc dlc
|
||||
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-GISEL-NEXT: s_clause 0x1
|
||||
; GFX10-GISEL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
|
||||
; GFX10-GISEL-NEXT: s_load_dword s11, s[8:9], 0x30
|
||||
; GFX10-GISEL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX10-GISEL-NEXT: s_load_dword s7, s[8:9], 0x30
|
||||
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX10-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX10-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
|
||||
; GFX10-GISEL-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
|
||||
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-GISEL-NEXT: s_endpgm
|
||||
@ -569,33 +497,22 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
|
||||
; GFX11-GISEL: ; %bb.0: ; %entry
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x10
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s9, 0
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s10, s9
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s6, s9
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s11, s[4:5], 0x10
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s11, s2
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11]
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
|
||||
; GFX11-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen glc dlc
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s9, s2
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX11-GISEL-NEXT: buffer_load_b32 v0, v0, s[8:11], 0 offen glc dlc
|
||||
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x20
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x30
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s4, s9
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-GISEL-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX11-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX11-GISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], 0 offen dlc
|
||||
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
@ -640,33 +557,22 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
|
||||
; GFX12-GISEL: ; %bb.0: ; %entry
|
||||
; GFX12-GISEL-NEXT: s_clause 0x1
|
||||
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
||||
; GFX12-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x10
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s9, 0
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s10, s9
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s6, s9
|
||||
; GFX12-GISEL-NEXT: s_load_b32 s11, s[4:5], 0x10
|
||||
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s11, s2
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[0:1], s[8:9], s[10:11]
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
|
||||
; GFX12-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen th:TH_LOAD_NT scope:SCOPE_SYS
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s9, s2
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s10, s3
|
||||
; GFX12-GISEL-NEXT: buffer_load_b32 v0, v0, s[8:11], null offen th:TH_LOAD_NT scope:SCOPE_SYS
|
||||
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_clause 0x1
|
||||
; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x20
|
||||
; GFX12-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x30
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s4, s9
|
||||
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s8, s3
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s4, s1
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s5, s2
|
||||
; GFX12-GISEL-NEXT: s_mov_b32 s6, s3
|
||||
; GFX12-GISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen th:TH_STORE_NT scope:SCOPE_SYS
|
||||
; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_endpgm
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user