[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC (#170396)
This commit is contained in:
Stanislav Mekhanoshin
GitHub
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5ee6cff90b
commit
befa4e85e4
@ -8,10 +8,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_ashr_i64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
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%2:sreg_64 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc
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...
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---
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@ -21,10 +23,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_lshl_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[DEF]], [[COPY]], implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_LSHL_B64 undef %1:sreg_64, %0, implicit-def $scc
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%2:sreg_64 = S_LSHL_B64 %1:sreg_64, %0, implicit-def $scc
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...
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---
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@ -34,10 +38,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_lshr_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[DEF]], [[COPY]], implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_LSHR_B64 undef %1:sreg_64, %0, implicit-def $scc
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%2:sreg_64 = S_LSHR_B64 %1:sreg_64, %0, implicit-def $scc
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...
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---
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@ -47,10 +53,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_bfe_i64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[DEF]], [[COPY]], implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_BFE_I64 undef %1:sreg_64, %0, implicit-def $scc
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%2:sreg_64 = S_BFE_I64 %1:sreg_64, %0, implicit-def $scc
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...
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---
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@ -60,10 +68,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_bfe_u64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[DEF]], [[COPY]], implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_BFE_U64 undef %1:sreg_64, %0, implicit-def $scc
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%2:sreg_64 = S_BFE_U64 %1:sreg_64, %0, implicit-def $scc
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...
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---
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@ -86,10 +96,14 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_bitcmp0_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: S_BITCMP0_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: $scc = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: S_BITCMP0_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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$scc = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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S_BITCMP0_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
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S_BITCMP0_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
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...
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---
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@ -99,10 +113,14 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_bitcmp1_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: S_BITCMP1_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: $scc = IMPLICIT_DEF
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: S_BITCMP1_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
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%1:sreg_64 = IMPLICIT_DEF
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$scc = IMPLICIT_DEF
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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S_BITCMP1_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
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S_BITCMP1_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
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...
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---
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@ -125,10 +143,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_bitset0_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BITSET0_B64_:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], undef [[S_BITSET0_B64_]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%1:sreg_64 = S_BITSET0_B64 %0, undef %1:sreg_64, implicit-def $scc
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; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
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; GCN-NEXT: $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
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; GCN-NEXT: $sgpr0_sgpr1 = S_BITSET0_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
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$sgpr0_sgpr1 = IMPLICIT_DEF
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$sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
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$sgpr0_sgpr1 = S_BITSET0_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
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...
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---
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@ -138,10 +158,12 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_bitset1_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BITSET1_B64_:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], undef [[S_BITSET1_B64_]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%1:sreg_64 = S_BITSET1_B64 %0, undef %1:sreg_64, implicit-def $scc
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; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
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; GCN-NEXT: $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
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; GCN-NEXT: $sgpr0_sgpr1 = S_BITSET1_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
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$sgpr0_sgpr1 = IMPLICIT_DEF
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$sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
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$sgpr0_sgpr1 = S_BITSET1_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
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...
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---
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@ -151,8 +173,11 @@ body: |
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bb.0:
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; GCN-LABEL: name: s_ashr_i64_phys_dst
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, [[COPY]], implicit-def $scc
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; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
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; GCN-NEXT: $sgpr2 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 $sgpr0_sgpr1, $sgpr2, implicit-def $scc
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$sgpr0_sgpr1 = IMPLICIT_DEF
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$sgpr2 = COPY $src_flat_scratch_base_hi
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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$sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
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$sgpr0_sgpr1 = S_ASHR_I64 $sgpr0_sgpr1, $sgpr2, implicit-def $scc
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...
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