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[AMDGPU][GlobalISel] Add RegBankLegalize rules for fma_legacy (#178759)

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vangthao95 2026-01-30 08:52:48 -08:00 committed by GitHub
parent b73122d5b7
commit bf8f6d8011
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2 changed files with 31 additions and 3 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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@ -1248,6 +1248,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32}});
addRulesForIOpcs({amdgcn_fma_legacy}, Standard)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
addRulesForIOpcs({amdgcn_frexp_mant, amdgcn_fract}, Standard)
.Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16}})
.Div(S16, {{Vgpr16}, {IntrId, Vgpr16}})

30
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
View File

@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
define float @v_fma(float %a, float %b, float %c) {
; GFX10-LABEL: v_fma:
@ -218,5 +218,29 @@ define float @v_fma_const_const(float %a) {
ret float %fma
}
define amdgpu_ps float @v_fma_sss(float inreg %a, float inreg %b, float inreg %c) {
; GFX10-LABEL: v_fma_sss:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_fma_legacy_f32 v0, s3, s2, v0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_fma_sss:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v0, s4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_dx9_zero_f32 v0, s3, s2, v0
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: v_fma_sss:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_fma_dx9_zero_f32 v0, s2, s3, v0
; GFX12-NEXT: ; return to shader part epilog
%fma = call float @llvm.amdgcn.fma.legacy(float %a, float %b, float %c)
ret float %fma
}
declare float @llvm.amdgcn.fma.legacy(float, float, float)
declare float @llvm.fabs.f32(float)