[RISCV][VLOPT] Add support for 11.11 div instructions (#112201)
This adds support for these instructions and also tests getOperandInfo for these instructions as well.
This commit is contained in:
Michael Maitland
GitHub
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82e89c0271
commit
c2c4db8d8f
@ -554,7 +554,14 @@ static bool isSupportedInstr(const MachineInstr &MI) {
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case RISCV::VMULHSU_VV:
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case RISCV::VMULHSU_VX:
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// 11.11. Vector Integer Divide Instructions
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// FIXME: Add support for 11.11 instructions
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case RISCV::VDIVU_VV:
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case RISCV::VDIVU_VX:
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case RISCV::VDIV_VV:
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case RISCV::VDIV_VX:
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case RISCV::VREMU_VV:
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case RISCV::VREMU_VX:
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case RISCV::VREM_VV:
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case RISCV::VREM_VX:
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// 11.12. Vector Widening Integer Multiply Instructions
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// FIXME: Add support for 11.12 instructions
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// 11.13. Vector Single-Width Integer Multiply-Add Instructions
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@ -962,6 +962,166 @@ define <vscale x 4 x i32> @vmulhsu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vdivu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; NOVLOPT-LABEL: vdivu_vv:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vdivu.vv v8, v8, v10
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; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v8, v10
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vdivu_vv:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; VLOPT-NEXT: vdivu.vv v8, v8, v10
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; VLOPT-NEXT: vmul.vv v8, v8, v10
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vdivu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vdivu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
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; NOVLOPT-LABEL: vdivu_vx:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vdivu.vx v10, v8, a0
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; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v10, v8
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vdivu_vx:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; VLOPT-NEXT: vdivu.vx v10, v8, a0
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; VLOPT-NEXT: vmul.vv v8, v10, v8
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vdivu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vdiv_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; NOVLOPT-LABEL: vdiv_vv:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vdiv.vv v8, v8, v10
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; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v8, v10
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vdiv_vv:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; VLOPT-NEXT: vdiv.vv v8, v8, v10
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; VLOPT-NEXT: vmul.vv v8, v8, v10
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vdiv.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vdiv_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
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; NOVLOPT-LABEL: vdiv_vx:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vdiv.vx v10, v8, a0
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; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v10, v8
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vdiv_vx:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; VLOPT-NEXT: vdiv.vx v10, v8, a0
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; VLOPT-NEXT: vmul.vv v8, v10, v8
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vdiv.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vremu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; NOVLOPT-LABEL: vremu_vv:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vremu.vv v8, v8, v10
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; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v8, v10
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vremu_vv:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; VLOPT-NEXT: vremu.vv v8, v8, v10
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; VLOPT-NEXT: vmul.vv v8, v8, v10
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vremu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vremu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
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; NOVLOPT-LABEL: vremu_vx:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vremu.vx v10, v8, a0
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; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v10, v8
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vremu_vx:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; VLOPT-NEXT: vremu.vx v10, v8, a0
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; VLOPT-NEXT: vmul.vv v8, v10, v8
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vremu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vrem_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; NOVLOPT-LABEL: vrem_vv:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vrem.vv v8, v8, v10
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; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v8, v10
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vrem_vv:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; VLOPT-NEXT: vrem.vv v8, v8, v10
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; VLOPT-NEXT: vmul.vv v8, v8, v10
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vrem.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vrem_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
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; NOVLOPT-LABEL: vrem_vx:
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; NOVLOPT: # %bb.0:
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; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; NOVLOPT-NEXT: vrem.vx v10, v8, a0
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; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; NOVLOPT-NEXT: vmul.vv v8, v10, v8
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; NOVLOPT-NEXT: ret
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;
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; VLOPT-LABEL: vrem_vx:
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; VLOPT: # %bb.0:
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; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; VLOPT-NEXT: vrem.vx v10, v8, a0
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; VLOPT-NEXT: vmul.vv v8, v10, v8
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; VLOPT-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vrem.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vwmacc_vx(<vscale x 4 x i16> %a, i16 %b, iXLen %vl) {
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; NOVLOPT-LABEL: vwmacc_vx:
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; NOVLOPT: # %bb.0:
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