shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

AMDGPU: Convert debug info tests to opaque pointers

Browse Source
This commit is contained in:
Matt Arsenault 2022-11-26 14:34:21 -05:00
parent 311801a017
commit c441bfb714
5 changed files with 66 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
View File

@ -18,23 +18,23 @@
declare void @llvm.dbg.declare(metadata, metadata, metadata)
define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 {
define amdgpu_kernel void @kernel1(ptr addrspace(1) %A) !dbg !7 {
entry:
%A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18
%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19
store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20
%A.addr = alloca ptr addrspace(1), align 4, addrspace(5)
store ptr addrspace(1) %A, ptr addrspace(5) %A.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %A.addr, metadata !16, metadata !17), !dbg !18
%0 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4, !dbg !19
store i32 11, ptr addrspace(1) %0, align 4, !dbg !20
ret void, !dbg !21
}
define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 {
define amdgpu_kernel void @kernel2(ptr addrspace(1) %B) !dbg !22 {
entry:
%B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24
%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25
store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26
%B.addr = alloca ptr addrspace(1), align 4, addrspace(5)
store ptr addrspace(1) %B, ptr addrspace(5) %B.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %B.addr, metadata !23, metadata !17), !dbg !24
%0 = load ptr addrspace(1), ptr addrspace(5) %B.addr, align 4, !dbg !25
store i32 12, ptr addrspace(1) %0, align 4, !dbg !26
ret void, !dbg !27
}

16
llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
View File

@ -20,18 +20,18 @@ declare void @llvm.dbg.value(metadata, metadata, metadata)
; CHECK-LABEL: {{^}}kernel1:
define amdgpu_kernel void @kernel1(
i32 addrspace(1)* nocapture readonly %A,
i32 addrspace(1)* nocapture %B) !dbg !7 {
ptr addrspace(1) nocapture readonly %A,
ptr addrspace(1) nocapture %B) !dbg !7 {
entry:
tail call void @llvm.dbg.value(metadata i32 addrspace(1)* %A, metadata !13, metadata !19), !dbg !20
tail call void @llvm.dbg.value(metadata i32 addrspace(1)* %B, metadata !14, metadata !19), !dbg !21
%0 = load i32, i32 addrspace(1)* %A, align 4, !dbg !22, !tbaa !24
tail call void @llvm.dbg.value(metadata ptr addrspace(1) %A, metadata !13, metadata !19), !dbg !20
tail call void @llvm.dbg.value(metadata ptr addrspace(1) %B, metadata !14, metadata !19), !dbg !21
%0 = load i32, ptr addrspace(1) %A, align 4, !dbg !22, !tbaa !24
%cmp = icmp eq i32 %0, 1, !dbg !28
br i1 %cmp, label %if.then, label %if.end, !dbg !29
if.then: ; preds = %entry
store i32 12, i32 addrspace(1)* %B, align 4, !dbg !30, !tbaa !24
%.pr = load i32, i32 addrspace(1)* %A, align 4, !dbg !32, !tbaa !24
store i32 12, ptr addrspace(1) %B, align 4, !dbg !30, !tbaa !24
%.pr = load i32, ptr addrspace(1) %A, align 4, !dbg !32, !tbaa !24
br label %if.end, !dbg !34
if.end: ; preds = %if.then, %entry
@ -40,7 +40,7 @@ if.end: ; preds = %if.then, %entry
br i1 %cmp1, label %if.then2, label %if.end3, !dbg !36
if.then2: ; preds = %if.end
store i32 13, i32 addrspace(1)* %B, align 4, !dbg !37, !tbaa !24
store i32 13, ptr addrspace(1) %B, align 4, !dbg !37, !tbaa !24
br label %if.end3, !dbg !39
if.end3: ; preds = %if.then2, %if.end

24
llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
View File

@ -19,23 +19,23 @@
declare void @llvm.dbg.declare(metadata, metadata, metadata)
define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 {
define amdgpu_kernel void @kernel1(ptr addrspace(1) %A) !dbg !7 {
entry:
%A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18
%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19
store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20
%A.addr = alloca ptr addrspace(1), align 4, addrspace(5)
store ptr addrspace(1) %A, ptr addrspace(5) %A.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %A.addr, metadata !16, metadata !17), !dbg !18
%0 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4, !dbg !19
store i32 11, ptr addrspace(1) %0, align 4, !dbg !20
ret void, !dbg !21
}
define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 {
define amdgpu_kernel void @kernel2(ptr addrspace(1) %B) !dbg !22 {
entry:
%B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24
%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25
store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26
%B.addr = alloca ptr addrspace(1), align 4, addrspace(5)
store ptr addrspace(1) %B, ptr addrspace(5) %B.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %B.addr, metadata !23, metadata !17), !dbg !24
%0 = load ptr addrspace(1), ptr addrspace(5) %B.addr, align 4, !dbg !25
store i32 12, ptr addrspace(1) %0, align 4, !dbg !26
ret void, !dbg !27
}

30
llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
View File

@ -53,21 +53,21 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
define amdgpu_kernel void @kernel1() !dbg !7 {
entry:
%FuncVar0 = alloca i32 addrspace(1)*, align 4, addrspace(5)
%FuncVar1 = alloca i32 addrspace(4)*, align 4, addrspace(5)
%FuncVar2 = alloca i32 addrspace(3)*, align 4, addrspace(5)
%FuncVar3 = alloca i32 addrspace(5)*, align 4, addrspace(5)
%FuncVar4 = alloca i32*, align 4, addrspace(5)
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %FuncVar0, metadata !10, metadata !13), !dbg !14
store i32 addrspace(1)* null, i32 addrspace(1)* addrspace(5)* %FuncVar0, align 4, !dbg !14
call void @llvm.dbg.declare(metadata i32 addrspace(4)* addrspace(5)* %FuncVar1, metadata !15, metadata !13), !dbg !16
store i32 addrspace(4)* null, i32 addrspace(4)* addrspace(5)* %FuncVar1, align 4, !dbg !16
call void @llvm.dbg.declare(metadata i32 addrspace(3)* addrspace(5)* %FuncVar2, metadata !17, metadata !13), !dbg !19
store i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*), i32 addrspace(3)* addrspace(5)* %FuncVar2, align 4, !dbg !19
call void @llvm.dbg.declare(metadata i32 addrspace(5)* addrspace(5)* %FuncVar3, metadata !20, metadata !13), !dbg !22
store i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %FuncVar3, align 4, !dbg !22
call void @llvm.dbg.declare(metadata i32* addrspace(5)* %FuncVar4, metadata !23, metadata !13), !dbg !24
store i32* null, i32* addrspace(5)* %FuncVar4, align 4, !dbg !24
%FuncVar0 = alloca ptr addrspace(1), align 4, addrspace(5)
%FuncVar1 = alloca ptr addrspace(4), align 4, addrspace(5)
%FuncVar2 = alloca ptr addrspace(3), align 4, addrspace(5)
%FuncVar3 = alloca ptr addrspace(5), align 4, addrspace(5)
%FuncVar4 = alloca ptr, align 4, addrspace(5)
call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar0, metadata !10, metadata !13), !dbg !14
store ptr addrspace(1) null, ptr addrspace(5) %FuncVar0, align 4, !dbg !14
call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar1, metadata !15, metadata !13), !dbg !16
store ptr addrspace(4) null, ptr addrspace(5) %FuncVar1, align 4, !dbg !16
call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar2, metadata !17, metadata !13), !dbg !19
store ptr addrspace(3) addrspacecast (ptr null to ptr addrspace(3)), ptr addrspace(5) %FuncVar2, align 4, !dbg !19
call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar3, metadata !20, metadata !13), !dbg !22
store ptr addrspace(5) addrspacecast (ptr null to ptr addrspace(5)), ptr addrspace(5) %FuncVar3, align 4, !dbg !22
call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar4, metadata !23, metadata !13), !dbg !24
store ptr null, ptr addrspace(5) %FuncVar4, align 4, !dbg !24
ret void, !dbg !25
}

38
llvm/test/DebugInfo/AMDGPU/variable-locations.ll
View File

@ -42,33 +42,33 @@ define amdgpu_kernel void @kernel1(
; CHECK: {{.*}}DW_TAG_formal_parameter
; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +8, DW_OP_lit1, DW_OP_swap, DW_OP_xderef)
; CHECK-NEXT: DW_AT_name {{.*}}"ArgA"
i32 addrspace(1)* %ArgA,
ptr addrspace(1) %ArgA,
; CHECK: {{.*}}DW_TAG_formal_parameter
; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +16, DW_OP_lit1, DW_OP_swap, DW_OP_xderef)
; CHECK-NEXT: DW_AT_name {{.*}}"ArgB"
i32 addrspace(1)* %ArgB) !dbg !13 {
ptr addrspace(1) %ArgB) !dbg !13 {
entry:
%ArgN.addr = alloca i32, align 4, addrspace(5)
%ArgA.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
%ArgB.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 %ArgN, i32 addrspace(5)* %ArgN.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(5)* %ArgN.addr, metadata !22, metadata !23), !dbg !24
store i32 addrspace(1)* %ArgA, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgA.addr, metadata !25, metadata !23), !dbg !26
store i32 addrspace(1)* %ArgB, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgB.addr, metadata !27, metadata !23), !dbg !28
%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4, !dbg !29
%1 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !30
%ArgA.addr = alloca ptr addrspace(1), align 4, addrspace(5)
%ArgB.addr = alloca ptr addrspace(1), align 4, addrspace(5)
store i32 %ArgN, ptr addrspace(5) %ArgN.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %ArgN.addr, metadata !22, metadata !23), !dbg !24
store ptr addrspace(1) %ArgA, ptr addrspace(5) %ArgA.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %ArgA.addr, metadata !25, metadata !23), !dbg !26
store ptr addrspace(1) %ArgB, ptr addrspace(5) %ArgB.addr, align 4
call void @llvm.dbg.declare(metadata ptr addrspace(5) %ArgB.addr, metadata !27, metadata !23), !dbg !28
%0 = load ptr addrspace(1), ptr addrspace(5) %ArgB.addr, align 4, !dbg !29
%1 = load i32, ptr addrspace(5) %ArgN.addr, align 4, !dbg !30
%idxprom = zext i32 %1 to i64, !dbg !29
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 %idxprom, !dbg !29
%2 = load i32, i32 addrspace(1)* %arrayidx, align 4, !dbg !29
%3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4, !dbg !31
%4 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !32
%arrayidx = getelementptr inbounds i32, ptr addrspace(1) %0, i64 %idxprom, !dbg !29
%2 = load i32, ptr addrspace(1) %arrayidx, align 4, !dbg !29
%3 = load ptr addrspace(1), ptr addrspace(5) %ArgA.addr, align 4, !dbg !31
%4 = load i32, ptr addrspace(5) %ArgN.addr, align 4, !dbg !32
%idxprom1 = zext i32 %4 to i64, !dbg !31
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %idxprom1, !dbg !31
%5 = load i32, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33
%arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %3, i64 %idxprom1, !dbg !31
%5 = load i32, ptr addrspace(1) %arrayidx2, align 4, !dbg !33
%add = add nsw i32 %5, %2, !dbg !33
store i32 %add, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33
store i32 %add, ptr addrspace(1) %arrayidx2, align 4, !dbg !33
ret void, !dbg !34
}