From c51a3aa6ceb63a58ab7658ea999c65b818da6b1d Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 4 May 2025 13:05:18 -0700 Subject: [PATCH] [llvm] Remove unused local variables (NFC) (#138467) --- llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | 1 - llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 ----- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 1 - llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp | 4 ---- .../Orc/TargetProcess/SimpleRemoteEPCServer.cpp | 1 - llvm/lib/ObjCopy/wasm/WasmReader.cpp | 1 - llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 2 -- llvm/lib/Target/ARM/ARMSubtarget.cpp | 2 -- llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp | 6 ------ llvm/lib/Transforms/IPO/IROutliner.cpp | 1 - llvm/tools/sancov/sancov.cpp | 1 - llvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp | 1 - llvm/unittests/XRay/GraphTest.cpp | 2 -- llvm/utils/TableGen/AsmWriterEmitter.cpp | 3 --- llvm/utils/TableGen/DFAEmitter.cpp | 1 - llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp | 1 - 16 files changed, 33 deletions(-) diff --git a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp index 02276695b5cf..d7e12dc80d7c 100644 --- a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp +++ b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp @@ -523,7 +523,6 @@ static void computeFunctionSummary( auto *MemProfMD = I.getMetadata(LLVMContext::MD_memprof); if (MemProfMD) { std::vector MIBs; - std::vector TotalSizes; std::vector> ContextSizeInfos; for (auto &MDOp : MemProfMD->operands()) { auto *MIBMD = cast(MDOp); diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 5c686f2f3907..713bf4177b5f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15197,10 +15197,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { if (ISD::isExtVecInRegOpcode(N0.getOpcode())) { SDValue N00 = N0.getOperand(0); unsigned N00Bits = N00.getScalarValueSizeInBits(); - unsigned DstElts = N0.getValueType().getVectorMinNumElements(); - unsigned SrcElts = N00.getValueType().getVectorMinNumElements(); bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; - APInt DemandedSrcElts = APInt::getLowBitsSet(SrcElts, DstElts); if ((N00Bits == ExtVTBits || (!IsZext && (N00Bits < ExtVTBits || DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) && @@ -20772,8 +20769,6 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { // We're checking for cases where we have common "c3 * A" expressions. bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, SDValue ConstNode) { - APInt Val; - // If the add only has one use, and the target thinks the folding is // profitable or does not lead to worse code, this would be OK to do. if (AddNode->hasOneUse() && diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 083173daae98..ba34c7215622 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -7965,7 +7965,6 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N, // If we shifted the input, shift the remainder left and add the bits we // shifted off the input. if (TrailingZeros) { - APInt Mask = APInt::getLowBitsSet(HBitWidth, TrailingZeros); RemL = DAG.getNode(ISD::SHL, dl, HiLoVT, RemL, DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl)); RemL = DAG.getNode(ISD::ADD, dl, HiLoVT, RemL, PartialRem); diff --git a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp index 49db94fff78a..43a62bdd8390 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp @@ -454,10 +454,6 @@ unsigned DWARFVerifier::verifyUnitSection(const DWARFSection &S) { bool hasDIE = DebugInfoData.isValidOffset(Offset); DWARFUnitVector TypeUnitVector; DWARFUnitVector CompileUnitVector; - /// A map that tracks all references (converted absolute references) so we - /// can verify each reference points to a valid DIE and not an offset that - /// lies between to valid DIEs. - ReferenceMap CrossUnitReferences; while (hasDIE) { if (!verifyUnitHeader(DebugInfoData, &Offset, UnitIdx, UnitType, isUnitDWARF64)) { diff --git a/llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp b/llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp index 0ac68122317a..74e3dfc567aa 100644 --- a/llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp @@ -191,7 +191,6 @@ Error SimpleRemoteEPCServer::sendSetupMessage( using namespace SimpleRemoteEPCDefaultBootstrapSymbolNames; - std::vector SetupPacket; SimpleRemoteEPCExecutorInfo EI; EI.TargetTriple = sys::getProcessTriple(); if (auto PageSize = sys::Process::getPageSize()) diff --git a/llvm/lib/ObjCopy/wasm/WasmReader.cpp b/llvm/lib/ObjCopy/wasm/WasmReader.cpp index 420d17f98643..fe61d120013e 100644 --- a/llvm/lib/ObjCopy/wasm/WasmReader.cpp +++ b/llvm/lib/ObjCopy/wasm/WasmReader.cpp @@ -19,7 +19,6 @@ Expected> Reader::create() const { auto Obj = std::make_unique(); Obj->Header = WasmObj.getHeader(); Obj->isRelocatableObject = WasmObj.isRelocatableObject(); - std::vector
Sections; Obj->Sections.reserve(WasmObj.getNumSections()); for (const SectionRef &Sec : WasmObj.sections()) { const WasmSection &WS = WasmObj.getWasmSection(Sec); diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index be07e88e8785..5193e8c15bb1 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -841,8 +841,6 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; - std::vector I1Defs; - for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE; ++BI) { diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 759070c6f08d..91d385a0b595 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -489,8 +489,6 @@ ARMSubtarget::PushPopSplitVariation ARMSubtarget::getPushPopSplitVariation(const MachineFunction &MF) const { const Function &F = MF.getFunction(); const MachineFrameInfo &MFI = MF.getFrameInfo(); - const std::vector CSI = - MF.getFrameInfo().getCalleeSavedInfo(); // Thumb1 always splits the pushes at R7, because the Thumb1 push instruction // cannot use high registers except for lr. diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index d430b52bd138..bc51b293b5dd 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1323,12 +1323,6 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, // Select the definition points, and generate the assignment between // these points and the uses. - // For each candidate offset, keep a pair CandData consisting of - // the total number of ranges containing that candidate, and the - // vector of corresponding RangeTree nodes. - using CandData = std::pair>; - std::map CandMap; - RangeTree Tree; for (const OffsetRange &R : Ranges) Tree.add(R); diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp b/llvm/lib/Transforms/IPO/IROutliner.cpp index 92d10d1c85ca..ff66a518be75 100644 --- a/llvm/lib/Transforms/IPO/IROutliner.cpp +++ b/llvm/lib/Transforms/IPO/IROutliner.cpp @@ -2296,7 +2296,6 @@ void IROutliner::deduplicateExtractedSections( fillOverallFunction(M, CurrentGroup, OutputStoreBBs, FuncsToRemove, OutputMappings); - std::vector SortedKeys; for (unsigned Idx = 1; Idx < CurrentGroup.Regions.size(); Idx++) { CurrentOS = CurrentGroup.Regions[Idx]; AttributeFuncs::mergeAttributesForOutlining(*CurrentGroup.OutlinedFunction, diff --git a/llvm/tools/sancov/sancov.cpp b/llvm/tools/sancov/sancov.cpp index 727b94b8477c..2cc84b47de6b 100644 --- a/llvm/tools/sancov/sancov.cpp +++ b/llvm/tools/sancov/sancov.cpp @@ -1003,7 +1003,6 @@ static void printNotCoveredFunctions(const SymbolizedCoverage &CovData, // Read list of files and merges their coverage info. static void readAndPrintRawCoverage(const std::vector &FileNames, raw_ostream &OS) { - std::vector> Covs; for (const auto &FileName : FileNames) { auto Cov = RawCoverage::read(FileName); if (!Cov) diff --git a/llvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp b/llvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp index b4501c36fd2b..bf09cff090ca 100644 --- a/llvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp +++ b/llvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp @@ -97,7 +97,6 @@ TEST(TypeHashingTest, ContentHash) { // LF_PROCEDURE 0x1004 {int** func(char**, int***)} // ArgList = 0x1003 // ReturnType = 0x1001 - std::vector Ordering1Hashes; CharPP[0] = createPointerRecord(Ordering1, CharP); IntPP[0] = createPointerRecord(Ordering1, IntP); IntPPP[0] = createPointerRecord(Ordering1, IntPP[0]); diff --git a/llvm/unittests/XRay/GraphTest.cpp b/llvm/unittests/XRay/GraphTest.cpp index 424fed13c17a..9a9e0e424fce 100644 --- a/llvm/unittests/XRay/GraphTest.cpp +++ b/llvm/unittests/XRay/GraphTest.cpp @@ -85,8 +85,6 @@ template void graphVertexTester(T &G) { } template void graphEdgeTester(T &G) { - std::set V({1u, 2u, 3u, 4u, 5u, 6u}); - std::set> E( {{1u, 2u}, {2u, 3u}, {6u, 3u}, {4u, 6u}, {2u, 4u}, {2u, 5u}, {4u, 5u}}); std::vector VA({0u, 3u, 5u, 7u, 11u, 13u, 17u}); diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp index 795185c677e3..d0ec4fc8e23a 100644 --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -869,9 +869,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { DenseMap MCOpPredicateMap; for (auto &Aliases : AliasMap) { - // Collection of instruction alias rules. May contain ambiguous rules. - std::vector IAPs; - for (auto &Alias : Aliases.second) { const CodeGenInstAlias &CGA = Alias.first; unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp index a77397dd7d26..eb0b0b448074 100644 --- a/llvm/utils/TableGen/DFAEmitter.cpp +++ b/llvm/utils/TableGen/DFAEmitter.cpp @@ -118,7 +118,6 @@ void DfaEmitter::emit(StringRef Name, raw_ostream &OS) { OS << "// to by index in " << Name << "Transitions[].\n"; SequenceToOffsetTable Table; - std::map EmittedIndices; for (auto &T : DfaTransitions) Table.add(T.second.second); Table.layout(); diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp index ad656aaefe54..4e491f8983ec 100644 --- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp @@ -567,7 +567,6 @@ void CombineRuleOperandTypeChecker::getInstEqClasses( CombineRuleOperandTypeChecker::TypeEquivalenceClasses CombineRuleOperandTypeChecker::getRuleEqClasses() const { - StringMap OpNameToEqClassIdx; TypeEquivalenceClasses TECs; if (DebugTypeInfer)