[RISCV] Add shuffle coverage for compress, decompress, and repeat idioms
compress is intented to match vcompress from the ISA manual. Note that deinterleave is a subset of this, and is already tested elsewhere. decompress is the synthetic pattern defined in same - though we can often do better than the mentioned iota/vrgather. Note that some of these can also be expressed as interleave with at least one undef source, and is already tested elsewhere. repeat repeats each input element N times in the output. It can be described as as a interleave operations, but we can sometimes do better lowering wise.
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Philip Reames
Philip Reames
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b1a34b80b8
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c55a080c08
@ -744,3 +744,200 @@ define <8 x i8> @shuffle_v64i8_v8i8(<64 x i8> %wide.vec) {
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%s = shufflevector <64 x i8> %wide.vec, <64 x i8> poison, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 40, i32 48, i32 56>
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ret <8 x i8> %s
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}
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define <8 x i8> @shuffle_compress_singlesrc_e8(<8 x i8> %v) {
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; CHECK-LABEL: shuffle_compress_singlesrc_e8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI49_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI49_0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vle8.v v10, (a0)
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; CHECK-NEXT: vrgather.vv v9, v8, v10
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 5, i32 7, i32 undef, i32 undef, i32 undef>
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ret <8 x i8> %out
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}
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define <8 x i16> @shuffle_compress_singlesrc_e16(<8 x i16> %v) {
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; CHECK-LABEL: shuffle_compress_singlesrc_e16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI50_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI50_0)
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v10, (a0)
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; CHECK-NEXT: vrgather.vv v9, v8, v10
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 5, i32 7, i32 undef, i32 undef, i32 undef>
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ret <8 x i16> %out
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}
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define <8 x i32> @shuffle_compress_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_compress_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI51_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI51_0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vle16.v v12, (a0)
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 undef>
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ret <8 x i32> %out
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}
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define <8 x i64> @shuffle_compress_singlesrc_e64(<8 x i64> %v) {
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; CHECK-LABEL: shuffle_compress_singlesrc_e64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI52_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI52_0)
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; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
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; CHECK-NEXT: vle16.v v16, (a0)
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; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
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; CHECK-NEXT: vmv.v.v v8, v12
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i64> %v, <8 x i64> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 5, i32 7, i32 undef, i32 undef, i32 undef>
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ret <8 x i64> %out
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}
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define <8 x i32> @shuffle_compress_singlesrc_gaps_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_compress_singlesrc_gaps_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI53_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI53_0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vle16.v v12, (a0)
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 undef, i32 4, i32 5, i32 7, i32 undef, i32 undef, i32 undef>
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ret <8 x i32> %out
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}
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define <8 x i32> @shuffle_decompress2_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_decompress2_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v8
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v8
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef>
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ret <8 x i32> %out
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}
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define <8 x i32> @shuffle_decompress3_singlesrc_e32(<8 x i32> %v) {
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; RV32-LABEL: shuffle_decompress3_singlesrc_e32:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, %hi(.LCPI55_0)
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; RV32-NEXT: addi a0, a0, %lo(.LCPI55_0)
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; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV32-NEXT: vle16.v v12, (a0)
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; RV32-NEXT: vrgatherei16.vv v10, v8, v12
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; RV32-NEXT: vmv.v.v v8, v10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: shuffle_decompress3_singlesrc_e32:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 32769
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; RV64-NEXT: slli a0, a0, 21
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vmv.v.x v12, a0
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; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV64-NEXT: vrgatherei16.vv v10, v8, v12
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; RV64-NEXT: vmv.v.v v8, v10
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; RV64-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 2, i32 undef>
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ret <8 x i32> %out
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}
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; TODO: This should be a single vslideup.vi
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define <8 x i32> @shuffle_decompress4_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_decompress4_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: vsrl.vi v12, v10, 2
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef>
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ret <8 x i32> %out
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}
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; TODO: This should be either a single vslideup.vi or two widening interleaves.
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define <8 x i8> @shuffle_decompress4_singlesrc_e8(<8 x i8> %v) {
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; CHECK-LABEL: shuffle_decompress4_singlesrc_e8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: vsrl.vi v10, v9, 2
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; CHECK-NEXT: vrgather.vv v9, v8, v10
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef>
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ret <8 x i8> %out
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}
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define <8 x i32> @shuffle_decompress_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_decompress_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI58_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI58_0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vle16.v v12, (a0)
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 3, i32 undef, i32 undef, i32 4>
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ret <8 x i32> %out
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}
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define <8 x i32> @shuffle_repeat2_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_repeat2_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v8
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v8
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
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ret <8 x i32> %out
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}
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define <8 x i32> @shuffle_repeat3_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_repeat3_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v0, 7
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; CHECK-NEXT: vmv.v.i v11, 1
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; CHECK-NEXT: li a0, 192
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vmerge.vim v11, v11, 0, v0
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; CHECK-NEXT: vmv.v.v v0, v10
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; CHECK-NEXT: vmerge.vim v12, v11, 2, v0
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 2, i32 2>
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ret <8 x i32> %out
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}
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define <8 x i32> @shuffle_repeat4_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_repeat4_singlesrc_e32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: vsrl.vi v12, v10, 2
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %out
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}
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