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AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)

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Previously the value created to represent the uninitialized memory
of the alloca was undef. Use freeze poison instead. Enables some
optimization improvements (which need defeating in the limit tests),
but also a few regressions. Seems to leave behind dead code in some
cases too.
This commit is contained in:
Matt Arsenault 2025-03-18 17:27:02 +07:00 committed by GitHub
parent f7716047c6
commit c5fe075eaf
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
15 changed files with 279 additions and 74 deletions
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20
llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
View File

@ -773,6 +773,15 @@ static void forEachWorkListItem(const InstContainer &WorkList,
}
}
/// Find an insert point after an alloca, after all other allocas clustered at
/// the start of the block.
static BasicBlock::iterator skipToNonAllocaInsertPt(BasicBlock &BB,
BasicBlock::iterator I) {
for (BasicBlock::iterator E = BB.end(); I != E && isa<AllocaInst>(*I); ++I)
;
return I;
}
// FIXME: Should try to pick the most likely to be profitable allocas first.
bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) {
LLVM_DEBUG(dbgs() << "Trying to promote to vector: " << Alloca << '\n');
@ -989,7 +998,16 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) {
// undef.
SSAUpdater Updater;
Updater.Initialize(VectorTy, "promotealloca");
Updater.AddAvailableValue(Alloca.getParent(), UndefValue::get(VectorTy));
BasicBlock *EntryBB = Alloca.getParent();
BasicBlock::iterator InitInsertPos =
skipToNonAllocaInsertPt(*EntryBB, Alloca.getIterator());
// Alloca memory is undefined to begin, not poison.
Value *AllocaInitValue =
new FreezeInst(PoisonValue::get(VectorTy), "", InitInsertPos);
AllocaInitValue->takeName(&Alloca);
Updater.AddAvailableValue(EntryBB, AllocaInitValue);
// First handle the initial worklist.
SmallVector<LoadInst *, 4> DeferredLoads;

32
llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
View File

@ -87,11 +87,12 @@ define amdgpu_vs void @promote_store_aggr() #0 {
define amdgpu_vs void @promote_load_from_store_aggr() #0 {
; CHECK-LABEL: @promote_load_from_store_aggr(
; CHECK-NEXT: [[F1:%.*]] = freeze <2 x float> poison
; CHECK-NEXT: [[FOO:%.*]] = getelementptr [[BLOCK3:%.*]], ptr addrspace(1) @block3, i32 0, i32 1
; CHECK-NEXT: [[FOO1:%.*]] = load i32, ptr addrspace(1) [[FOO]], align 4
; CHECK-NEXT: [[FOO3:%.*]] = load [2 x float], ptr addrspace(1) @block3, align 4
; CHECK-NEXT: [[FOO3_FCA_0_EXTRACT:%.*]] = extractvalue [2 x float] [[FOO3]], 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[FOO3_FCA_0_EXTRACT]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[F1]], float [[FOO3_FCA_0_EXTRACT]], i32 0
; CHECK-NEXT: [[FOO3_FCA_1_EXTRACT:%.*]] = extractvalue [2 x float] [[FOO3]], 1
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[FOO3_FCA_1_EXTRACT]], i32 1
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 [[FOO1]]
@ -131,8 +132,9 @@ define amdgpu_vs void @promote_load_from_store_aggr() #0 {
; optimized out (variable %aliasTofoo3 in the test)
define amdgpu_vs void @promote_load_from_store_aggr_varoff(<4 x i32> %input) {
; CHECK-LABEL: @promote_load_from_store_aggr_varoff(
; CHECK-NEXT: [[F1:%.*]] = freeze <3 x i32> poison
; CHECK-NEXT: [[FOO3_UNPACK2:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @block4, i64 8), align 4
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> undef, i32 [[FOO3_UNPACK2]], i32 2
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> [[F1]], i32 [[FOO3_UNPACK2]], i32 2
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i32> [[TMP1]], i32 [[FOO3_UNPACK2]]
; CHECK-NEXT: [[FOO12:%.*]] = insertelement <4 x i32> [[INPUT:%.*]], i32 [[TMP2]], i64 3
; CHECK-NEXT: store <4 x i32> [[FOO12]], ptr addrspace(1) @pv1, align 16
@ -152,6 +154,15 @@ define amdgpu_vs void @promote_load_from_store_aggr_varoff(<4 x i32> %input) {
define amdgpu_vs void @promote_memmove_aggr() #0 {
; CHECK-LABEL: @promote_memmove_aggr(
; CHECK-NEXT: [[F1:%.*]] = freeze <5 x float> poison
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x float> [[F1]], float 0.000000e+00, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <5 x float> [[TMP1]], float 0.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <5 x float> [[TMP2]], float 0.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <5 x float> [[TMP3]], float 0.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <5 x float> [[TMP4]], float 0.000000e+00, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <5 x float> [[TMP5]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <5 x float> [[TMP6]], float 2.000000e+00, i32 3
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <5 x float> [[TMP7]], <5 x float> poison, <5 x i32> <i32 1, i32 2, i32 3, i32 4, i32 4>
; CHECK-NEXT: store float 1.000000e+00, ptr addrspace(1) @pv, align 4
; CHECK-NEXT: ret void
;
@ -169,9 +180,16 @@ define amdgpu_vs void @promote_memmove_aggr() #0 {
define amdgpu_vs void @promote_memcpy_aggr() #0 {
; CHECK-LABEL: @promote_memcpy_aggr(
; CHECK-NEXT: [[F1:%.*]] = freeze <5 x float> poison
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <5 x float> [[F1]], float 0.000000e+00, i32 0
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <5 x float> [[TMP7]], float 0.000000e+00, i32 1
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <5 x float> [[TMP8]], float 0.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <5 x float> [[TMP9]], float 0.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <5 x float> [[TMP4]], float 0.000000e+00, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <5 x float> [[TMP5]], float 2.000000e+00, i32 3
; CHECK-NEXT: [[FOO3:%.*]] = getelementptr [[BLOCK3:%.*]], ptr addrspace(1) @block3, i32 0, i32 0
; CHECK-NEXT: [[FOO4:%.*]] = load i32, ptr addrspace(1) [[FOO3]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, float 3.000000e+00, i32 [[FOO4]]
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x float> [[TMP6]], float 3.000000e+00, i32 [[FOO4]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <5 x float> [[TMP1]], <5 x float> poison, <5 x i32> <i32 3, i32 4, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <5 x float> [[TMP2]], i32 0
; CHECK-NEXT: store float [[TMP3]], ptr addrspace(1) @pv, align 4
@ -300,9 +318,15 @@ define amdgpu_vs void @promote_memcpy_p1p5_aggr(ptr addrspace(1) inreg %src) #0
define amdgpu_vs void @promote_memcpy_inline_aggr() #0 {
; CHECK-LABEL: @promote_memcpy_inline_aggr(
; CHECK-NEXT: [[F1:%.*]] = freeze <5 x float> poison
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <5 x float> [[F1]], float 0.000000e+00, i32 0
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <5 x float> [[TMP6]], float 0.000000e+00, i32 1
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <5 x float> [[TMP7]], float 0.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <5 x float> [[TMP8]], float 0.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <5 x float> [[TMP4]], float 0.000000e+00, i32 4
; CHECK-NEXT: [[FOO3:%.*]] = getelementptr [[BLOCK3:%.*]], ptr addrspace(1) @block3, i32 0, i32 0
; CHECK-NEXT: [[FOO4:%.*]] = load i32, ptr addrspace(1) [[FOO3]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x float> zeroinitializer, float 3.000000e+00, i32 [[FOO4]]
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x float> [[TMP5]], float 3.000000e+00, i32 [[FOO4]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <5 x float> [[TMP1]], <5 x float> poison, <5 x i32> <i32 3, i32 4, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <5 x float> [[TMP2]], i32 0
; CHECK-NEXT: store float [[TMP3]], ptr addrspace(1) @pv, align 4

2
llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
View File

@ -9,6 +9,8 @@ define amdgpu_kernel void @simple_users_scores() {
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MANYUSERS:%.*]] = alloca [64 x i64], align 4, addrspace(5)
; CHECK-NEXT: [[SIMPLEUSER:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> [[SIMPLEUSER]], i64 42, i32 0
; CHECK-NEXT: [[MANYUSERS_1:%.*]] = getelementptr i8, ptr addrspace(5) [[MANYUSERS]], i64 2
; CHECK-NEXT: [[V0:%.*]] = load i8, ptr addrspace(5) [[MANYUSERS_1]], align 1
; CHECK-NEXT: [[V0_EXT:%.*]] = zext i8 [[V0]] to i64

50
llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
View File

@ -7,17 +7,19 @@ define amdgpu_kernel void @test_overwrite(i64 %val, i1 %cond) {
; CHECK-LABEL: define amdgpu_kernel void @test_overwrite
; CHECK-SAME: (i64 [[VAL:%.*]], i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <3 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x i64> [[STACK]], i64 43, i32 0
; CHECK-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[END:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP2:%.*]], [[LOOP]] ], [ <i64 43, i64 undef, i64 undef>, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 68, i32 0
; CHECK-NEXT: [[TMP2]] = insertelement <3 x i64> [[TMP1]], i64 32, i32 0
; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP0]], 68
; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP3:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 68, i32 0
; CHECK-NEXT: [[TMP3]] = insertelement <3 x i64> [[TMP2]], i64 32, i32 0
; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP1]], 68
; CHECK-NEXT: br i1 [[LOOP_CC]], label [[LOOP]], label [[END]]
; CHECK: end:
; CHECK-NEXT: [[PROMOTEALLOCA:%.*]] = phi <3 x i64> [ [[TMP2]], [[LOOP]] ], [ <i64 43, i64 undef, i64 undef>, [[ENTRY]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 0
; CHECK-NEXT: [[PROMOTEALLOCA:%.*]] = phi <3 x i64> [ [[TMP3]], [[LOOP]] ], [ [[TMP0]], [[ENTRY]] ]
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 0
; CHECK-NEXT: ret void
;
entry:
@ -42,8 +44,9 @@ define <4 x i64> @test_fullvec_out_of_bounds(<4 x i64> %arg) {
; CHECK-LABEL: define <4 x i64> @test_fullvec_out_of_bounds
; CHECK-SAME: (<4 x i64> [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i64> [[ARG]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> undef, i64 [[TMP0]], i32 3
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[STACK]], i64 [[TMP0]], i32 3
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[ARG]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[ARG]], i64 2
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[ARG]], i64 3
@ -62,17 +65,19 @@ define amdgpu_kernel void @test_no_overwrite(i64 %val, i1 %cond) {
; CHECK-LABEL: define amdgpu_kernel void @test_no_overwrite
; CHECK-SAME: (i64 [[VAL:%.*]], i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <3 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x i64> [[STACK]], i64 43, i32 0
; CHECK-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[END:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP1:%.*]], [[LOOP]] ], [ <i64 43, i64 undef, i64 undef>, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 0
; CHECK-NEXT: [[TMP1]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 32, i32 1
; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP0]], 32
; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP2:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 0
; CHECK-NEXT: [[TMP2]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 32, i32 1
; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP1]], 32
; CHECK-NEXT: br i1 [[LOOP_CC]], label [[LOOP]], label [[END]]
; CHECK: end:
; CHECK-NEXT: [[PROMOTEALLOCA:%.*]] = phi <3 x i64> [ [[TMP1]], [[LOOP]] ], [ <i64 43, i64 undef, i64 undef>, [[ENTRY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 1
; CHECK-NEXT: [[PROMOTEALLOCA:%.*]] = phi <3 x i64> [ [[TMP2]], [[LOOP]] ], [ [[TMP0]], [[ENTRY]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 1
; CHECK-NEXT: ret void
;
entry:
@ -97,6 +102,7 @@ define ptr @alloca_load_store_ptr64_full_ivec(ptr %arg) {
; CHECK-LABEL: define ptr @alloca_load_store_ptr64_full_ivec
; CHECK-SAME: (ptr [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i8> poison
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <8 x i8>
; CHECK-NEXT: ret ptr [[ARG]]
@ -112,6 +118,7 @@ define ptr addrspace(3) @alloca_load_store_ptr32_full_ivec(ptr addrspace(3) %arg
; CHECK-LABEL: define ptr addrspace(3) @alloca_load_store_ptr32_full_ivec
; CHECK-SAME: (ptr addrspace(3) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <4 x i8> poison
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(3) [[ARG]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to <4 x i8>
; CHECK-NEXT: ret ptr addrspace(3) [[ARG]]
@ -127,6 +134,7 @@ define <4 x ptr addrspace(3)> @alloca_load_store_ptr_mixed_full_ptrvec(<2 x ptr>
; CHECK-LABEL: define <4 x ptr addrspace(3)> @alloca_load_store_ptr_mixed_full_ptrvec
; CHECK-SAME: (<2 x ptr> [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <4 x i32> poison
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr> [[ARG]] to <2 x i64>
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = inttoptr <4 x i32> [[TMP1]] to <4 x ptr addrspace(3)>
@ -143,6 +151,7 @@ define <8 x i16> @ptralloca_load_store_ints_full(<2 x i64> %arg) {
; CHECK-LABEL: define <8 x i16> @ptralloca_load_store_ints_full
; CHECK-SAME: (<2 x i64> [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x ptr addrspace(5)> poison
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[ARG]] to <4 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = inttoptr <4 x i32> [[TMP0]] to <4 x ptr addrspace(5)>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <8 x i16>
@ -159,9 +168,10 @@ define void @alloca_load_store_ptr_mixed_ptrvec(<2 x ptr addrspace(3)> %arg) {
; CHECK-LABEL: define void @alloca_load_store_ptr_mixed_ptrvec
; CHECK-SAME: (<2 x ptr addrspace(3)> [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i32> poison
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr addrspace(3)> [[ARG]] to <2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[ALLOCA]], i32 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[TMP3]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP1]], i64 0
@ -169,9 +179,11 @@ define void @alloca_load_store_ptr_mixed_ptrvec(<2 x ptr addrspace(3)> %arg) {
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr <2 x i32> [[TMP6]] to <2 x ptr addrspace(3)>
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP3]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 undef, i64 2
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 undef, i64 3
; CHECK-NEXT: [[TMP12:%.*]] = inttoptr <4 x i32> [[TMP11]] to <4 x ptr addrspace(3)>
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP4]], i32 2
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP10]], i64 2
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i32> [[TMP4]], i32 3
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP12]], i64 3
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr <4 x i32> [[TMP13]] to <4 x ptr addrspace(3)>
; CHECK-NEXT: ret void
;
entry:

6
llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
View File

@ -31,6 +31,7 @@ define amdgpu_kernel void @i32_24_elements(ptr %out) #0 {
; MAX24-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; MAX24-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; MAX24-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; MAX24-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison
; MAX24-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]
; MAX24-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; MAX24-NEXT: ret void
@ -43,6 +44,7 @@ define amdgpu_kernel void @i32_24_elements(ptr %out) #0 {
; MAX32-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; MAX32-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; MAX32-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; MAX32-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison
; MAX32-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]
; MAX32-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; MAX32-NEXT: ret void
@ -74,6 +76,7 @@ define amdgpu_kernel void @i32_24_elements_attrib(ptr %out) #1 {
; BASE-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; BASE-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; BASE-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; BASE-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison
; BASE-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]
; BASE-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; BASE-NEXT: ret void
@ -143,6 +146,7 @@ define amdgpu_kernel void @i32_32_elements(ptr %out) #0 {
; MAX32-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; MAX32-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; MAX32-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; MAX32-NEXT: [[ALLOCA:%.*]] = freeze <32 x i32> poison
; MAX32-NEXT: [[TMP1:%.*]] = extractelement <32 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0>, i32 [[SEL2]]
; MAX32-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; MAX32-NEXT: ret void
@ -174,6 +178,7 @@ define amdgpu_kernel void @i32_32_elements_attrib(ptr %out) #2 {
; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <32 x i32> poison
; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <32 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0>, i32 [[SEL2]]
; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; DEFAULT-NEXT: ret void
@ -205,6 +210,7 @@ define amdgpu_kernel void @i32_32_elements_attrib(ptr %out) #2 {
; MAX32-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; MAX32-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; MAX32-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; MAX32-NEXT: [[ALLOCA:%.*]] = freeze <32 x i32> poison
; MAX32-NEXT: [[TMP1:%.*]] = extractelement <32 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0>, i32 [[SEL2]]
; MAX32-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; MAX32-NEXT: ret void

6
llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
View File

@ -6,6 +6,7 @@
define amdgpu_kernel void @memset_all_zero(i64 %val) {
; CHECK-LABEL: @memset_all_zero(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <6 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <6 x i64> zeroinitializer, i64 [[VAL:%.*]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i64> [[TMP0]], i64 [[VAL]], i32 1
; CHECK-NEXT: ret void
@ -23,6 +24,7 @@ entry:
define amdgpu_kernel void @memset_all_5(i64 %val) {
; CHECK-LABEL: @memset_all_5(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> splat (i64 361700864190383365), i64 [[VAL:%.*]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[VAL]], i32 1
; CHECK-NEXT: ret void
@ -86,6 +88,7 @@ entry:
define amdgpu_kernel void @memset_array_ptr_alloca(ptr %out) {
; CHECK-LABEL: @memset_array_ptr_alloca(
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison
; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
@ -98,6 +101,7 @@ define amdgpu_kernel void @memset_array_ptr_alloca(ptr %out) {
define amdgpu_kernel void @memset_vector_ptr_alloca(ptr %out) {
; CHECK-LABEL: @memset_vector_ptr_alloca(
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison
; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
@ -110,6 +114,7 @@ define amdgpu_kernel void @memset_vector_ptr_alloca(ptr %out) {
define amdgpu_kernel void @memset_array_of_array_ptr_alloca(ptr %out) {
; CHECK-LABEL: @memset_array_of_array_ptr_alloca(
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison
; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
@ -122,6 +127,7 @@ define amdgpu_kernel void @memset_array_of_array_ptr_alloca(ptr %out) {
define amdgpu_kernel void @memset_array_of_vec_ptr_alloca(ptr %out) {
; CHECK-LABEL: @memset_array_of_vec_ptr_alloca(
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x ptr> poison
; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;

119
llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
View File

@ -4,6 +4,13 @@
define amdgpu_kernel void @i32_2d_load_store(ptr %out) {
; CHECK-LABEL: define amdgpu_kernel void @i32_2d_load_store(
; CHECK-SAME: ptr [[OUT:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i32> poison
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i32> [[ALLOCA]], i32 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i32> [[TMP1]], i32 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i32> [[TMP2]], i32 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i32> [[TMP3]], i32 3, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i32> [[TMP4]], i32 4, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i32> [[TMP5]], i32 5, i32 5
; CHECK-NEXT: store i32 3, ptr [[OUT]], align 4
; CHECK-NEXT: ret void
;
@ -29,6 +36,13 @@ define amdgpu_kernel void @i32_2d_load_store(ptr %out) {
define amdgpu_kernel void @i64_2d_load_store(ptr %out) {
; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store(
; CHECK-SAME: ptr [[OUT:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i64> [[TMP1]], i64 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i64> [[TMP2]], i64 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i64> [[TMP3]], i64 3, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i64> [[TMP4]], i64 4, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i64> [[TMP5]], i64 5, i32 5
; CHECK-NEXT: store i64 3, ptr [[OUT]], align 8
; CHECK-NEXT: ret void
;
@ -61,7 +75,12 @@ define amdgpu_kernel void @i32_2d_alloca_store_partial(ptr addrspace(1) %out, pt
; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 {{.*}}, i32 {{.*}}, i32 {{.*}}, i32 {{.*}}>, i32 [[SEL2]]
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i32> poison
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[ALLOCA]], i32 1, i32 0
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 2, i32 1
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP5]], i32 3, i32 2
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 4, i32 3
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i32> [[TMP3]], i32 [[SEL2]]
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
; CHECK-NEXT: store float [[TMP1]], ptr addrspace(1) [[OUT]], align 4
; CHECK-NEXT: ret void
@ -91,7 +110,14 @@ define amdgpu_kernel void @i64_2d_load_store_cast(ptr %out) {
; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i32 [[SEL2]]
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i64> [[TMP7]], i64 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i64> [[TMP2]], i64 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i64> [[TMP3]], i64 3, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i64> [[TMP4]], i64 4, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i64> [[TMP5]], i64 5, i32 5
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <6 x i64> [[TMP6]], i32 [[SEL2]]
; CHECK-NEXT: store i64 [[TMP1]], ptr [[OUT]], align 8
; CHECK-NEXT: ret void
;
@ -123,6 +149,13 @@ define amdgpu_kernel void @i64_2d_load_store_cast(ptr %out) {
define amdgpu_kernel void @i64_2d_load_store_subvec_1(ptr %out) {
; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_1(
; CHECK-SAME: ptr [[OUT:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i64> [[TMP1]], i64 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i64> [[TMP2]], i64 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i64> [[TMP3]], i64 3, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i64> [[TMP4]], i64 4, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i64> [[TMP5]], i64 5, i32 5
; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> <i64 3, i64 4, i64 5>, i32 2
; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8
; CHECK-NEXT: ret void
@ -142,6 +175,13 @@ define amdgpu_kernel void @i64_2d_load_store_subvec_1(ptr %out) {
define amdgpu_kernel void @i64_2d_load_store_subvec_2(ptr %out) {
; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_2(
; CHECK-SAME: ptr [[OUT:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i64> poison
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i64> [[TMP1]], i64 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i64> [[TMP2]], i64 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i64> [[TMP3]], i64 3, i32 4
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i64> [[TMP4]], i64 4, i32 5
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i64> [[TMP5]], i64 5, i32 6
; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> <i64 3, i64 4, i64 5>, i32 2
; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8
; CHECK-NEXT: ret void
@ -167,14 +207,21 @@ define amdgpu_kernel void @i64_2d_load_store_subvec_3(ptr %out) {
; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <6 x i64> [[TMP10]], i64 1, i32 1
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <6 x i64> [[TMP11]], i64 2, i32 2
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <6 x i64> [[TMP12]], i64 3, i32 3
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <6 x i64> [[TMP13]], i64 4, i32 4
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <6 x i64> [[TMP14]], i64 5, i32 5
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[SEL2]], 3
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i32 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i64> [[TMP15]], i32 [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i32 [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <6 x i64> [[TMP15]], i32 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP5]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP1]], 2
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i32 [[TMP7]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x i64> [[TMP15]], i32 [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x i64> [[TMP6]], i64 [[TMP8]], i64 2
; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP9]], i32 2
; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8
@ -208,14 +255,21 @@ define amdgpu_kernel void @i64_2d_load_store_subvec_3_i64_offset(ptr %out) {
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; CHECK-NEXT: [[SEL3:%.*]] = zext i32 [[SEL2]] to i64
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <6 x i64> [[TMP10]], i64 1, i32 1
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <6 x i64> [[TMP11]], i64 2, i32 2
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <6 x i64> [[TMP12]], i64 3, i32 3
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <6 x i64> [[TMP13]], i64 4, i32 4
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <6 x i64> [[TMP14]], i64 5, i32 5
; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[SEL3]], 3
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i64 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i64> [[TMP15]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP1]], 1
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i64 [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <6 x i64> [[TMP15]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP5]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5>, i64 [[TMP7]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x i64> [[TMP15]], i64 [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x i64> [[TMP6]], i64 [[TMP8]], i64 2
; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP9]], i32 2
; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8
@ -249,14 +303,21 @@ define amdgpu_kernel void @i64_2d_load_store_subvec_4(ptr %out) {
; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i64> poison
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[ALLOCA]], i64 0, i32 0
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i64> [[TMP10]], i64 1, i32 1
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i64> [[TMP11]], i64 2, i32 2
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i64> [[TMP12]], i64 3, i32 4
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i64> [[TMP13]], i64 4, i32 5
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i64> [[TMP14]], i64 5, i32 6
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[SEL2]], 4
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i64> <i64 0, i64 1, i64 2, i64 {{.*}}, i64 3, i64 4, i64 5, i64 {{.*}}>, i32 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i64> [[TMP15]], i32 [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> <i64 0, i64 1, i64 2, i64 {{.*}}, i64 3, i64 4, i64 5, i64 {{.*}}>, i32 [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> [[TMP15]], i32 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP5]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP1]], 2
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i64> <i64 0, i64 1, i64 2, i64 {{.*}}, i64 3, i64 4, i64 5, i64 {{.*}}>, i32 [[TMP7]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i64> [[TMP15]], i32 [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x i64> [[TMP6]], i64 [[TMP8]], i64 2
; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP9]], i32 2
; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8
@ -289,7 +350,20 @@ define amdgpu_kernel void @i32_3d_load_store(ptr %out) {
; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>, i32 [[SEL2]]
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <12 x i32> poison
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <12 x i32> [[ALLOCA]], i32 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x i32> [[TMP13]], i32 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <12 x i32> [[TMP2]], i32 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <12 x i32> [[TMP3]], i32 3, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x i32> [[TMP4]], i32 4, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <12 x i32> [[TMP5]], i32 5, i32 5
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <12 x i32> [[TMP6]], i32 6, i32 6
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <12 x i32> [[TMP7]], i32 7, i32 7
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <12 x i32> [[TMP8]], i32 8, i32 8
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <12 x i32> [[TMP9]], i32 9, i32 9
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <12 x i32> [[TMP10]], i32 10, i32 10
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <12 x i32> [[TMP11]], i32 11, i32 11
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <12 x i32> [[TMP12]], i32 [[SEL2]]
; CHECK-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; CHECK-NEXT: ret void
;
@ -333,8 +407,15 @@ define amdgpu_kernel void @i32_3d_load_store(ptr %out) {
define amdgpu_kernel void @i16_2d_load_store(ptr %out, i32 %sel) {
; CHECK-LABEL: define amdgpu_kernel void @i16_2d_load_store(
; CHECK-SAME: ptr [[OUT:%.*]], i32 [[SEL:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i16> poison
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x i16> [[ALLOCA]], i16 0, i32 0
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <6 x i16> [[TMP7]], i16 1, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i16> [[TMP8]], i16 2, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i16> [[TMP3]], i16 3, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i16> [[TMP4]], i16 4, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i16> [[TMP5]], i16 5, i32 5
; CHECK-NEXT: [[TMP1:%.*]] = add i32 3, [[SEL]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5>, i32 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i16> [[TMP6]], i32 [[TMP1]]
; CHECK-NEXT: store i16 [[TMP2]], ptr [[OUT]], align 2
; CHECK-NEXT: ret void
;
@ -360,8 +441,15 @@ define amdgpu_kernel void @i16_2d_load_store(ptr %out, i32 %sel) {
define amdgpu_kernel void @float_2d_load_store(ptr %out, i32 %sel) {
; CHECK-LABEL: define amdgpu_kernel void @float_2d_load_store(
; CHECK-SAME: ptr [[OUT:%.*]], i32 [[SEL:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x float> poison
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x float> [[ALLOCA]], float 0.000000e+00, i32 0
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <6 x float> [[TMP7]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x float> [[TMP8]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x float> [[TMP4]], float 4.000000e+00, i32 4
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x float> [[TMP5]], float 5.000000e+00, i32 5
; CHECK-NEXT: [[TMP1:%.*]] = add i32 3, [[SEL]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 5.000000e+00>, i32 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x float> [[TMP6]], i32 [[TMP1]]
; CHECK-NEXT: store float [[TMP2]], ptr [[OUT]], align 4
; CHECK-NEXT: ret void
;
@ -387,13 +475,14 @@ define amdgpu_kernel void @float_2d_load_store(ptr %out, i32 %sel) {
define amdgpu_kernel void @ptr_2d_load_store(ptr %out, i32 %sel) {
; CHECK-LABEL: define amdgpu_kernel void @ptr_2d_load_store(
; CHECK-SAME: ptr [[OUT:%.*]], i32 [[SEL:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison
; CHECK-NEXT: [[PTR_0:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 0
; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 1
; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 2
; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 3
; CHECK-NEXT: [[PTR_4:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 4
; CHECK-NEXT: [[PTR_5:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 5
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x ptr> {{.*}}, ptr [[PTR_0]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x ptr> [[ALLOCA]], ptr [[PTR_0]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x ptr> [[TMP1]], ptr [[PTR_1]], i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x ptr> [[TMP2]], ptr [[PTR_2]], i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x ptr> [[TMP3]], ptr [[PTR_3]], i32 3

1
llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
View File

@ -8,6 +8,7 @@ define amdgpu_kernel void @non_constant_index(i32 %arg) {
; CHECK-LABEL: define amdgpu_kernel void @non_constant_index(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[I:%.*]] = freeze <2 x float> poison
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB1]]

3
llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
View File

@ -4,8 +4,9 @@
define i64 @test_pointer_array(i64 %v) {
; OPT-LABEL: @test_pointer_array(
; OPT-NEXT: entry:
; OPT-NEXT: [[A:%.*]] = freeze <3 x ptr> poison
; OPT-NEXT: [[TMP0:%.*]] = inttoptr i64 [[V:%.*]] to ptr
; OPT-NEXT: [[TMP1:%.*]] = insertelement <3 x ptr> undef, ptr [[TMP0]], i32 0
; OPT-NEXT: [[TMP1:%.*]] = insertelement <3 x ptr> [[A]], ptr [[TMP0]], i32 0
; OPT-NEXT: ret i64 [[V]]
;
entry:

29
llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
View File

@ -7,8 +7,9 @@ define void @test_trivial_subvector(<2 x i64> %val.0, <2 x i64> %val.1) {
; CHECK-LABEL: define void @test_trivial_subvector
; CHECK-SAME: (<2 x i64> [[VAL_0:%.*]], <2 x i64> [[VAL_1:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[VAL_0]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> undef, i64 [[TMP0]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[STACK]], i64 [[TMP0]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[VAL_0]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[TMP2]], i32 1
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[VAL_1]], i64 0
@ -54,9 +55,10 @@ define void @test_different_type_subvector(<4 x i32> %val.0, <8 x i16> %val.1, <
; CHECK-LABEL: define void @test_different_type_subvector
; CHECK-SAME: (<4 x i32> [[VAL_0:%.*]], <8 x i16> [[VAL_1:%.*]], <16 x i8> [[VAL_2:%.*]], <128 x i1> [[VAL_3:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[VAL_0]] to <2 x i64>
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> undef, i64 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[STACK]], i64 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP0]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[TMP3]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[TMP1]], i64 0
@ -166,9 +168,10 @@ define void @test_different_type_subvector_fp(<2 x double> %val.0, <4 x float> %
; CHECK-LABEL: define void @test_different_type_subvector_fp
; CHECK-SAME: (<2 x double> [[VAL_0:%.*]], <4 x float> [[VAL_1:%.*]], <8 x half> [[VAL_2:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x double> poison
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VAL_2]] to <2 x double>
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> undef, double [[TMP1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[STACK]], double [[TMP1]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP0]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP2]], double [[TMP3]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i64 0
@ -222,9 +225,10 @@ define void @test_different_type_subvector_ptrs(<2 x ptr addrspace(1)> %val.0, <
; CHECK-LABEL: define void @test_different_type_subvector_ptrs
; CHECK-SAME: (<2 x ptr addrspace(1)> [[VAL_0:%.*]], <4 x ptr addrspace(3)> [[VAL_1:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr addrspace(1)> [[VAL_0]] to <2 x i64>
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> undef, i64 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[STACK]], i64 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP0]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[TMP3]], i32 1
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[TMP1]], i64 0
@ -262,10 +266,11 @@ define void @test_different_type_subvector_ptralloca(<2 x i64> %val.0, <8 x i16>
; CHECK-LABEL: define void @test_different_type_subvector_ptralloca
; CHECK-SAME: (<2 x i64> [[VAL_0:%.*]], <8 x i16> [[VAL_1:%.*]], <2 x ptr addrspace(3)> [[VAL_2:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <8 x ptr addrspace(5)> poison
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VAL_0]] to <4 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = inttoptr <4 x i32> [[TMP0]] to <4 x ptr addrspace(5)>
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x ptr addrspace(5)> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x ptr addrspace(5)> undef, ptr addrspace(5) [[TMP2]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x ptr addrspace(5)> [[STACK]], ptr addrspace(5) [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x ptr addrspace(5)> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x ptr addrspace(5)> [[TMP3]], ptr addrspace(5) [[TMP4]], i32 1
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x ptr addrspace(5)> [[TMP1]], i64 2
@ -331,8 +336,9 @@ define void @test_out_of_bounds_subvec(<2 x i64> %val) {
; CHECK-LABEL: define void @test_out_of_bounds_subvec
; CHECK-SAME: (<2 x i64> [[VAL:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[VAL]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> undef, i64 [[TMP0]], i32 3
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[STACK]], i64 [[TMP0]], i32 3
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[VAL]], i64 1
; CHECK-NEXT: ret void
;
@ -374,9 +380,14 @@ entry:
define void @store_2xi32_into_double(double %foo) {
; CHECK-LABEL: define void @store_2xi32_into_double
; CHECK-SAME: (double [[FOO:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <9 x double> poison
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <9 x double> [[ALLOCA]], double 0x5F0000005E, i32 0
; CHECK-NEXT: [[DUMMYUSER0:%.*]] = freeze double 0x5F0000005E
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <9 x double> [[TMP1]], double 0x6700000066, i32 4
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <9 x double> [[TMP2]], double 0x6900000068, i32 5
; CHECK-NEXT: [[DUMMYUSER1:%.*]] = freeze double 0x6700000066
; CHECK-NEXT: [[DUMMYUSER2:%.*]] = freeze double 0x6900000068
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <9 x double> [[TMP3]], double 0x6F0000006E, i32 8
; CHECK-NEXT: [[DUMMYUSER3:%.*]] = freeze double 0x6F0000006E
; CHECK-NEXT: ret void
;
@ -407,6 +418,7 @@ define <4 x i16> @nonconst_indexes(i1 %cond, i32 %otheridx, <4 x i16> %store) #0
; CHECK-LABEL: define <4 x i16> @nonconst_indexes
; CHECK-SAME: (i1 [[COND:%.*]], i32 [[OTHERIDX:%.*]], <4 x i16> [[STORE:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DATA:%.*]] = freeze <16 x i16> poison
; CHECK-NEXT: br i1 [[COND]], label [[THEN:%.*]], label [[ELSE:%.*]]
; CHECK: then:
; CHECK-NEXT: br label [[FINALLY:%.*]]
@ -416,7 +428,7 @@ define <4 x i16> @nonconst_indexes(i1 %cond, i32 %otheridx, <4 x i16> %store) #0
; CHECK-NEXT: [[INDEX_1:%.*]] = phi i32 [ 0, [[THEN]] ], [ [[OTHERIDX]], [[ELSE]] ]
; CHECK-NEXT: [[INDEX_2:%.*]] = phi i32 [ 2, [[THEN]] ], [ [[OTHERIDX]], [[ELSE]] ]
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i16> [[STORE]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i16> undef, i16 [[TMP0]], i32 [[INDEX_1]]
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i16> [[DATA]], i16 [[TMP0]], i32 [[INDEX_1]]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX_1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i16> [[STORE]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i16> [[TMP1]], i16 [[TMP3]], i32 [[TMP2]]
@ -465,8 +477,9 @@ define void @test_smaller_alloca_store(<4 x i32> %store1, <4 x i32> %store2) {
; CHECK-LABEL: define void @test_smaller_alloca_store
; CHECK-SAME: (<4 x i32> [[STORE1:%.*]], <4 x i32> [[STORE2:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RES:%.*]] = freeze <3 x i32> poison
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> [[STORE1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> undef, i32 [[TMP0]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> [[RES]], i32 [[TMP0]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[STORE1]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i32> [[TMP1]], i32 [[TMP2]], i32 1
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[STORE1]], i64 2

13
llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
View File

@ -43,12 +43,13 @@ entry:
; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]
; GCN: store_dwordx4 v{{.+}},
; OPT: %0 = insertelement <4 x float> undef, float 1.000000e+00, i32 %sel2
; OPT: %0 = insertelement <4 x float> poison, float 1.000000e+00, i32 %sel2
; OPT: store <4 x float> %0, ptr addrspace(1) %out, align 4
define amdgpu_kernel void @float4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {
entry:
%alloca = alloca <4 x float>, align 16, addrspace(5)
store <4 x float> poison, ptr addrspace(5) %alloca
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
%y = tail call i32 @llvm.amdgcn.workitem.id.y()
%c1 = icmp uge i32 %x, 3
@ -95,7 +96,8 @@ entry:
; GCN-NOT: buffer_
; GCN: s_mov_b64 s[{{[0-9:]+}}], 0xffff
; OPT: %0 = insertelement <4 x half> undef, half 0xH3C00, i32 %sel2
; OPT: %alloca = freeze <4 x half> poison
; OPT: %0 = insertelement <4 x half> %alloca, half 0xH3C00, i32 %sel2
; OPT: store <4 x half> %0, ptr addrspace(1) %out, align 2
define amdgpu_kernel void @half4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {
@ -147,7 +149,8 @@ entry:
; GCN-NOT: buffer_
; GCN: s_mov_b64 s[{{[0-9:]+}}], 0xffff
; OPT: %0 = insertelement <4 x i16> undef, i16 1, i32 %sel2
; OPT: %alloca = freeze <4 x i16> poison
; OPT: %0 = insertelement <4 x i16> %alloca, i16 1, i32 %sel2
; OPT: store <4 x i16> %0, ptr addrspace(1) %out, align 2
define amdgpu_kernel void @short4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {
@ -170,7 +173,9 @@ entry:
; OPT-LABEL: define i64 @ptr_alloca_bitcast
; GCN-NOT: buffer_
; GCN: v_mov_b32_e32 v1, 0
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64
; OPT: ret i64 undef

6
llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
View File

@ -31,6 +31,7 @@ define amdgpu_kernel void @i32_24_elements(ptr %out) #0 {
; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison
; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]
; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; RATIO2-NEXT: ret void
@ -81,6 +82,7 @@ define amdgpu_kernel void @i32_24_elements_attrib(ptr %out) #1 {
; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison
; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]
; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; DEFAULT-NEXT: ret void
@ -93,6 +95,7 @@ define amdgpu_kernel void @i32_24_elements_attrib(ptr %out) #1 {
; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison
; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]
; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; RATIO2-NEXT: ret void
@ -143,6 +146,7 @@ define amdgpu_kernel void @i32_16_elements(ptr %out) #0 {
; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison
; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <16 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43>, i32 [[SEL2]]
; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; DEFAULT-NEXT: ret void
@ -155,6 +159,7 @@ define amdgpu_kernel void @i32_16_elements(ptr %out) #0 {
; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison
; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <16 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43>, i32 [[SEL2]]
; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; RATIO2-NEXT: ret void
@ -224,6 +229,7 @@ define amdgpu_kernel void @i32_16_elements_attrib(ptr %out) #2 {
; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3
; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2
; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]
; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison
; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <16 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43>, i32 [[SEL2]]
; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4
; RATIO2-NEXT: ret void

32
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
View File

@ -2101,16 +2101,18 @@ define void @crash_lshlrevb16_not_reg_op() {
; NOSDWA-LABEL: crash_lshlrevb16_not_reg_op:
; NOSDWA: ; %bb.0: ; %bb0
; NOSDWA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; NOSDWA-NEXT: s_bitset1_b32 s4, 8
; NOSDWA-NEXT: s_and_b32 s6, s4, 0x1ff
; NOSDWA-NEXT: s_mov_b64 s[4:5], 0
; NOSDWA-NEXT: s_and_b64 vcc, exec, -1
; NOSDWA-NEXT: .LBB22_1: ; %bb1
; NOSDWA-NEXT: ; =>This Inner Loop Header: Depth=1
; NOSDWA-NEXT: s_lshl_b32 s6, s4, 3
; NOSDWA-NEXT: s_lshl_b32 s7, s4, 3
; NOSDWA-NEXT: v_mov_b32_e32 v0, s4
; NOSDWA-NEXT: s_lshr_b32 s6, 0x100, s6
; NOSDWA-NEXT: s_lshr_b32 s7, s6, s7
; NOSDWA-NEXT: v_mov_b32_e32 v1, s5
; NOSDWA-NEXT: s_mov_b64 s[4:5], 1
; NOSDWA-NEXT: v_mov_b32_e32 v2, s6
; NOSDWA-NEXT: v_mov_b32_e32 v2, s7
; NOSDWA-NEXT: flat_store_byte v[0:1], v2
; NOSDWA-NEXT: s_mov_b64 vcc, vcc
; NOSDWA-NEXT: s_cbranch_vccnz .LBB22_1
@ -2121,16 +2123,18 @@ define void @crash_lshlrevb16_not_reg_op() {
; GFX89-LABEL: crash_lshlrevb16_not_reg_op:
; GFX89: ; %bb.0: ; %bb0
; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-NEXT: s_bitset1_b32 s4, 8
; GFX89-NEXT: s_and_b32 s6, s4, 0x1ff
; GFX89-NEXT: s_mov_b64 s[4:5], 0
; GFX89-NEXT: s_and_b64 vcc, exec, -1
; GFX89-NEXT: .LBB22_1: ; %bb1
; GFX89-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX89-NEXT: s_lshl_b32 s6, s4, 3
; GFX89-NEXT: s_lshl_b32 s7, s4, 3
; GFX89-NEXT: v_mov_b32_e32 v0, s4
; GFX89-NEXT: s_lshr_b32 s6, 0x100, s6
; GFX89-NEXT: s_lshr_b32 s7, s6, s7
; GFX89-NEXT: v_mov_b32_e32 v1, s5
; GFX89-NEXT: s_mov_b64 s[4:5], 1
; GFX89-NEXT: v_mov_b32_e32 v2, s6
; GFX89-NEXT: v_mov_b32_e32 v2, s7
; GFX89-NEXT: flat_store_byte v[0:1], v2
; GFX89-NEXT: s_mov_b64 vcc, vcc
; GFX89-NEXT: s_cbranch_vccnz .LBB22_1
@ -2141,16 +2145,18 @@ define void @crash_lshlrevb16_not_reg_op() {
; GFX9-LABEL: crash_lshlrevb16_not_reg_op:
; GFX9: ; %bb.0: ; %bb0
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_bitset1_b32 s4, 8
; GFX9-NEXT: s_and_b32 s6, s4, 0x1ff
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_and_b64 vcc, exec, -1
; GFX9-NEXT: .LBB22_1: ; %bb1
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_lshl_b32 s6, s4, 3
; GFX9-NEXT: s_lshl_b32 s7, s4, 3
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_lshr_b32 s6, 0x100, s6
; GFX9-NEXT: s_lshr_b32 s7, s6, s7
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_mov_b64 s[4:5], 1
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7
; GFX9-NEXT: flat_store_byte v[0:1], v2
; GFX9-NEXT: s_mov_b64 vcc, vcc
; GFX9-NEXT: s_cbranch_vccnz .LBB22_1
@ -2161,14 +2167,16 @@ define void @crash_lshlrevb16_not_reg_op() {
; GFX10-LABEL: crash_lshlrevb16_not_reg_op:
; GFX10: ; %bb.0: ; %bb0
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b64 s[4:5], 0
; GFX10-NEXT: s_bitset1_b32 s4, 8
; GFX10-NEXT: s_mov_b32 vcc_lo, exec_lo
; GFX10-NEXT: s_and_b32 s6, s4, 0x1ff
; GFX10-NEXT: s_mov_b64 s[4:5], 0
; GFX10-NEXT: .LBB22_1: ; %bb1
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_lshl_b32 s6, s4, 3
; GFX10-NEXT: s_lshl_b32 s7, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_lshr_b32 s4, 0x100, s6
; GFX10-NEXT: s_lshr_b32 s4, s6, s7
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_mov_b64 s[4:5], 1
; GFX10-NEXT: flat_store_byte v[0:1], v2

6
llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
View File

@ -73,7 +73,7 @@ entry:
; OPT-LABEL: @vector_write_read_bitcast_to_float(
; OPT-NOT: alloca
; OPT: bb2:
; OPT: %promotealloca = phi <6 x float> [ undef, %bb ], [ %0, %bb2 ]
; OPT: %promotealloca = phi <6 x float> [ zeroinitializer, %bb ], [ %0, %bb2 ]
; OPT: %0 = insertelement <6 x float> %promotealloca, float %tmp71, i32 %tmp10
; OPT: .preheader:
; OPT: %bc = bitcast <6 x float> %0 to <6 x i32>
@ -133,7 +133,7 @@ bb15: ; preds = %.preheader
; OPT-LABEL: @vector_write_read_bitcast_to_double(
; OPT-NOT: alloca
; OPT: bb2:
; OPT: %promotealloca = phi <6 x double> [ undef, %bb ], [ %0, %bb2 ]
; OPT: %promotealloca = phi <6 x double> [ zeroinitializer, %bb ], [ %0, %bb2 ]
; OPT: %0 = insertelement <6 x double> %promotealloca, double %tmp71, i32 %tmp10
; OPT: .preheader:
; OPT: %bc = bitcast <6 x double> %0 to <6 x i64>
@ -194,7 +194,7 @@ bb15: ; preds = %.preheader
; OPT-LABEL: @vector_write_read_bitcast_to_i64(
; OPT-NOT: alloca
; OPT: bb2:
; OPT: %promotealloca = phi <6 x i64> [ undef, %bb ], [ %0, %bb2 ]
; OPT: %promotealloca = phi <6 x i64> [ zeroinitializer, %bb ], [ %0, %bb2 ]
; OPT: %0 = insertelement <6 x i64> %promotealloca, i64 %tmp6, i32 %tmp9
; OPT: .preheader:
; OPT: %1 = extractelement <6 x i64> %0, i32 %tmp18

28
llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
View File

@ -8,10 +8,12 @@ target datalayout = "A5"
; OPT: <8 x i64>
; LIMIT32: alloca
; LIMIT32-NOT: <8 x i64>
define amdgpu_kernel void @alloca_8xi64_max1024(ptr addrspace(1) %out, i32 %index) #0 {
define amdgpu_kernel void @alloca_8xi64_max1024(ptr addrspace(1) %out, i32 %index, i32 %index1) #0 {
entry:
%tmp = alloca [8 x i64], addrspace(5)
store i64 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i64 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [8 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i64, ptr addrspace(5) %tmp1
store i64 %tmp2, ptr addrspace(1) %out
@ -38,10 +40,12 @@ entry:
; OPT: <16 x i64>
; LIMIT32: alloca
; LIMIT32-NOT: <16 x i64>
define amdgpu_kernel void @alloca_16xi64_max512(ptr addrspace(1) %out, i32 %index) #1 {
define amdgpu_kernel void @alloca_16xi64_max512(ptr addrspace(1) %out, i32 %index, i32 %index1) #1 {
entry:
%tmp = alloca [16 x i64], addrspace(5)
store i64 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i64 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [16 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i64, ptr addrspace(5) %tmp1
store i64 %tmp2, ptr addrspace(1) %out
@ -83,10 +87,12 @@ entry:
; OPT: <9 x i128>
; LIMIT32: alloca
; LIMIT32-NOT: <9 x i128>
define amdgpu_kernel void @alloca_9xi128_max256(ptr addrspace(1) %out, i32 %index) #2 {
define amdgpu_kernel void @alloca_9xi128_max256(ptr addrspace(1) %out, i32 %index, i32 %index1) #2 {
entry:
%tmp = alloca [9 x i128], addrspace(5)
store i128 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i128], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i128 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [9 x i128], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i128, ptr addrspace(5) %tmp1
store i128 %tmp2, ptr addrspace(1) %out
@ -98,10 +104,12 @@ entry:
; OPT: <16 x i128>
; LIMIT32: alloca
; LIMIT32-NOT: <16 x i128>
define amdgpu_kernel void @alloca_16xi128_max256(ptr addrspace(1) %out, i32 %index) #2 {
define amdgpu_kernel void @alloca_16xi128_max256(ptr addrspace(1) %out, i32 %index, i32 %index1) #2 {
entry:
%tmp = alloca [16 x i128], addrspace(5)
store i128 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i128], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i128 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [16 x i128], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i128, ptr addrspace(5) %tmp1
store i128 %tmp2, ptr addrspace(1) %out
@ -113,10 +121,12 @@ entry:
; OPT-NOT: <9 x i256>
; LIMIT32: alloca
; LIMIT32-NOT: <9 x i256>
define amdgpu_kernel void @alloca_9xi256_max256(ptr addrspace(1) %out, i32 %index) #2 {
define amdgpu_kernel void @alloca_9xi256_max256(ptr addrspace(1) %out, i32 %index, i32 %index1) #2 {
entry:
%tmp = alloca [9 x i256], addrspace(5)
store i256 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i256], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i128 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [9 x i256], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i256, ptr addrspace(5) %tmp1
store i256 %tmp2, ptr addrspace(1) %out
@ -128,10 +138,12 @@ entry:
; OPT: <9 x i64>
; LIMIT32: alloca
; LIMIT32-NOT: <9 x i64>
define amdgpu_kernel void @alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #2 {
define amdgpu_kernel void @alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index, i32 %index1) #2 {
entry:
%tmp = alloca [9 x i64], addrspace(5)
store i64 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i64 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [9 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i64, ptr addrspace(5) %tmp1
store i64 %tmp2, ptr addrspace(1) %out
@ -158,10 +170,12 @@ entry:
; OPT: <9 x i64>
; LIMIT32: alloca
; LIMIT32-NOT: <9 x i64>
define void @alwaysinlined_func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #3 {
define void @alwaysinlined_func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index, i32 %index1) #3 {
entry:
%tmp = alloca [9 x i64], addrspace(5)
store i64 0, ptr addrspace(5) %tmp
%gep0 = getelementptr [8 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index1
store i64 1, ptr addrspace(5) %gep0
%tmp1 = getelementptr [9 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index
%tmp2 = load i64, ptr addrspace(5) %tmp1
store i64 %tmp2, ptr addrspace(1) %out