[X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D155147
This commit is contained in:
Freddy Ye
parent
e1be36c649
commit
c6f66de21a
@ -817,6 +817,10 @@ X86 Support
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* Support intrinsic of ``_mm256_sha512msg1_epi64``.
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* Support intrinsic of ``_mm256_sha512msg2_epi64``.
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* Support intrinsic of ``_mm256_sha512rnds2_epi64``.
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- Support ISA of ``SM3``.
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* Support intrinsic of ``_mm_sm3msg1_epi32``.
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* Support intrinsic of ``_mm_sm3msg2_epi32``.
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* Support intrinsic of ``_mm_sm3rnds2_epi32``.
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Arm and AArch64 Support
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^^^^^^^^^^^^^^^^^^^^^^^
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@ -2146,6 +2146,11 @@ TARGET_HEADER_BUILTIN(_InterlockedIncrement64, "WiWiD*", "nh", INTRIN_H, ALL
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TARGET_HEADER_BUILTIN(_InterlockedOr64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(_InterlockedXor64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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// SM3
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TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
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TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
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TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3")
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#undef BUILTIN
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#undef TARGET_BUILTIN
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#undef TARGET_HEADER_BUILTIN
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@ -5058,6 +5058,8 @@ def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
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def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
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def msha512 : Flag<["-"], "msha512">, Group<m_x86_Features_Group>;
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def mno_sha512 : Flag<["-"], "mno-sha512">, Group<m_x86_Features_Group>;
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def msm3 : Flag<["-"], "msm3">, Group<m_x86_Features_Group>;
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def mno_sm3 : Flag<["-"], "mno-sm3">, Group<m_x86_Features_Group>;
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def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
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def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
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def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;
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@ -265,6 +265,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasSHA512 = true;
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} else if (Feature == "+shstk") {
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HasSHSTK = true;
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} else if (Feature == "+sm3") {
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HasSM3 = true;
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} else if (Feature == "+movbe") {
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HasMOVBE = true;
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} else if (Feature == "+sgx") {
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@ -776,6 +778,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("__SHSTK__");
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if (HasSGX)
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Builder.defineMacro("__SGX__");
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if (HasSM3)
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Builder.defineMacro("__SM3__");
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if (HasPREFETCHI)
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Builder.defineMacro("__PREFETCHI__");
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if (HasPREFETCHWT1)
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@ -1005,6 +1009,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
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.Case("sha", true)
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.Case("sha512", true)
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.Case("shstk", true)
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.Case("sm3", true)
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.Case("sse", true)
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.Case("sse2", true)
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.Case("sse3", true)
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@ -1111,6 +1116,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
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.Case("sha", HasSHA)
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.Case("sha512", HasSHA512)
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.Case("shstk", HasSHSTK)
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.Case("sm3", HasSM3)
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.Case("sse", SSELevel >= SSE1)
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.Case("sse2", SSELevel >= SSE2)
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.Case("sse3", SSELevel >= SSE3)
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@ -114,6 +114,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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bool HasSHA = false;
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bool HasSHA512 = false;
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bool HasSHSTK = false;
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bool HasSM3 = false;
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bool HasSGX = false;
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bool HasCX8 = false;
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bool HasCX16 = false;
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@ -205,6 +205,7 @@ set(x86_files
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sgxintrin.h
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sha512intrin.h
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shaintrin.h
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sm3intrin.h
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smmintrin.h
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tbmintrin.h
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tmmintrin.h
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@ -274,6 +274,11 @@
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#include <sha512intrin.h>
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#endif
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#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
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defined(__SM3__)
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#include <sm3intrin.h>
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#endif
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#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
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defined(__RDPID__)
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/// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).
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238
clang/lib/Headers/sm3intrin.h
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238
clang/lib/Headers/sm3intrin.h
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@ -0,0 +1,238 @@
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/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
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#endif // __IMMINTRIN_H
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#ifndef __SM3INTRIN_H
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#define __SM3INTRIN_H
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#define __DEFAULT_FN_ATTRS128 \
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__attribute__((__always_inline__, __nodebug__, __target__("sm3"), \
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__min_vector_width__(128)))
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/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
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/// intrinsic performs an initial calculation for the next four SM3 message
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/// words. The calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
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///
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/// \param __A
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/// A 128-bit vector of [4 x int].
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/// \param __B
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/// A 128-bit vector of [4 x int].
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/// \param __C
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/// A 128-bit vector of [4 x int].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// DEFINE ROL32(dword, n) {
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/// count := n % 32
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/// dest := (dword << count) | (dword >> (32 - count))
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/// RETURN dest
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/// }
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/// DEFINE P1(x) {
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/// RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
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/// }
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/// W[0] := __C.dword[0]
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/// W[1] := __C.dword[1]
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/// W[2] := __C.dword[2]
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/// W[3] := __C.dword[3]
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/// W[7] := __A.dword[0]
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/// W[8] := __A.dword[1]
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/// W[9] := __A.dword[2]
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/// W[10] := __A.dword[3]
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/// W[13] := __B.dword[0]
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/// W[14] := __B.dword[1]
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/// W[15] := __B.dword[2]
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/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
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/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
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/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
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/// TMP3 := W[10] ^ W[3]
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/// dst.dword[0] := P1(TMP0)
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/// dst.dword[1] := P1(TMP1)
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/// dst.dword[2] := P1(TMP2)
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/// dst.dword[3] := P1(TMP3)
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/// dst[MAX:128] := 0
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/// \endcode
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static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
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__m128i __B,
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__m128i __C) {
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return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
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(__v4su)__C);
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}
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/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
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/// intrinsic performs the final calculation for the next four SM3 message
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/// words. The calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
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///
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/// \param __A
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/// A 128-bit vector of [4 x int].
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/// \param __B
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/// A 128-bit vector of [4 x int].
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/// \param __C
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/// A 128-bit vector of [4 x int].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// DEFINE ROL32(dword, n) {
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/// count := n % 32
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/// dest := (dword << count) | (dword >> (32-count))
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/// RETURN dest
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/// }
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/// WTMP[0] := __A.dword[0]
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/// WTMP[1] := __A.dword[1]
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/// WTMP[2] := __A.dword[2]
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/// WTMP[3] := __A.dword[3]
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/// W[3] := __B.dword[0]
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/// W[4] := __B.dword[1]
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/// W[5] := __B.dword[2]
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/// W[6] := __B.dword[3]
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/// W[10] := __C.dword[0]
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/// W[11] := __C.dword[1]
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/// W[12] := __C.dword[2]
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/// W[13] := __C.dword[3]
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/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
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/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
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/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
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/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
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/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
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/// dst.dword[0] := W[16]
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/// dst.dword[1] := W[17]
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/// dst.dword[2] := W[18]
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/// dst.dword[3] := W[19]
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/// dst[MAX:128] := 0
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/// \endcode
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static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
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__m128i __B,
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__m128i __C) {
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return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
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(__v4su)__C);
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}
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/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
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/// (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
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/// from \a __B and a pre-computed words from the \a __C. \a __A with
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/// initial SM3 state of (C, D, G, H) assumes input of non-rotated left
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/// variables from previous state. The updated SM3 state (A, B, E, F) is
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/// written to \a __A. The \a imm8 should contain the even round number
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/// for the first of the two rounds computed by this instruction. The
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/// computation masks the \a imm8 value by AND’ing it with 0x3E so that only
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/// even round numbers from 0 through 62 are used for this operation. The
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/// calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
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/// imm8) \endcode
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///
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/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
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///
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/// \param __A
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/// A 128-bit vector of [4 x int].
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/// \param __B
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/// A 128-bit vector of [4 x int].
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/// \param __C
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/// A 128-bit vector of [4 x int].
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/// \param imm8
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/// A 8-bit constant integer.
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// DEFINE ROL32(dword, n) {
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/// count := n % 32
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/// dest := (dword << count) | (dword >> (32-count))
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/// RETURN dest
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/// }
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/// DEFINE P0(dword) {
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/// RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
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/// }
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/// DEFINE FF(x,y,z, round){
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/// IF round < 16
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/// RETURN (x ^ y ^ z)
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/// ELSE
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/// RETURN (x & y) | (x & z) | (y & z)
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/// FI
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/// }
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/// DEFINE GG(x, y, z, round){
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/// IF round < 16
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/// RETURN (x ^ y ^ z)
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/// ELSE
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/// RETURN (x & y) | (~x & z)
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/// FI
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/// }
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/// A[0] := __B.dword[3]
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/// B[0] := __B.dword[2]
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/// C[0] := __A.dword[3]
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/// D[0] := __A.dword[2]
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/// E[0] := __B.dword[1]
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/// F[0] := __B.dword[0]
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/// G[0] := __A.dword[1]
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/// H[0] := __A.dword[0]
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/// W[0] := __C.dword[0]
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/// W[1] := __C.dword[1]
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/// W[4] := __C.dword[2]
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/// W[5] := __C.dword[3]
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/// C[0] := ROL32(C[0], 9)
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/// D[0] := ROL32(D[0], 9)
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/// G[0] := ROL32(G[0], 19)
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/// H[0] := ROL32(H[0], 19)
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/// ROUND := __D & 0x3E
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/// IF ROUND < 16
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/// CONST := 0x79CC4519
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/// ELSE
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/// CONST := 0x7A879D8A
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/// FI
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/// CONST := ROL32(CONST,ROUND)
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/// FOR i:= 0 to 1
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/// S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
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/// S2 := S1 ^ ROL32(A[i], 12)
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/// T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
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/// T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
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/// D[i+1] := C[i]
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/// C[i+1] := ROL32(B[i],9)
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/// B[i+1] := A[i]
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/// A[i+1] := T1
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/// H[i+1] := G[i]
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/// G[i+1] := ROL32(F[i], 19)
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/// F[i+1] := E[i]
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/// E[i+1] := P0(T2)
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/// CONST := ROL32(CONST, 1)
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/// ENDFOR
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/// dst.dword[3] := A[2]
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/// dst.dword[2] := B[2]
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/// dst.dword[1] := E[2]
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/// dst.dword[0] := F[2]
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/// dst[MAX:128] := 0
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/// \endcode
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#define _mm_sm3rnds2_epi32(A, B, C, D) \
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(__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
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#undef __DEFAULT_FN_ATTRS128
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#endif // __SM3INTRIN_H
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@ -6296,6 +6296,7 @@ bool Sema::CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
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case X86::BI__builtin_ia32_pternlogq128_maskz:
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case X86::BI__builtin_ia32_pternlogq256_mask:
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case X86::BI__builtin_ia32_pternlogq256_maskz:
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case X86::BI__builtin_ia32_vsm3rnds2:
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i = 3; l = 0; u = 255;
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break;
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case X86::BI__builtin_ia32_gatherpfdpd:
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22
clang/test/CodeGen/X86/sm3-builtins.c
Normal file
22
clang/test/CodeGen/X86/sm3-builtins.c
Normal file
@ -0,0 +1,22 @@
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// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
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// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
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#include <immintrin.h>
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__m128i test_mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) {
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// CHECK-LABEL: @test_mm_sm3msg1_epi32(
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// CHECK: call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
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return _mm_sm3msg1_epi32(__A, __B, __C);
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}
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__m128i test_mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) {
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// CHECK-LABEL: @test_mm_sm3msg2_epi32(
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// CHECK: call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
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return _mm_sm3msg2_epi32(__A, __B, __C);
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}
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|
||||
__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
|
||||
// CHECK-LABEL: @test_mm_sm3rnds2_epi32(
|
||||
// CHECK: call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 127)
|
||||
return _mm_sm3rnds2_epi32(__A, __B, __C, 127);
|
||||
}
|
||||
7
clang/test/CodeGen/X86/sm3-error.c
Normal file
7
clang/test/CodeGen/X86/sm3-error.c
Normal file
@ -0,0 +1,7 @@
|
||||
// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +sm3 -emit-llvm -fsyntax-only -verify
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
|
||||
return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
|
||||
}
|
||||
@ -54,9 +54,9 @@ void __attribute__((target("arch=x86-64-v4"))) x86_64_v4(void) {}
|
||||
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
|
||||
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
|
||||
// CHECK-NOT: tune-cpu
|
||||
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
|
||||
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
|
||||
// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
|
||||
// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
|
||||
// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
|
||||
// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
|
||||
// CHECK-NOT: tune-cpu
|
||||
// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"
|
||||
|
||||
@ -354,6 +354,11 @@
|
||||
// SHA512: "-target-feature" "+sha512"
|
||||
// NO-SHA512: "-target-feature" "-sha512"
|
||||
|
||||
// RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s
|
||||
// RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s
|
||||
// SM3: "-target-feature" "+sm3"
|
||||
// NO-SM3: "-target-feature" "-sm3"
|
||||
|
||||
// RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
|
||||
// RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
|
||||
// CRC32: "-target-feature" "+crc32"
|
||||
|
||||
@ -673,6 +673,20 @@
|
||||
// SHA512NOAVX-NOT: #define __AVX__ 1
|
||||
// SHA512NOAVX-NOT: #define __SHA512__ 1
|
||||
|
||||
// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -x c -E -dM -o - %s | FileCheck -check-prefix=SM3 %s
|
||||
|
||||
// SM3: #define __AVX__ 1
|
||||
// SM3: #define __SM3__ 1
|
||||
|
||||
// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-sm3 -x c -E -dM -o - %s | FileCheck -check-prefix=NOSM3 %s
|
||||
|
||||
// NOSM3-NOT: #define __SM3__ 1
|
||||
|
||||
// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -mno-avx -x c -E -dM -o - %s | FileCheck -check-prefix=SM3NOAVX %s
|
||||
|
||||
// SM3NOAVX-NOT: #define __SM3__ 1
|
||||
// SM3NOAVX-NOT: #define __AVX__ 1
|
||||
|
||||
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
|
||||
|
||||
// CRC32: #define __CRC32__ 1
|
||||
|
||||
@ -280,6 +280,7 @@ Changes to the X86 Backend
|
||||
``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
|
||||
* Add support for the ``PBNDKB`` instruction.
|
||||
* Support ISA of ``SHA512``.
|
||||
* Support ISA of ``SM3``.
|
||||
|
||||
Changes to the OCaml bindings
|
||||
-----------------------------
|
||||
|
||||
@ -5527,6 +5527,25 @@ def int_x86_vcvtneps2bf16256
|
||||
DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8f32_ty], [IntrNoMem]>;
|
||||
}
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SM3 intrinsics
|
||||
let TargetPrefix = "x86" in {
|
||||
def int_x86_vsm3msg1
|
||||
: ClangBuiltin<"__builtin_ia32_vsm3msg1">,
|
||||
DefaultAttrsIntrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_vsm3msg2
|
||||
: ClangBuiltin<"__builtin_ia32_vsm3msg2">,
|
||||
DefaultAttrsIntrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_vsm3rnds2
|
||||
: ClangBuiltin<"__builtin_ia32_vsm3rnds2">,
|
||||
DefaultAttrsIntrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
|
||||
[ImmArg<ArgIndex<3>>, IntrNoMem]>;
|
||||
}
|
||||
//===----------------------------------------------------------------------===//
|
||||
// RAO-INT intrinsics
|
||||
let TargetPrefix = "x86" in {
|
||||
def int_x86_aadd32
|
||||
|
||||
@ -221,6 +221,7 @@ X86_FEATURE (XSAVES, "xsaves")
|
||||
X86_FEATURE (HRESET, "hreset")
|
||||
X86_FEATURE (RAOINT, "raoint")
|
||||
X86_FEATURE (AVX512FP16, "avx512fp16")
|
||||
X86_FEATURE (SM3, "sm3")
|
||||
X86_FEATURE (AMX_FP16, "amx-fp16")
|
||||
X86_FEATURE (CMPCCXADD, "cmpccxadd")
|
||||
X86_FEATURE (AVXNECONVERT, "avxneconvert")
|
||||
|
||||
@ -245,6 +245,9 @@ def FeatureSHA512 : SubtargetFeature<"sha512", "HasSHA512", "true",
|
||||
// using Shadow Stack
|
||||
def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
|
||||
"Support CET Shadow-Stack instructions">;
|
||||
def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true",
|
||||
"Support SM3 instructions",
|
||||
[FeatureAVX]>;
|
||||
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
|
||||
"Support PRFCHW instructions">;
|
||||
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
|
||||
|
||||
@ -969,6 +969,7 @@ def HasADX : Predicate<"Subtarget->hasADX()">;
|
||||
def HasSHA : Predicate<"Subtarget->hasSHA()">;
|
||||
def HasSHA512 : Predicate<"Subtarget->hasSHA512()">;
|
||||
def HasSGX : Predicate<"Subtarget->hasSGX()">;
|
||||
def HasSM3 : Predicate<"Subtarget->hasSM3()">;
|
||||
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
|
||||
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
|
||||
def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
|
||||
|
||||
@ -8317,3 +8317,44 @@ def VSHA512RNDS2rr : I<0xcb, MRMSrcReg, (outs VR256:$dst),
|
||||
(int_x86_vsha512rnds2 VR256:$src1, VR256:$src2, VR128:$src3))]>,
|
||||
VEX_L, VEX_4V, T8XD, Sched<[WriteVecIMul]>;
|
||||
}
|
||||
|
||||
// FIXME: Is there a better scheduler class for SM3 than WriteVecIMul?
|
||||
let Predicates = [HasSM3], Constraints = "$src1 = $dst" in {
|
||||
multiclass SM3_Base<string OpStr> {
|
||||
def rr : I<0xda, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
!strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR128:$dst,
|
||||
(!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
|
||||
VR128:$src2, VR128:$src3))]>,
|
||||
Sched<[WriteVecIMul]>, VEX_4V;
|
||||
def rm : I<0xda, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, i128mem:$src3),
|
||||
!strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR128:$dst,
|
||||
(!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
|
||||
VR128:$src2, (loadv4i32 addr:$src3)))]>,
|
||||
Sched<[WriteVecIMul]>, VEX_4V;
|
||||
}
|
||||
|
||||
multiclass VSM3RNDS2_Base {
|
||||
def rr : Ii8<0xde, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, VR128:$src3, i32u8imm:$src4),
|
||||
"vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_vsm3rnds2 VR128:$src1,
|
||||
VR128:$src2, VR128:$src3, timm:$src4))]>,
|
||||
Sched<[WriteVecIMul]>;
|
||||
def rm : Ii8<0xde, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, i128mem:$src3, i32u8imm:$src4),
|
||||
"vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_vsm3rnds2 VR128:$src1,
|
||||
VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
|
||||
Sched<[WriteVecIMul]>;
|
||||
}
|
||||
}
|
||||
|
||||
defm VSM3MSG1 : SM3_Base<"vsm3msg1">, T8PS;
|
||||
defm VSM3MSG2 : SM3_Base<"vsm3msg2">, T8PD;
|
||||
defm VSM3RNDS2 : VSM3RNDS2_Base, VEX_4V, TAPD;
|
||||
|
||||
@ -1747,6 +1747,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
||||
bool HasLeaf7Subleaf1 =
|
||||
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
|
||||
Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
|
||||
Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
|
||||
Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
|
||||
Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
|
||||
Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
|
||||
|
||||
@ -613,6 +613,7 @@ constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
|
||||
constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
|
||||
constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
|
||||
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
|
||||
constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
|
||||
|
||||
// AVX512 features.
|
||||
constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
|
||||
|
||||
34
llvm/test/CodeGen/X86/sm3-intrinsics.ll
Normal file
34
llvm/test/CodeGen/X86/sm3-intrinsics.ll
Normal file
@ -0,0 +1,34 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
|
||||
; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
|
||||
|
||||
define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
|
||||
; CHECK-LABEL: test_int_x86_vsm3msg1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
|
||||
ret <4 x i32> %ret
|
||||
}
|
||||
declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
|
||||
|
||||
define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
|
||||
; CHECK-LABEL: test_int_x86_vsm3msg2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
|
||||
ret <4 x i32> %ret
|
||||
}
|
||||
declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
|
||||
|
||||
define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
|
||||
; CHECK-LABEL: test_int_x86_vsm3rnds2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127)
|
||||
ret <4 x i32> %ret
|
||||
}
|
||||
declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D)
|
||||
|
||||
87
llvm/test/MC/Disassembler/X86/sm3-32.txt
Normal file
87
llvm/test/MC/Disassembler/X86/sm3-32.txt
Normal file
@ -0,0 +1,87 @@
|
||||
# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT
|
||||
# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
|
||||
|
||||
# ATT: vsm3msg1 %xmm4, %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmm4
|
||||
0xc4,0xe2,0x60,0xda,0xd4
|
||||
|
||||
# ATT: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
|
||||
0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
|
||||
|
||||
# ATT: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
|
||||
0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg1 (%eax), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
|
||||
0xc4,0xe2,0x60,0xda,0x10
|
||||
|
||||
# ATT: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
|
||||
0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
|
||||
|
||||
# ATT: vsm3msg1 2032(%ecx), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
|
||||
0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg1 -2048(%edx), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
|
||||
0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff
|
||||
|
||||
# ATT: vsm3msg2 %xmm4, %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmm4
|
||||
0xc4,0xe2,0x61,0xda,0xd4
|
||||
|
||||
# ATT: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
|
||||
0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
|
||||
|
||||
# ATT: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
|
||||
0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg2 (%eax), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
|
||||
0xc4,0xe2,0x61,0xda,0x10
|
||||
|
||||
# ATT: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
|
||||
0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
|
||||
|
||||
# ATT: vsm3msg2 2032(%ecx), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
|
||||
0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg2 -2048(%edx), %xmm3, %xmm2
|
||||
# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
|
||||
0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff
|
||||
|
||||
# ATT: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmm4, 123
|
||||
0xc4,0xe3,0x61,0xde,0xd4,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
|
||||
0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
|
||||
0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, (%eax), %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
|
||||
0xc4,0xe3,0x61,0xde,0x10,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
|
||||
0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
|
||||
0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
|
||||
# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
|
||||
0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b
|
||||
|
||||
87
llvm/test/MC/Disassembler/X86/sm3-64.txt
Normal file
87
llvm/test/MC/Disassembler/X86/sm3-64.txt
Normal file
@ -0,0 +1,87 @@
|
||||
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
|
||||
# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
|
||||
|
||||
# ATT: vsm3msg1 %xmm4, %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmm4
|
||||
0xc4,0x62,0x10,0xda,0xe4
|
||||
|
||||
# ATT: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
|
||||
0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
|
||||
|
||||
# ATT: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
|
||||
0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg1 (%rip), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
|
||||
0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
|
||||
0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
|
||||
|
||||
# ATT: vsm3msg1 2032(%rcx), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
|
||||
0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg1 -2048(%rdx), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
|
||||
0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff
|
||||
|
||||
# ATT: vsm3msg2 %xmm4, %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmm4
|
||||
0xc4,0x62,0x11,0xda,0xe4
|
||||
|
||||
# ATT: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
|
||||
0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
|
||||
|
||||
# ATT: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
|
||||
0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg2 (%rip), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
|
||||
0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
|
||||
0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
|
||||
|
||||
# ATT: vsm3msg2 2032(%rcx), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
|
||||
0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00
|
||||
|
||||
# ATT: vsm3msg2 -2048(%rdx), %xmm13, %xmm12
|
||||
# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
|
||||
0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff
|
||||
|
||||
# ATT: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmm4, 123
|
||||
0xc4,0x63,0x11,0xde,0xe4,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
|
||||
0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
|
||||
0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, (%rip), %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
|
||||
0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
|
||||
0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
|
||||
0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b
|
||||
|
||||
# ATT: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12
|
||||
# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
|
||||
0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b
|
||||
|
||||
86
llvm/test/MC/X86/sm3-att-32.s
Normal file
86
llvm/test/MC/X86/sm3-att-32.s
Normal file
@ -0,0 +1,86 @@
|
||||
// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vsm3msg1 %xmm4, %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
|
||||
vsm3msg1 %xmm4, %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
|
||||
vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
|
||||
vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg1 (%eax), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
|
||||
vsm3msg1 (%eax), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg1 2032(%ecx), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg1 2032(%ecx), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg1 -2048(%edx), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg1 -2048(%edx), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 %xmm4, %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
|
||||
vsm3msg2 %xmm4, %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
|
||||
vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
|
||||
vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 (%eax), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
|
||||
vsm3msg2 (%eax), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 2032(%ecx), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg2 2032(%ecx), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3msg2 -2048(%edx), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg2 -2048(%edx), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
|
||||
vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
|
||||
vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
|
||||
vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, (%eax), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
|
||||
vsm3rnds2 $123, (%eax), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
|
||||
vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
|
||||
vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
|
||||
|
||||
// CHECK: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
|
||||
vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
|
||||
|
||||
86
llvm/test/MC/X86/sm3-att-64.s
Normal file
86
llvm/test/MC/X86/sm3-att-64.s
Normal file
@ -0,0 +1,86 @@
|
||||
// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vsm3msg1 %xmm4, %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
|
||||
vsm3msg1 %xmm4, %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
|
||||
vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
|
||||
vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg1 (%rip), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
|
||||
vsm3msg1 (%rip), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg1 2032(%rcx), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg1 2032(%rcx), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg1 -2048(%rdx), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg1 -2048(%rdx), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 %xmm4, %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
|
||||
vsm3msg2 %xmm4, %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
|
||||
vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
|
||||
vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 (%rip), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
|
||||
vsm3msg2 (%rip), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 2032(%rcx), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg2 2032(%rcx), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3msg2 -2048(%rdx), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg2 -2048(%rdx), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
|
||||
vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
|
||||
vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
|
||||
vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, (%rip), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
|
||||
vsm3rnds2 $123, (%rip), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b]
|
||||
vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b]
|
||||
vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12
|
||||
|
||||
// CHECK: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b]
|
||||
vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12
|
||||
|
||||
86
llvm/test/MC/X86/sm3-intel-32.s
Normal file
86
llvm/test/MC/X86/sm3-intel-32.s
Normal file
@ -0,0 +1,86 @@
|
||||
// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmm4
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
|
||||
vsm3msg1 xmm2, xmm3, xmm4
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
|
||||
vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
|
||||
vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
|
||||
vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
|
||||
|
||||
// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmm4
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
|
||||
vsm3msg2 xmm2, xmm3, xmm4
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
|
||||
vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
|
||||
vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
|
||||
vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
|
||||
|
||||
// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
|
||||
// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmm4, 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmm4, 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
|
||||
// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
|
||||
vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
|
||||
|
||||
86
llvm/test/MC/X86/sm3-intel-64.s
Normal file
86
llvm/test/MC/X86/sm3-intel-64.s
Normal file
@ -0,0 +1,86 @@
|
||||
// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmm4
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
|
||||
vsm3msg1 xmm12, xmm13, xmm4
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
|
||||
// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
|
||||
vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
|
||||
// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
|
||||
vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
|
||||
vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
|
||||
|
||||
// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
|
||||
// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmm4
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
|
||||
vsm3msg2 xmm12, xmm13, xmm4
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
|
||||
// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
|
||||
vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
|
||||
// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
|
||||
vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
|
||||
vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
|
||||
vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
|
||||
vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
|
||||
|
||||
// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
|
||||
// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
|
||||
vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmm4, 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
|
||||
// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
|
||||
// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
|
||||
|
||||
// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
|
||||
// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b]
|
||||
vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
|
||||
|
||||
@ -4800,6 +4800,9 @@ static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
|
||||
{X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0},
|
||||
{X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0},
|
||||
{X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0},
|
||||
{X86::VSM3MSG1rr, X86::VSM3MSG1rm, 0},
|
||||
{X86::VSM3MSG2rr, X86::VSM3MSG2rm, 0},
|
||||
{X86::VSM3RNDS2rr, X86::VSM3RNDS2rm, 0},
|
||||
{X86::VSQRTPDZ128rk, X86::VSQRTPDZ128mk, 0},
|
||||
{X86::VSQRTPDZ256rk, X86::VSQRTPDZ256mk, 0},
|
||||
{X86::VSQRTPDZrk, X86::VSQRTPDZmk, 0},
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user