[AMDGPU] Update patterns for v_cvt_flr and v_cvt_rpi (#177962)
Support GlobalISel and switch to checking `nnan` flag on instruction
instead of TargetOptions.
Instruction are renamed to v_cvt_floor and v_cvt_nearest on gfx11+
so add gfx11 tests as well.
This commit is contained in:
Mirko Brkušanin
GitHub
parent
ecb1b0b90f
commit
c9e0cf139c
@ -1201,6 +1201,14 @@ def sext_like : PatFrags<(ops node:$src),
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[(zext_nneg node:$src),
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(sext node:$src)]>;
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def ffloor_nnan : PatFrag<(ops node:$src), (ffloor node:$src), [{
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return N->getFlags().hasNoNaNs();
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}]> {
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let GISelPredicateCode = [{
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return MI.getFlag(MachineInstr::FmNoNans);
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}];
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}
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// null_frag - The null pattern operator is used in multiclass instantiations
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// which accept an SDPatternOperator for use in matching patterns for internal
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// definitions. When expanding a pattern, if the null fragment is referenced
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@ -758,8 +758,11 @@ def FP_ONE : PatLeaf <
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def FP_HALF : PatLeaf <
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(fpimm),
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[{return N->isExactlyValue(0.5);}]
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>;
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[{return N->isExactlyValue(0.5);}]> {
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let GISelPredicateCode = [{
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return MI.getOperand(1).getFPImm()->isExactlyValue(0.5);
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}];
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}
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/* Generic helper patterns for intrinsics */
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/* -------------------------------------- */
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@ -806,16 +809,15 @@ class DwordAddrPat<ValueType vt, RegisterClass rc> : AMDGPUPat <
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// Special conversion patterns
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def cvt_rpi_i32_f32 : PatFrag <
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let GIIgnoreCopies = 1 in
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def cvt_rpi_i32_f32 : PatFrag<
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(ops node:$src),
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(fp_to_sint (ffloor (fadd $src, FP_HALF))),
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[{ (void) N; return TM.Options.NoNaNsFPMath; }]
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>;
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(fp_to_sint (ffloor_nnan (fadd $src, FP_HALF)))
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>, GISelFlags;
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def cvt_flr_i32_f32 : PatFrag <
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def cvt_flr_i32_f32 : PatFrag<
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(ops node:$src),
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(fp_to_sint (ffloor $src)),
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[{ (void)N; return TM.Options.NoNaNsFPMath; }]
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(fp_to_sint (ffloor_nnan $src))
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>;
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let AddedComplexity = 2 in {
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@ -1,82 +1,332 @@
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -enable-no-nans-fp-math < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SDAG %s
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; RUN: llc -mtriple=amdgcn -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.floor.f32(float) #1
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NOT: add
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; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_flr_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {
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%floor = call float @llvm.floor.f32(float %x) #1
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; SI-SDAG-LABEL: cvt_flr_i32_f32_0:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s2, -1
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e32 v0, s6
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; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: cvt_flr_i32_f32_0:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_cvt_flr_i32_f32_e32 v0, s3
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; GFX11-SDAG-LABEL: cvt_flr_i32_f32_0:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_clause 0x1
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; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e32 v1, s2
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: cvt_flr_i32_f32_0:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_clause 0x1
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; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_cvt_floor_i32_f32_e32 v0, s2
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_endpgm
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%floor = call nnan float @llvm.floor.f32(float %x) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
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; SI: v_add_f32_e64 [[TMP:v[0-9]+]], s{{[0-9]+}}, 1.0
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_flr_i32_f32_1(ptr addrspace(1) %out, float %x) #0 {
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; SI-SDAG-LABEL: cvt_flr_i32_f32_1:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s2, -1
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: v_add_f32_e64 v0, s6, 1.0
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; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e32 v0, v0
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; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: cvt_flr_i32_f32_1:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_add_f32_e64 v0, s3, 1.0
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; SI-GISEL-NEXT: v_cvt_flr_i32_f32_e32 v0, v0
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; GFX11-SDAG-LABEL: cvt_flr_i32_f32_1:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_clause 0x1
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; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_add_f32_e64 v0, s2, 1.0
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; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e32 v0, v0
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; GFX11-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: cvt_flr_i32_f32_1:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_clause 0x1
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; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_add_f32_e64 v0, s2, 1.0
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; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-GISEL-NEXT: v_cvt_floor_i32_f32_e32 v0, v0
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_endpgm
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%fadd = fadd float %x, 1.0
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%floor = call float @llvm.floor.f32(float %fadd) #1
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%floor = call nnan float @llvm.floor.f32(float %fadd) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
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; SI-NOT: add
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_flr_i32_f32_fabs(ptr addrspace(1) %out, float %x) #0 {
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; SI-SDAG-LABEL: cvt_flr_i32_f32_fabs:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s2, -1
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e64 v0, |s6|
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; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: cvt_flr_i32_f32_fabs:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_cvt_flr_i32_f32_e64 v0, |s3|
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; GFX11-SDAG-LABEL: cvt_flr_i32_f32_fabs:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_clause 0x1
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; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e64 v1, |s2|
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: cvt_flr_i32_f32_fabs:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_clause 0x1
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; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_cvt_floor_i32_f32_e64 v0, |s2|
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_endpgm
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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%floor = call float @llvm.floor.f32(float %x.fabs) #1
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%floor = call nnan float @llvm.floor.f32(float %x.fabs) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
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; SI-NOT: add
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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; SI: s_endpgm
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; FIXME: GlobalISel selecting modifier fails because of G_FCANONICALIZE
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define amdgpu_kernel void @cvt_flr_i32_f32_fneg(ptr addrspace(1) %out, float %x) #0 {
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; SI-SDAG-LABEL: cvt_flr_i32_f32_fneg:
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; SI-SDAG: ; %bb.0:
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; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
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; SI-SDAG-NEXT: s_mov_b32 s2, -1
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; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e64 v0, -s6
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; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-SDAG-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: cvt_flr_i32_f32_fneg:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, -s3
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; SI-GISEL-NEXT: v_cvt_flr_i32_f32_e32 v0, v0
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; GFX11-SDAG-LABEL: cvt_flr_i32_f32_fneg:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_clause 0x1
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; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e64 v1, -s2
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: cvt_flr_i32_f32_fneg:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_clause 0x1
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; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_max_f32_e64 v0, -s2, -s2
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_cvt_floor_i32_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%x.fneg = fsub float -0.000000e+00, %x
|
||||
%floor = call float @llvm.floor.f32(float %x.fneg) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %x.fneg) #1
|
||||
%cvt = fptosi float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
|
||||
; SI-NOT: add
|
||||
; SI-SAFE-NOT: v_cvt_flr_i32_f32
|
||||
; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @cvt_flr_i32_f32_fabs_fneg(ptr addrspace(1) %out, float %x) #0 {
|
||||
; SI-SDAG-LABEL: cvt_flr_i32_f32_fabs_fneg:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e64 v0, -|s6|
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: cvt_flr_i32_f32_fabs_fneg:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, -|s3|
|
||||
; SI-GISEL-NEXT: v_cvt_flr_i32_f32_e32 v0, v0
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: cvt_flr_i32_f32_fabs_fneg:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e64 v1, -|s2|
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: cvt_flr_i32_f32_fabs_fneg:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_max_f32_e64 v0, -|s2|, -|s2|
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_cvt_floor_i32_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%x.fabs = call float @llvm.fabs.f32(float %x) #1
|
||||
%x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
|
||||
%floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %x.fabs.fneg) #1
|
||||
%cvt = fptosi float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}no_cvt_flr_i32_f32_0:
|
||||
; SI-NOT: v_cvt_flr_i32_f32
|
||||
; SI: v_floor_f32
|
||||
; SI: v_cvt_u32_f32_e32
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @no_cvt_flr_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {
|
||||
%floor = call float @llvm.floor.f32(float %x) #1
|
||||
;
|
||||
; SI-SDAG-LABEL: no_cvt_flr_i32_f32_0:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_floor_f32_e32 v0, s6
|
||||
; SI-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: no_cvt_flr_i32_f32_0:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_floor_f32_e32 v0, s3
|
||||
; SI-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: no_cvt_flr_i32_f32_0:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_floor_f32_e32 v0, s2
|
||||
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: no_cvt_flr_i32_f32_0:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_floor_f32_e32 v0, s2
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%floor = call nnan float @llvm.floor.f32(float %x) #1
|
||||
%cvt = fptoui float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
|
||||
@ -1,79 +1,291 @@
|
||||
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -mtriple=amdgcn -enable-no-nans-fp-math < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
|
||||
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SDAG %s
|
||||
; RUN: llc -mtriple=amdgcn -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s
|
||||
|
||||
declare float @llvm.fabs.f32(float) #1
|
||||
declare float @llvm.floor.f32(float) #1
|
||||
|
||||
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
|
||||
; SI-SAFE-NOT: v_cvt_rpi_i32_f32
|
||||
; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @cvt_rpi_i32_f32(ptr addrspace(1) %out, float %x) #0 {
|
||||
; SI-SDAG-LABEL: cvt_rpi_i32_f32:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_cvt_rpi_i32_f32_e32 v0, s6
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: cvt_rpi_i32_f32:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_cvt_rpi_i32_f32_e32 v0, s3
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_cvt_nearest_i32_f32_e32 v1, s2
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_cvt_nearest_i32_f32_e32 v0, s2
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%fadd = fadd float %x, 0.5
|
||||
%floor = call float @llvm.floor.f32(float %fadd) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %fadd) #1
|
||||
%cvt = fptosi float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
|
||||
; SI-SAFE-NOT: v_cvt_rpi_i32_f32
|
||||
; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @cvt_rpi_i32_f32_fabs(ptr addrspace(1) %out, float %x) #0 {
|
||||
; SI-SDAG-LABEL: cvt_rpi_i32_f32_fabs:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_cvt_rpi_i32_f32_e64 v0, |s6|
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: cvt_rpi_i32_f32_fabs:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_cvt_rpi_i32_f32_e64 v0, |s3|
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32_fabs:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_cvt_nearest_i32_f32_e64 v1, |s2|
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32_fabs:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_cvt_nearest_i32_f32_e64 v0, |s2|
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%x.fabs = call float @llvm.fabs.f32(float %x) #1
|
||||
%fadd = fadd float %x.fabs, 0.5
|
||||
%floor = call float @llvm.floor.f32(float %fadd) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %fadd) #1
|
||||
%cvt = fptosi float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: This doesn't work because it forms fsub 0.5, x
|
||||
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
|
||||
; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
|
||||
; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
|
||||
; SI-SAFE-NOT: v_cvt_flr_i32_f32
|
||||
; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @cvt_rpi_i32_f32_fneg(ptr addrspace(1) %out, float %x) #0 {
|
||||
; SI-SDAG-LABEL: cvt_rpi_i32_f32_fneg:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_sub_f32_e64 v0, 0.5, s6
|
||||
; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e32 v0, v0
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: cvt_rpi_i32_f32_fneg:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, -s3
|
||||
; SI-GISEL-NEXT: v_cvt_rpi_i32_f32_e32 v0, v0
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32_fneg:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_sub_f32_e64 v0, 0.5, s2
|
||||
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e32 v0, v0
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32_fneg:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_max_f32_e64 v0, -s2, -s2
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_cvt_nearest_i32_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%x.fneg = fsub float -0.000000e+00, %x
|
||||
%fadd = fadd float %x.fneg, 0.5
|
||||
%floor = call float @llvm.floor.f32(float %fadd) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %fadd) #1
|
||||
%cvt = fptosi float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: This doesn't work for same reason as above
|
||||
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
|
||||
; SI-SAFE-NOT: v_cvt_rpi_i32_f32
|
||||
; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
|
||||
|
||||
; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
|
||||
; SI-SAFE-NOT: v_cvt_flr_i32_f32
|
||||
; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @cvt_rpi_i32_f32_fabs_fneg(ptr addrspace(1) %out, float %x) #0 {
|
||||
;
|
||||
; SI-SDAG-LABEL: cvt_rpi_i32_f32_fabs_fneg:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_sub_f32_e64 v0, 0.5, |s6|
|
||||
; SI-SDAG-NEXT: v_cvt_flr_i32_f32_e32 v0, v0
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: cvt_rpi_i32_f32_fabs_fneg:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_mul_f32_e64 v0, 1.0, -|s3|
|
||||
; SI-GISEL-NEXT: v_cvt_rpi_i32_f32_e32 v0, v0
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32_fabs_fneg:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_sub_f32_e64 v0, 0.5, |s2|
|
||||
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-SDAG-NEXT: v_cvt_floor_i32_f32_e32 v0, v0
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32_fabs_fneg:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_max_f32_e64 v0, -|s2|, -|s2|
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_cvt_nearest_i32_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%x.fabs = call float @llvm.fabs.f32(float %x) #1
|
||||
%x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
|
||||
%fadd = fadd float %x.fabs.fneg, 0.5
|
||||
%floor = call float @llvm.floor.f32(float %fadd) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %fadd) #1
|
||||
%cvt = fptosi float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:
|
||||
; SI-NOT: v_cvt_rpi_i32_f32
|
||||
; SI: v_add_f32
|
||||
; SI: v_floor_f32
|
||||
; SI: v_cvt_u32_f32
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @no_cvt_rpi_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {
|
||||
; SI-SDAG-LABEL: no_cvt_rpi_i32_f32_0:
|
||||
; SI-SDAG: ; %bb.0:
|
||||
; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
|
||||
; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SDAG-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SDAG-NEXT: v_add_f32_e64 v0, s6, 0.5
|
||||
; SI-SDAG-NEXT: v_floor_f32_e32 v0, v0
|
||||
; SI-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; SI-GISEL-LABEL: no_cvt_rpi_i32_f32_0:
|
||||
; SI-GISEL: ; %bb.0:
|
||||
; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
|
||||
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
||||
; SI-GISEL-NEXT: s_mov_b32 s2, -1
|
||||
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-GISEL-NEXT: v_add_f32_e64 v0, s3, 0.5
|
||||
; SI-GISEL-NEXT: v_floor_f32_e32 v0, v0
|
||||
; SI-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-GISEL-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-SDAG-LABEL: no_cvt_rpi_i32_f32_0:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_clause 0x1
|
||||
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_add_f32_e64 v0, s2, 0.5
|
||||
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
||||
; GFX11-SDAG-NEXT: v_floor_f32_e32 v0, v0
|
||||
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; GFX11-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX11-GISEL-LABEL: no_cvt_rpi_i32_f32_0:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_clause 0x1
|
||||
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
|
||||
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
|
||||
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_add_f32_e64 v0, s2, 0.5
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_floor_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
|
||||
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
|
||||
; GFX11-GISEL-NEXT: s_endpgm
|
||||
%fadd = fadd float %x, 0.5
|
||||
%floor = call float @llvm.floor.f32(float %fadd) #1
|
||||
%floor = call nnan float @llvm.floor.f32(float %fadd) #1
|
||||
%cvt = fptoui float %floor to i32
|
||||
store i32 %cvt, ptr addrspace(1) %out
|
||||
ret void
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
// CHECK: // PatFrag predicates.
|
||||
// CHECK-NEXT: enum {
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_and_or_pat = GICXXPred_Invalid + 1,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_ffloor_nnan,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_mul_pat,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_or_disjoint,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_or_oneuse,
|
||||
@ -17,6 +18,8 @@
|
||||
// CHECK: bool MyTargetInstructionSelector::testMIPredicate_MI(
|
||||
// CHECK: case GICXXPred_MI_Predicate_and_or_pat: {
|
||||
// CHECK: return doesComplexCheck(MI);
|
||||
// CHECK: case GICXXPred_MI_Predicate_ffloor_nnan: {
|
||||
// CHECK: return MI.getFlag(MachineInstr::FmNoNans);
|
||||
// CHECK: case GICXXPred_MI_Predicate_mul_pat: {
|
||||
// CHECK: return doesComplexCheck(MI);
|
||||
// CHECK: case GICXXPred_MI_Predicate_or_oneuse: {
|
||||
|
||||
@ -155,7 +155,8 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
|
||||
|
||||
// CHECK-LABEL: // PatFrag predicates.
|
||||
// CHECK-NEXT: enum {
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_frag = GICXXPred_Invalid + 1,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_ffloor_nnan = GICXXPred_Invalid + 1,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_frag,
|
||||
// CHECK-NEXT: GICXXPred_MI_Predicate_or_disjoint,
|
||||
// CHECK-NEXT: };
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user