[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)
This commit is contained in:
Chinmay Deshpande
GitHub
parent
854df547a0
commit
ca7edf2d14
@ -939,7 +939,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
|
||||
|
||||
bool hasSALUFloat = ST->hasSALUFloatInsts();
|
||||
|
||||
addRulesForGOpcs({G_FADD, G_FMUL}, Standard)
|
||||
addRulesForGOpcs({G_FADD, G_FMUL, G_STRICT_FADD, G_STRICT_FMUL}, Standard)
|
||||
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}, !hasSALUFloat)
|
||||
.Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}}, hasSALUFloat)
|
||||
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
|
||||
@ -951,9 +951,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
|
||||
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}}, !hasSALUFloat)
|
||||
.Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, ScalarizeToS16},
|
||||
hasSALUFloat)
|
||||
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
|
||||
.Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32, VgprV2S32}}})
|
||||
.Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32, VgprV2S32}}});
|
||||
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
|
||||
|
||||
// FNEG and FABS are either folded as source modifiers or can be selected as
|
||||
// bitwise XOR and AND with Mask. XOR and AND are available on SALU but for
|
||||
|
||||
@ -1,41 +1,29 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG-TRUE16 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG-FAKE16 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG-FAKE16 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
|
||||
; FIXME: promotion not handled without f16 insts
|
||||
|
||||
define half @v_constained_fadd_f16_fpexcept_strict(half %x, half %y) #0 {
|
||||
; GFX9-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
; GCN-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GCN-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX11-SDAG-TRUE16: ; %bb.0:
|
||||
@ -43,24 +31,12 @@ define half @v_constained_fadd_f16_fpexcept_strict(half %x, half %y) #0 {
|
||||
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX11-SDAG-FAKE16: ; %bb.0:
|
||||
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX11-GISEL-TRUE16: ; %bb.0:
|
||||
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX11-GISEL-FAKE16: ; %bb.0:
|
||||
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-LABEL: v_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
@ -75,23 +51,11 @@ define half @v_constained_fadd_f16_fpexcept_strict(half %x, half %y) #0 {
|
||||
}
|
||||
|
||||
define half @v_constained_fadd_f16_fpexcept_ignore(half %x, half %y) #0 {
|
||||
; GFX9-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
; GCN-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GCN-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX11-SDAG-TRUE16: ; %bb.0:
|
||||
@ -99,24 +63,12 @@ define half @v_constained_fadd_f16_fpexcept_ignore(half %x, half %y) #0 {
|
||||
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX11-SDAG-FAKE16: ; %bb.0:
|
||||
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX11-GISEL-TRUE16: ; %bb.0:
|
||||
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX11-GISEL-FAKE16: ; %bb.0:
|
||||
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
@ -126,38 +78,16 @@ define half @v_constained_fadd_f16_fpexcept_ignore(half %x, half %y) #0 {
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX11-TRUE16: ; %bb.0:
|
||||
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_ignore:
|
||||
; GFX11-FAKE16: ; %bb.0:
|
||||
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
%val = call half @llvm.experimental.constrained.fadd.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
|
||||
ret half %val
|
||||
}
|
||||
|
||||
define half @v_constained_fadd_f16_fpexcept_maytrap(half %x, half %y) #0 {
|
||||
; GFX9-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
; GCN-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GCN-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX11-SDAG-TRUE16: ; %bb.0:
|
||||
@ -165,24 +95,12 @@ define half @v_constained_fadd_f16_fpexcept_maytrap(half %x, half %y) #0 {
|
||||
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX11-SDAG-FAKE16: ; %bb.0:
|
||||
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX11-GISEL-TRUE16: ; %bb.0:
|
||||
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX11-GISEL-FAKE16: ; %bb.0:
|
||||
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
@ -192,16 +110,6 @@ define half @v_constained_fadd_f16_fpexcept_maytrap(half %x, half %y) #0 {
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-TRUE16-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX11-TRUE16: ; %bb.0:
|
||||
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
|
||||
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-FAKE16-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
|
||||
; GFX11-FAKE16: ; %bb.0:
|
||||
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
|
||||
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
%val = call half @llvm.experimental.constrained.fadd.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
|
||||
ret half %val
|
||||
}
|
||||
@ -439,18 +347,6 @@ define <3 x half> @v_constained_fadd_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
|
||||
; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v2
|
||||
; GFX12-GISEL-NEXT: v_pk_add_f16 v1, v1, v3
|
||||
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-TRUE16-LABEL: v_constained_fadd_v3f16_fpexcept_strict:
|
||||
; GFX11-TRUE16: ; %bb.0:
|
||||
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
|
||||
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-FAKE16-LABEL: v_constained_fadd_v3f16_fpexcept_strict:
|
||||
; GFX11-FAKE16: ; %bb.0:
|
||||
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v1, v1, v3
|
||||
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
%val = call <3 x half> @llvm.experimental.constrained.fadd.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret <3 x half> %val
|
||||
}
|
||||
@ -578,28 +474,6 @@ define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
|
||||
; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v2
|
||||
; GFX12-GISEL-NEXT: v_pk_add_f16 v1, v1, v3
|
||||
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-TRUE16-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
|
||||
; GFX11-TRUE16: ; %bb.0:
|
||||
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.h, v1.h, v3.h
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.h, v0.h, v2.h
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
|
||||
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-FAKE16-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
|
||||
; GFX11-FAKE16: ; %bb.0:
|
||||
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
||||
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
||||
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
||||
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v1, v1, v3
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v2, v6, v5
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e32 v3, v7, v4
|
||||
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
|
||||
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
|
||||
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
||||
%val = call <4 x half> @llvm.experimental.constrained.fadd.v4f16(<4 x half> %x, <4 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret <4 x half> %val
|
||||
}
|
||||
@ -648,14 +522,6 @@ define amdgpu_ps half @s_constained_fadd_f16_fpexcept_strict(half inreg %x, half
|
||||
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
|
||||
; GFX12-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX12-NEXT: ; return to shader part epilog
|
||||
; GFX11-TRUE16-LABEL: s_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX11-TRUE16: ; %bb.0:
|
||||
; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, s2, s3
|
||||
; GFX11-TRUE16-NEXT: ; return to shader part epilog
|
||||
; GFX11-FAKE16-LABEL: s_constained_fadd_f16_fpexcept_strict:
|
||||
; GFX11-FAKE16: ; %bb.0:
|
||||
; GFX11-FAKE16-NEXT: v_add_f16_e64 v0, s2, s3
|
||||
; GFX11-FAKE16-NEXT: ; return to shader part epilog
|
||||
%val = call half @llvm.experimental.constrained.fadd.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret half %val
|
||||
}
|
||||
@ -681,14 +547,19 @@ define amdgpu_ps <2 x half> @s_constained_fadd_v2f16_fpexcept_strict(<2 x half>
|
||||
;
|
||||
; GFX8-GISEL-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
|
||||
; GFX8-GISEL: ; %bb.0:
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s3
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX8-GISEL-NEXT: v_add_f16_e32 v0, s2, v0
|
||||
; GFX8-GISEL-NEXT: v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s2, v0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s1
|
||||
; GFX8-GISEL-NEXT: v_add_f16_e32 v0, s0, v0
|
||||
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX8-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
|
||||
; GFX8-GISEL-NEXT: s_and_b32 s1, 0xffff, s2
|
||||
; GFX8-GISEL-NEXT: s_lshl_b32 s0, s0, 16
|
||||
; GFX8-GISEL-NEXT: s_or_b32 s0, s1, s0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX8-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
|
||||
@ -701,10 +572,21 @@ define amdgpu_ps <2 x half> @s_constained_fadd_v2f16_fpexcept_strict(<2 x half>
|
||||
; GFX11-NEXT: v_pk_add_f16 v0, s2, s3
|
||||
; GFX11-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: v_pk_add_f16 v0, s2, s3
|
||||
; GFX12-NEXT: ; return to shader part epilog
|
||||
; GFX12-SDAG-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
|
||||
; GFX12-SDAG: ; %bb.0:
|
||||
; GFX12-SDAG-NEXT: v_pk_add_f16 v0, s2, s3
|
||||
; GFX12-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-GISEL-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
|
||||
; GFX12-GISEL: ; %bb.0:
|
||||
; GFX12-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX12-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX12-GISEL-NEXT: s_add_f16 s2, s2, s3
|
||||
; GFX12-GISEL-NEXT: s_add_f16 s0, s0, s1
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s2, s0
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX12-GISEL-NEXT: ; return to shader part epilog
|
||||
%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret <2 x half> %val
|
||||
}
|
||||
|
||||
@ -1,15 +1,15 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
|
||||
define float @v_constained_fadd_f32_fpexcept_strict(float %x, float %y) #0 {
|
||||
; GFX9-LABEL: v_constained_fadd_f32_fpexcept_strict:
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX11 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX11 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX11-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX11-GISEL %s
|
||||
|
||||
define double @v_constained_fadd_f64_fpexcept_strict(double %x, double %y) #0 {
|
||||
; GCN-LABEL: v_constained_fadd_f64_fpexcept_strict:
|
||||
@ -96,12 +96,38 @@ define amdgpu_ps <2 x float> @s_constained_fadd_f64_fpexcept_strict(double inreg
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GCN-GISEL-NEXT: v_add_f64 v[0:1], s[2:3], v[0:1]
|
||||
; GCN-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GCN-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10PLUS-LABEL: s_constained_fadd_f64_fpexcept_strict:
|
||||
; GFX10PLUS: ; %bb.0:
|
||||
; GFX10PLUS-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX10PLUS-NEXT: ; return to shader part epilog
|
||||
; GFX10-SDAG-LABEL: s_constained_fadd_f64_fpexcept_strict:
|
||||
; GFX10-SDAG: ; %bb.0:
|
||||
; GFX10-SDAG-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX10-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-GISEL-LABEL: s_constained_fadd_f64_fpexcept_strict:
|
||||
; GFX10-GISEL: ; %bb.0:
|
||||
; GFX10-GISEL-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX10-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-SDAG-LABEL: s_constained_fadd_f64_fpexcept_strict:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX11-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-GISEL-LABEL: s_constained_fadd_f64_fpexcept_strict:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
||||
; GFX11-GISEL-NEXT: ; return to shader part epilog
|
||||
%val = call double @llvm.experimental.constrained.fadd.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
%cast = bitcast double %val to <2 x float>
|
||||
ret <2 x float> %cast
|
||||
@ -113,6 +139,3 @@ declare <3 x double> @llvm.experimental.constrained.fadd.v3f64(<3 x double>, <3
|
||||
|
||||
attributes #0 = { strictfp }
|
||||
attributes #1 = { inaccessiblememonly nounwind willreturn }
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; GFX10: {{.*}}
|
||||
; GFX11: {{.*}}
|
||||
|
||||
@ -1,20 +1,20 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
|
||||
; FIXME: promotion not handled without f16 insts
|
||||
|
||||
@ -627,14 +627,19 @@ define amdgpu_ps <2 x half> @s_constained_fmul_v2f16_fpexcept_strict(<2 x half>
|
||||
;
|
||||
; GFX8-GISEL-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX8-GISEL: ; %bb.0:
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s3
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_e32 v0, s2, v0
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s2, v0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s1
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_e32 v0, s0, v0
|
||||
; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX8-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
|
||||
; GFX8-GISEL-NEXT: s_and_b32 s1, 0xffff, s2
|
||||
; GFX8-GISEL-NEXT: s_lshl_b32 s0, s0, 16
|
||||
; GFX8-GISEL-NEXT: s_or_b32 s0, s1, s0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX8-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10PLUS-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
@ -642,10 +647,21 @@ define amdgpu_ps <2 x half> @s_constained_fmul_v2f16_fpexcept_strict(<2 x half>
|
||||
; GFX10PLUS-NEXT: v_pk_mul_f16 v0, s2, s3
|
||||
; GFX10PLUS-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: v_pk_mul_f16 v0, s2, s3
|
||||
; GFX12-NEXT: ; return to shader part epilog
|
||||
; GFX12-SDAG-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX12-SDAG: ; %bb.0:
|
||||
; GFX12-SDAG-NEXT: v_pk_mul_f16 v0, s2, s3
|
||||
; GFX12-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX12-GISEL-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX12-GISEL: ; %bb.0:
|
||||
; GFX12-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX12-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX12-GISEL-NEXT: s_mul_f16 s2, s2, s3
|
||||
; GFX12-GISEL-NEXT: s_mul_f16 s0, s0, s1
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
||||
; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s0, s2, s0
|
||||
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX12-GISEL-NEXT: ; return to shader part epilog
|
||||
%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret <2 x half> %val
|
||||
}
|
||||
|
||||
@ -1,15 +1,15 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
|
||||
|
||||
define float @v_constained_fmul_f32_fpexcept_strict(float %x, float %y) #0 {
|
||||
; GCN-LABEL: v_constained_fmul_f32_fpexcept_strict:
|
||||
@ -339,6 +339,3 @@ declare <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float>, <2 x
|
||||
declare <3 x float> @llvm.experimental.constrained.fmul.v3f32(<3 x float>, <3 x float>, metadata, metadata)
|
||||
|
||||
attributes #0 = { strictfp }
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; GFX12-GISEL: {{.*}}
|
||||
; GFX12-SDAG: {{.*}}
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
|
||||
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
|
||||
|
||||
define double @v_constained_fmul_f64_fpexcept_strict(double %x, double %y) #0 {
|
||||
; GCN-LABEL: v_constained_fmul_f64_fpexcept_strict:
|
||||
@ -178,22 +178,50 @@ define <3 x double> @v_constained_fmul_v3f64_fpexcept_strict(<3 x double> %x, <3
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x float> @s_constained_fmul_f64_fpexcept_strict(double inreg %x, double inreg %y) #0 {
|
||||
; GCN-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GCN-NEXT: v_mul_f64 v[0:1], s[2:3], v[0:1]
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
; GCN-SDAG-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GCN-SDAG: ; %bb.0:
|
||||
; GCN-SDAG-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GCN-SDAG-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GCN-SDAG-NEXT: v_mul_f64 v[0:1], s[2:3], v[0:1]
|
||||
; GCN-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
; GCN-GISEL-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GCN-GISEL: ; %bb.0:
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GCN-GISEL-NEXT: v_mul_f64 v[0:1], s[2:3], v[0:1]
|
||||
; GCN-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GCN-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GCN-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX11-NEXT: ; return to shader part epilog
|
||||
; GFX10-SDAG-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GFX10-SDAG: ; %bb.0:
|
||||
; GFX10-SDAG-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX10-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-GISEL-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GFX10-GISEL: ; %bb.0:
|
||||
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX10-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-SDAG-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX11-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX11-GISEL-LABEL: s_constained_fmul_f64_fpexcept_strict:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5]
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
||||
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
||||
; GFX11-GISEL-NEXT: ; return to shader part epilog
|
||||
%val = call double @llvm.experimental.constrained.fmul.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
%cast = bitcast double %val to <2 x float>
|
||||
ret <2 x float> %cast
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user