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Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for COPY"

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This reverts commit r315781, breaks:
http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882

llvm-svn: 315823
This commit is contained in:
Bruno Cardoso Lopes 2017-10-14 19:31:03 +00:00
parent 13376a4bdf
commit caac2fbd19
1 changed files with 4 additions and 32 deletions
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36
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
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@ -415,10 +415,12 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
const RegisterBankInfo::InstructionMapping &
AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const unsigned Opc = MI.getOpcode();
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
// Try the default logic for non-generic instructions that are either copies
// or already have some operands assigned to banks.
if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
if (!isPreISelGenericOpcode(Opc) ||
Opc == TargetOpcode::G_PHI) {
const RegisterBankInfo::InstructionMapping &Mapping =
getInstrMappingImpl(MI);
@ -426,11 +428,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
return Mapping;
}
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
switch (Opc) {
// G_{F|S|U}REM are not listed because they are not legal.
// Arithmetic ops.
@ -454,30 +451,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FDIV:
return getSameKindOfOperandsMapping(MI);
case TargetOpcode::COPY: {
unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcReg = MI.getOperand(1).getReg();
if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
if (!DstRB)
DstRB = SrcRB;
else if (!SrcRB)
SrcRB = DstRB;
// If both RB are null that means both registers are generic.
// We shouldn't be here.
assert(DstRB && SrcRB && "Both RegBank were nullptr");
unsigned Size = getSizeInBits(DstReg, MRI, TRI);
return getInstructionMapping(
DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
// We only care about the mapping of the destination.
/*NumOperands*/ 1);
}
// Both registers are generic, use G_BITCAST.
LLVM_FALLTHROUGH;
}
case TargetOpcode::G_BITCAST: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
@ -491,8 +464,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
return getInstructionMapping(
DefaultMappingID, copyCost(DstRB, SrcRB, Size),
getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
// We only care about the mapping of the destination for COPY.
/*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
/*NumOperands*/ 2);
}
default:
break;