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Use APInt::popcount instead of APInt::countPopulation (NFC)

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This is for consistency with the C++20-style bit manipulation
functions in <bit>.
This commit is contained in:
Kazu Hirata 2023-02-19 11:29:12 -08:00
parent 179a24c2f1
commit cbde2124f1
21 changed files with 44 additions and 49 deletions
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4
clang/lib/AST/ExprConstant.cpp
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@ -12142,7 +12142,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!EvaluateInteger(E->getArg(0), Val, Info))
return false;
return Success(Val.countPopulation() % 2, E);
return Success(Val.popcount() % 2, E);
}
case Builtin::BI__builtin_popcount:
@ -12152,7 +12152,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!EvaluateInteger(E->getArg(0), Val, Info))
return false;
return Success(Val.countPopulation(), E);
return Success(Val.popcount(), E);
}
case Builtin::BI__builtin_rotateleft8:

2
llvm/include/llvm/ADT/APInt.h
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@ -347,7 +347,7 @@ public:
///
/// \returns true if this APInt only has the specified bit set.
bool isOneBitSet(unsigned BitNo) const {
return (*this)[BitNo] && countPopulation() == 1;
return (*this)[BitNo] && popcount() == 1;
}
/// Determine if all bits are set. This is true for zero-width values.

2
llvm/include/llvm/CodeGen/BasicTTIImpl.h
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@ -1508,7 +1508,7 @@ public:
// SelectionDAGBuilder.
APInt Exponent = RHSC->getValue().abs();
unsigned ActiveBits = Exponent.getActiveBits();
unsigned PopCount = Exponent.countPopulation();
unsigned PopCount = Exponent.popcount();
InstructionCost Cost = (ActiveBits + PopCount - 2) *
thisT()->getArithmeticInstrCost(
Instruction::FMul, RetTy, CostKind);

8
llvm/include/llvm/Support/KnownBits.h
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@ -49,7 +49,7 @@ public:
/// Returns true if we know the value of all bits.
bool isConstant() const {
assert(!hasConflict() && "KnownBits conflict!");
return Zero.countPopulation() + One.countPopulation() == getBitWidth();
return Zero.popcount() + One.popcount() == getBitWidth();
}
/// Returns the value when all bits have a known value. This just returns One
@ -290,13 +290,11 @@ public:
}
/// Returns the number of bits known to be one.
unsigned countMinPopulation() const {
return One.countPopulation();
}
unsigned countMinPopulation() const { return One.popcount(); }
/// Returns the maximum number of bits that could be one.
unsigned countMaxPopulation() const {
return getBitWidth() - Zero.countPopulation();
return getBitWidth() - Zero.popcount();
}
/// Returns the maximum number of bits needed to represent all possible

2
llvm/lib/Analysis/ConstantFolding.cpp
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@ -2395,7 +2395,7 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
case Intrinsic::bswap:
return ConstantInt::get(Ty->getContext(), Op->getValue().byteSwap());
case Intrinsic::ctpop:
return ConstantInt::get(Ty, Op->getValue().countPopulation());
return ConstantInt::get(Ty, Op->getValue().popcount());
case Intrinsic::bitreverse:
return ConstantInt::get(Ty->getContext(), Op->getValue().reverseBits());
case Intrinsic::convert_from_fp16: {

6
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -18187,7 +18187,7 @@ struct LoadedSlice {
/// Get the size of the slice to be loaded in bytes.
unsigned getLoadedSize() const {
unsigned SliceSize = getUsedBits().countPopulation();
unsigned SliceSize = getUsedBits().popcount();
assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
return SliceSize / 8;
}
@ -24034,7 +24034,7 @@ static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf,
assert((unsigned)Idx < NumElts && "Out-of-bounds shuffle indice?");
DemandedElts.setBit(Idx);
}
assert(DemandedElts.countPopulation() > 1 && "Is a splat shuffle already?");
assert(DemandedElts.popcount() > 1 && "Is a splat shuffle already?");
APInt UndefElts;
if (DAG.isSplatValue(Shuf->getOperand(0), DemandedElts, UndefElts)) {
// Even if all demanded elements are splat, some of them could be undef.
@ -26109,7 +26109,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
SDValue AndLHS = N0->getOperand(0);
auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
if (ConstAndRHS && ConstAndRHS->getAPIntValue().popcount() == 1) {
// Shift the tested bit over the sign bit.
const APInt &AndMask = ConstAndRHS->getAPIntValue();
unsigned ShCt = AndMask.getBitWidth() - 1;

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2714,7 +2714,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
// TODO: Handle source ops splats with undefs.
auto CheckSplatSrc = [&](SDValue Src, const APInt &SrcElts) {
APInt SrcUndefs;
return (SrcElts.countPopulation() == 1) ||
return (SrcElts.popcount() == 1) ||
(isSplatValue(Src, SrcElts, SrcUndefs, Depth + 1) &&
(SrcElts & SrcUndefs).isZero());
};
@ -5264,7 +5264,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return getConstant(Val.byteSwap(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTPOP:
return getConstant(Val.countPopulation(), DL, VT, C->isTargetOpcode(),
return getConstant(Val.popcount(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF:

4
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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@ -3149,7 +3149,7 @@ static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
// BFI/BFXIL dst, src, #lsb, #width.
int LSB = llvm::countr_one(NotKnownZero);
int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
int Width = BitWidth - APInt(BitWidth, NotKnownZero).popcount();
// BFI/BFXIL is an alias of BFM, so translate to BFM operands.
unsigned ImmR = (BitWidth - LSB) % BitWidth;
@ -3505,7 +3505,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
SDValue Src = And1->getOperand(0);
SDValue Dst = And0->getOperand(0);
unsigned LSB = llvm::countr_zero(Mask1Imm);
int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
int Width = BitWidth - APInt(BitWidth, Mask0Imm).popcount();
// The BFXIL inserts the low-order bits from a source register, so right
// shift the needed bits into place.

2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -2115,7 +2115,7 @@ bool AArch64TargetLowering::targetShrinkDemandedConstant(
"i32 or i64 is expected after legalization.");
// Exit early if we demand all bits.
if (DemandedBits.countPopulation() == Size)
if (DemandedBits.popcount() == Size)
return false;
unsigned NewOpc;

2
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
View File

@ -1152,7 +1152,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC,
Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal);
}
unsigned NewNumElts = DemandedElts.countPopulation();
unsigned NewNumElts = DemandedElts.popcount();
if (!NewNumElts)
return UndefValue::get(IIVTy);

2
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -5031,7 +5031,7 @@ void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
int OpIdx) const {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
"Expected G_CONSTANT");
MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation());
MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount());
}
/// This only really exists to satisfy DAG type checking machinery, so is a

2
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -3542,7 +3542,7 @@ static std::optional<std::pair<unsigned, unsigned>>
getContiguousRangeOfSetBits(const APInt &A) {
unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
unsigned LastOne = A.countTrailingZeros();
if (A.countPopulation() != (FirstOne - LastOne + 1))
if (A.popcount() != (FirstOne - LastOne + 1))
return std::nullopt;
return std::make_pair(FirstOne, LastOne);
}

4
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -14687,7 +14687,7 @@ static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) {
SDValue From = N->getOperand(1);
ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue();
FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation());
FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.popcount());
// If the Base came from a SHR #C, we can deduce that it is really testing bit
// #C in the base of the SHR.
@ -17915,7 +17915,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
// Now, is it profitable to continue?
APInt OrCI = OrC->getAPIntValue();
unsigned Heuristic = Subtarget->isThumb() ? 3 : 2;
if (OrCI.countPopulation() > Heuristic)
if (OrCI.popcount() > Heuristic)
return SDValue();
// Lastly, can we determine that the bits defined by OrCI

6
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
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@ -670,8 +670,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
// as the original value.
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
EltTy);
Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
return true;
}
}
@ -702,8 +701,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
// Extract the run of set bits starting with bit zero, and test that the
// result is the same as the original value
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
EltTy);
Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
return true;
}
}

20
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -9401,14 +9401,14 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
LoadMask.setBit(i);
LastLoadedElt = i;
}
assert((ZeroMask.countPopulation() + UndefMask.countPopulation() +
LoadMask.countPopulation()) == NumElems &&
assert((ZeroMask.popcount() + UndefMask.popcount() + LoadMask.popcount()) ==
NumElems &&
"Incomplete element masks");
// Handle Special Cases - all undef or undef/zero.
if (UndefMask.countPopulation() == NumElems)
if (UndefMask.popcount() == NumElems)
return DAG.getUNDEF(VT);
if ((ZeroMask.countPopulation() + UndefMask.countPopulation()) == NumElems)
if ((ZeroMask.popcount() + UndefMask.popcount()) == NumElems)
return VT.isInteger() ? DAG.getConstant(0, DL, VT)
: DAG.getConstantFP(0.0, DL, VT);
@ -11269,7 +11269,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
// our source BUILD_VECTOR, create another FREEZE-UNDEF splat BUILD_VECTOR,
// and blend the FREEZE-UNDEF operands back in.
// FIXME: is this worthwhile even for a single FREEZE-UNDEF operand?
if (unsigned NumFrozenUndefElts = FrozenUndefMask.countPopulation();
if (unsigned NumFrozenUndefElts = FrozenUndefMask.popcount();
NumFrozenUndefElts >= 2 && NumFrozenUndefElts < NumElems) {
SmallVector<int, 16> BlendMask(NumElems, -1);
SmallVector<SDValue, 16> Elts(NumElems, DAG.getUNDEF(OpEltVT));
@ -11320,8 +11320,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (SDValue BitOp = lowerBuildVectorToBitOp(BV, Subtarget, DAG))
return BitOp;
unsigned NumZero = ZeroMask.countPopulation();
unsigned NumNonZero = NonZeroMask.countPopulation();
unsigned NumZero = ZeroMask.popcount();
unsigned NumNonZero = NonZeroMask.popcount();
// If we are inserting one variable into a vector of non-zero constants, try
// to avoid loading each constant element as a scalar. Load the constants as a
@ -38089,7 +38089,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
case X86ISD::PEXT: {
Known = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
// The result has as many leading zeros as the number of zeroes in the mask.
unsigned Count = Known.Zero.countPopulation();
unsigned Count = Known.Zero.popcount();
Known.Zero = APInt::getHighBitsSet(BitWidth, Count);
Known.One.clearAllBits();
break;
@ -43298,7 +43298,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// operand 0 used. Undemanded bits from the mask don't matter so filter
// them before counting.
KnownBits Known2;
uint64_t Count = (~Known.Zero & LoMask).countPopulation();
uint64_t Count = (~Known.Zero & LoMask).popcount();
APInt DemandedMask(APInt::getLowBitsSet(BitWidth, Count));
if (SimplifyDemandedBits(Op0, DemandedMask, Known2, TLO, Depth + 1))
return true;
@ -43411,7 +43411,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
if (IdentityOp == 0)
break;
}
assert((IdentityOp == 0 || IdentityOp.countPopulation() == 1) &&
assert((IdentityOp == 0 || IdentityOp.popcount() == 1) &&
"Multiple identity shuffles detected");
if (IdentityOp != 0)

6
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
View File

@ -4502,7 +4502,7 @@ X86TTIImpl::getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
// series of UNPCK followed by CONCAT_VECTORS - all of these can be
// considered cheap.
if (Ty->isIntOrIntVectorTy())
Cost += DemandedElts.countPopulation();
Cost += DemandedElts.popcount();
// Get the smaller of the legalized or original pow2-extended number of
// vector elements, which represents the number of unpacks we'll end up
@ -4667,7 +4667,7 @@ X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
// then we won't need to do that shuffle, so adjust the cost accordingly.
APInt DemandedDstVectors = APIntOps::ScaleBitMask(
DemandedDstElts.zext(NumDstVectors * NumEltsPerDstVec), NumDstVectors);
unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation();
unsigned NumDstVectorsDemanded = DemandedDstVectors.popcount();
InstructionCost SingleShuffleCost = getShuffleCost(
TTI::SK_PermuteSingleSrc, SingleDstVecTy, /*Mask=*/std::nullopt, CostKind,
@ -4813,7 +4813,7 @@ InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
APInt DemandedElts =
APInt::getBitsSet(CoalescedVecTy->getNumElements(),
CoalescedVecEltIdx, CoalescedVecEltIdx + 1);
assert(DemandedElts.countPopulation() == 1 && "Inserting single value");
assert(DemandedElts.popcount() == 1 && "Inserting single value");
Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
!IsLoad, CostKind);
}

2
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -1653,7 +1653,7 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
// corresponding input elements are undef.
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
if (SubUndef.countPopulation() == Ratio)
if (SubUndef.popcount() == Ratio)
UndefElts.setBit(OutIdx);
}
} else {

2
llvm/lib/Transforms/Utils/Local.cpp
View File

@ -3152,7 +3152,7 @@ collectBitParts(Value *V, bool MatchBSwaps, bool MatchBitReversals,
// Check that the mask allows a multiple of 8 bits for a bswap, for an
// early exit.
unsigned NumMaskedBits = AndMask.countPopulation();
unsigned NumMaskedBits = AndMask.popcount();
if (!MatchBitReversals && (NumMaskedBits % 8) != 0)
return Result;

4
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
View File

@ -5469,7 +5469,7 @@ static bool eliminateDeadSwitchCases(SwitchInst *SI, DomTreeUpdater *DTU,
bool HasDefault =
!isa<UnreachableInst>(SI->getDefaultDest()->getFirstNonPHIOrDbg());
const unsigned NumUnknownBits =
Known.getBitWidth() - (Known.Zero | Known.One).countPopulation();
Known.getBitWidth() - (Known.Zero | Known.One).popcount();
assert(NumUnknownBits <= Known.getBitWidth());
if (HasDefault && DeadCases.empty() &&
NumUnknownBits < 64 /* avoid overflow */ &&
@ -5860,7 +5860,7 @@ static Value *foldSwitchToSelect(const SwitchCaseResultVectorTy &ResultVector,
// Check if cases with the same result can cover all number
// in touched bits.
if (BitMask.countPopulation() == Log2_32(CaseCount)) {
if (BitMask.popcount() == Log2_32(CaseCount)) {
if (!MinCaseVal->isNullValue())
Condition = Builder.CreateSub(Condition, MinCaseVal);
Value *And = Builder.CreateAnd(Condition, ~BitMask, "switch.and");

4
llvm/utils/TableGen/CodeGenSchedule.cpp
View File

@ -370,8 +370,8 @@ processSTIPredicate(STIPredicateFunction &Fn,
const std::pair<APInt, APInt> &RhsMasks = OpcodeMasks[RhsIdx];
auto LessThan = [](const APInt &Lhs, const APInt &Rhs) {
unsigned LhsCountPopulation = Lhs.countPopulation();
unsigned RhsCountPopulation = Rhs.countPopulation();
unsigned LhsCountPopulation = Lhs.popcount();
unsigned RhsCountPopulation = Rhs.popcount();
return ((LhsCountPopulation < RhsCountPopulation) ||
((LhsCountPopulation == RhsCountPopulation) &&
(Lhs.countLeadingZeros() > Rhs.countLeadingZeros())));

5
mlir/lib/Dialect/Math/IR/MathOps.cpp
View File

@ -171,9 +171,8 @@ OpFoldResult math::CountTrailingZerosOp::fold(FoldAdaptor adaptor) {
OpFoldResult math::CtPopOp::fold(FoldAdaptor adaptor) {
return constFoldUnaryOp<IntegerAttr>(
adaptor.getOperands(), [](const APInt &a) {
return APInt(a.getBitWidth(), a.countPopulation());
});
adaptor.getOperands(),
[](const APInt &a) { return APInt(a.getBitWidth(), a.popcount()); });
}
//===----------------------------------------------------------------------===//