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[RISCV] Add MERGE, MVM, and MVMN to isSignExtendedW in RISCVOptWInstrs. (#183433)

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These instructions are a combination of AND/OR/XOR which return sign
extended values if all inputs are sign extended.
This commit is contained in:
Craig Topper 2026-02-25 21:26:13 -08:00 committed by GitHub
parent 8533889a54
commit d12870ea96
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GPG Key ID: B5690EEEBB952194
2 changed files with 132 additions and 3 deletions
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16
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
View File

@ -581,13 +581,17 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
case RISCV::PseudoCCANDN:
case RISCV::PseudoCCORN:
case RISCV::PseudoCCXNOR:
case RISCV::PHI: {
case RISCV::PHI:
case RISCV::MERGE:
case RISCV::MVM:
case RISCV::MVMN: {
// If all incoming values are sign-extended, the output of AND, OR, XOR,
// MIN, MAX, or PHI is also sign-extended.
// MIN, MAX, PHI, or bitwise merge instructions is also sign-extended.
// The input registers for PHI are operand 1, 3, ...
// The input registers for PseudoCCMOVGPR(NoX0) are 4 and 5.
// The input registers for PseudoCCAND/OR/XOR are 4, 5, and 6.
// The input registers for MERGE/MVM/MVMN are 1, 2, and 3.
// The input registers for others are operand 1 and 2.
unsigned B = 1, E = 3, D = 1;
switch (MI->getOpcode()) {
@ -609,7 +613,13 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
B = 4;
E = 7;
break;
}
case RISCV::MERGE:
case RISCV::MVM:
case RISCV::MVMN:
B = 1;
E = 4;
break;
}
for (unsigned I = B; I != E; I += D) {
if (!MI->getOperand(I).isReg())

119
llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir Normal file
View File

@ -0,0 +1,119 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
---
name: merge_sextw_removed
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; CHECK-LABEL: name: merge_sextw_removed
; CHECK: liveins: $x10, $x11, $x12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[ADDW]], [[ADDW1]], [[ADDW2]]
; CHECK-NEXT: $x10 = COPY [[MERGE]]
; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = COPY $x11
%2:gpr = COPY $x12
; ADDW produces sign-extended results
%3:gpr = ADDW %0, %1
%4:gpr = ADDW %1, %2
%5:gpr = ADDW %0, %2
%6:gpr = MERGE %3, %4, %5
%7:gpr = ADDIW %6, 0
$x10 = COPY %7
PseudoRET
...
---
name: mvm_sextw_removed
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; CHECK-LABEL: name: mvm_sextw_removed
; CHECK: liveins: $x10, $x11, $x12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
; CHECK-NEXT: [[MVM:%[0-9]+]]:gpr = MVM [[ADDW]], [[ADDW1]], [[ADDW2]]
; CHECK-NEXT: $x10 = COPY [[MVM]]
; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = COPY $x11
%2:gpr = COPY $x12
%3:gpr = ADDW %0, %1
%4:gpr = ADDW %1, %2
%5:gpr = ADDW %0, %2
%6:gpr = MVM %3, %4, %5
%7:gpr = ADDIW %6, 0
$x10 = COPY %7
PseudoRET
...
---
name: mvmn_sextw_removed
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; CHECK-LABEL: name: mvmn_sextw_removed
; CHECK: liveins: $x10, $x11, $x12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
; CHECK-NEXT: [[MVMN:%[0-9]+]]:gpr = MVMN [[ADDW]], [[ADDW1]], [[ADDW2]]
; CHECK-NEXT: $x10 = COPY [[MVMN]]
; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = COPY $x11
%2:gpr = COPY $x12
%3:gpr = ADDW %0, %1
%4:gpr = ADDW %1, %2
%5:gpr = ADDW %0, %2
%6:gpr = MVMN %3, %4, %5
%7:gpr = ADDIW %6, 0
$x10 = COPY %7
PseudoRET
...
---
name: merge_sextw_not_removed
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; CHECK-LABEL: name: merge_sextw_not_removed
; CHECK: liveins: $x10, $x11, $x12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[COPY]], [[COPY1]], [[COPY2]]
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MERGE]], 0
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = COPY $x11
%2:gpr = COPY $x12
%3:gpr = MERGE %0, %1, %2
%4:gpr = ADDIW %3, 0
$x10 = COPY %4
PseudoRET
...