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AMDGPU/GlobalISel: RegBankLegalize rules for s_setreg (#186872)

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vangthao95 2026-03-17 14:57:29 -07:00 committed by GitHub
parent 8f891a1bb3
commit d13eb6d16e
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GPG Key ID: B5690EEEBB952194
4 changed files with 15 additions and 6 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
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@ -1255,6 +1255,7 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
case SgprB32:
case VgprB32:
case SgprB32_M0:
case SgprB32_ReadFirstLane:
case UniInVgprB32:
if (Ty == LLT::scalar(32) || Ty == LLT::fixed_vector(2, 16) ||
isAnyPtr(Ty, 32))
@ -1723,7 +1724,8 @@ bool RegBankLegalizeHelper::applyMappingSrc(
}
break;
}
case SgprB32_M0: {
case SgprB32_M0:
case SgprB32_ReadFirstLane: {
assert(Ty == getBTyFromID(MethodIDs[i], Ty));
if (RB == SgprRB)
break;

3
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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@ -1452,6 +1452,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_s_getreg}).Any({{}, {{Sgpr32}, {IntrId, Imm}}});
addRulesForIOpcs({amdgcn_s_setreg})
.Any({{_, _, S32}, {{}, {IntrId, Imm, SgprB32_ReadFirstLane}}});
addRulesForIOpcs({amdgcn_groupstaticsize}).Any({{S32}, {{Sgpr32}, {IntrId}}});
// Intrinsics with no register operands.

4
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
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@ -240,6 +240,10 @@ enum RegBankLLTMappingApplyID {
// readfirstlane to SGPR. The result can then be copied to M0 in ISel.
SgprB32_M0,
// Src only modifiers: operand must be SGPR, if in VGPR, insert readfirstlane
// to move to SGPR.
SgprB32_ReadFirstLane,
// Src only modifiers: extends
Sgpr32AExt,
Sgpr32AExtBoolInReg,

10
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
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@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=verde -show-mc-encoding < %s | FileCheck -check-prefixes=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=verde -show-mc-encoding < %s | FileCheck -check-prefixes=GFX6 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11 %s
; FIXME: This test has a DAG duplicate