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[X86] Rename VBROADCASTF128/VBROADCASTI128 to VBROADCASTF128rm/VBROADCASTI128rm (#75040)

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Add missing rm postfix to show these are load instructions
This commit is contained in:
Simon Pilgrim 2023-12-11 11:52:53 +00:00 committed by GitHub
parent 7b7c85d156
commit d1deeae094
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GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 44 additions and 44 deletions
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4
llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
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@ -1285,8 +1285,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
Src2Name = getRegName(MI->getOperand(2).getReg());
break;
case X86::VBROADCASTF128:
case X86::VBROADCASTI128:
case X86::VBROADCASTF128rm:
case X86::VBROADCASTI128rm:
CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
DecodeSubVectorBroadcast(4, 2, ShuffleMask);

4
llvm/lib/Target/X86/X86FixupVectorConstants.cpp
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@ -285,7 +285,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
case X86::VMOVAPSYrm:
case X86::VMOVUPDYrm:
case X86::VMOVUPSYrm:
return ConvertToBroadcast(0, X86::VBROADCASTF128, X86::VBROADCASTSDYrm,
return ConvertToBroadcast(0, X86::VBROADCASTF128rm, X86::VBROADCASTSDYrm,
X86::VBROADCASTSSYrm, 0, 0, 1);
case X86::VMOVAPDZ128rm:
case X86::VMOVAPSZ128rm:
@ -318,7 +318,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
case X86::VMOVDQAYrm:
case X86::VMOVDQUYrm:
return ConvertToBroadcast(
0, HasAVX2 ? X86::VBROADCASTI128 : X86::VBROADCASTF128,
0, HasAVX2 ? X86::VBROADCASTI128rm : X86::VBROADCASTF128rm,
HasAVX2 ? X86::VPBROADCASTQYrm : X86::VBROADCASTSDYrm,
HasAVX2 ? X86::VPBROADCASTDYrm : X86::VBROADCASTSSYrm,
HasAVX2 ? X86::VPBROADCASTWYrm : 0, HasAVX2 ? X86::VPBROADCASTBYrm : 0,

30
llvm/lib/Target/X86/X86InstrSSE.td
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@ -7093,35 +7093,35 @@ def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
// halves of a 256-bit vector.
//
let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in
def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
(ins i128mem:$src),
"vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
Sched<[WriteShuffleLd]>, VEX, VEX_L;
def VBROADCASTI128rm : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
(ins i128mem:$src),
"vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
Sched<[WriteShuffleLd]>, VEX, VEX_L;
let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX],
ExeDomain = SSEPackedSingle in
def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
(ins f128mem:$src),
"vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
def VBROADCASTF128rm : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
(ins f128mem:$src),
"vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
let Predicates = [HasAVX, NoVLX] in {
def : Pat<(v4f64 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
def : Pat<(v8f32 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
// NOTE: We're using FP instructions here, but execution domain fixing can
// convert to integer when profitable.
def : Pat<(v4i64 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
def : Pat<(v8i32 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
def : Pat<(v16i16 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
def : Pat<(v16f16 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
def : Pat<(v32i8 (X86SubVBroadcastld128 addr:$src)),
(VBROADCASTF128 addr:$src)>;
(VBROADCASTF128rm addr:$src)>;
}
//===----------------------------------------------------------------------===//

8
llvm/lib/Target/X86/X86MCInstLower.cpp
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@ -1865,8 +1865,8 @@ static void addConstantComments(const MachineInstr *MI,
// For loads from a constant pool to a vector register, print the constant
// loaded.
CASE_ALL_MOV_RM()
case X86::VBROADCASTF128:
case X86::VBROADCASTI128:
case X86::VBROADCASTF128rm:
case X86::VBROADCASTI128rm:
case X86::VBROADCASTF32X4Z256rm:
case X86::VBROADCASTF32X4rm:
case X86::VBROADCASTF32X8rm:
@ -1891,8 +1891,8 @@ static void addConstantComments(const MachineInstr *MI,
CASE_128_MOV_RM() NumLanes = 1; BitWidth = 128; break;
CASE_256_MOV_RM() NumLanes = 1; BitWidth = 256; break;
CASE_512_MOV_RM() NumLanes = 1; BitWidth = 512; break;
case X86::VBROADCASTF128: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTI128: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTF128rm: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTI128rm: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTF32X4rm: NumLanes = 4; BitWidth = 128; break;
case X86::VBROADCASTF32X8rm: NumLanes = 2; BitWidth = 256; break;

2
llvm/lib/Target/X86/X86ReplaceableInstrs.def
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@ -202,7 +202,7 @@ ENTRY(VBROADCASTSSYrr, VBROADCASTSSYrr, VPBROADCASTDYrr)
ENTRY(VBROADCASTSSYrm, VBROADCASTSSYrm, VPBROADCASTDYrm)
ENTRY(VBROADCASTSDYrr, VBROADCASTSDYrr, VPBROADCASTQYrr)
ENTRY(VBROADCASTSDYrm, VBROADCASTSDYrm, VPBROADCASTQYrm)
ENTRY(VBROADCASTF128, VBROADCASTF128, VBROADCASTI128)
ENTRY(VBROADCASTF128rm, VBROADCASTF128rm, VBROADCASTI128rm)
ENTRY(VBLENDPSYrri, VBLENDPSYrri, VPBLENDDYrri)
ENTRY(VBLENDPSYrmi, VBLENDPSYrmi, VPBLENDDYrmi)
ENTRY(VPERMILPSYmi, VPERMILPSYmi, VPSHUFDYmi)

2
llvm/lib/Target/X86/X86SchedAlderlakeP.td
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@ -1328,7 +1328,7 @@ def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 8;
}
def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",
"^VBROADCAST(F|I)128$",
"^VBROADCAST(F|I)128rm$",
"^VBROADCASTS(D|S)Yrm$",
"^VMOV(D|SH|SL)DUPYrm$",
"^VPBROADCAST(D|Q)Yrm$")>;

4
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -946,8 +946,8 @@ def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
VBROADCASTI128,
def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128rm,
VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,

4
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -876,8 +876,8 @@ def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
}
def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
VBROADCASTI128,
def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128rm,
VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,

4
llvm/lib/Target/X86/X86SchedIceLake.td
View File

@ -1274,8 +1274,8 @@ def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
VBROADCASTI128,
def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128rm,
VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,

2
llvm/lib/Target/X86/X86SchedSapphireRapids.td
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@ -1599,7 +1599,7 @@ def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_11]> {
let Latency = 8;
}
def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$",
"^VBROADCAST(F|I)128$",
"^VBROADCAST(F|I)128rm$",
"^VBROADCAST(F|I)32X(2|4)Z256rm$",
"^VBROADCAST(F|I)32X(8|2Z)rm$",
"^VBROADCAST(F|I)(32|64)X4rm$",

4
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -1064,8 +1064,8 @@ def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
VBROADCASTI128,
def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,
VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,

4
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -1254,8 +1254,8 @@ def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
VBROADCASTI128,
def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128rm,
VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,

2
llvm/lib/Target/X86/X86ScheduleBdVer2.td
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@ -933,7 +933,7 @@ def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let ReleaseAtCycles = [1, 3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128rm)>;
defm : PdWriteResXMMPair<WriteFVarShuffle, [PdFPU1, PdFPXBR], 3>;
defm : PdWriteResYMMPair<WriteFVarShuffleY, [PdFPU1, PdFPXBR], 3, [2, 2], 2>;

2
llvm/lib/Target/X86/X86ScheduleBtVer2.td
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@ -816,7 +816,7 @@ def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
}
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
VBROADCASTSSYrm,
VBROADCASTF128)>;
VBROADCASTF128rm)>;
def JWriteJVZEROALL: SchedWriteRes<[]> {
let Latency = 90;

4
llvm/lib/Target/X86/X86ScheduleZnver1.td
View File

@ -996,8 +996,8 @@ def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> {
let Latency = 8;
}
// VBROADCASTF128 / VBROADCASTI128.
def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
VBROADCASTI128)>;
def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128rm,
VBROADCASTI128rm)>;
// EXTRACTPS.
// r32,x,i.

4
llvm/lib/Target/X86/X86ScheduleZnver2.td
View File

@ -1004,8 +1004,8 @@ def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
let Latency = 8;
}
// VBROADCASTF128 / VBROADCASTI128.
def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
VBROADCASTI128)>;
def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128rm,
VBROADCASTI128rm)>;
// EXTRACTPS.
// r32,x,i.

4
llvm/test/CodeGen/X86/evex-to-vex-compress.mir
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@ -677,7 +677,7 @@ body: |
$ymm0 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VPMOVZXWQYrr $xmm0
$ymm0 = VPMOVZXWQZ256rr $xmm0
; CHECK: $ymm0 = VBROADCASTF128 $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VBROADCASTF128rm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg
@ -703,7 +703,7 @@ body: |
$ymm0 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VPBROADCASTWYrr $xmm0
$ymm0 = VPBROADCASTWZ256rr $xmm0
; CHECK: $ymm0 = VBROADCASTI128 $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VBROADCASTI128rm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg