Manual instruction lowering
This commit is contained in:
parent
ddf3a97f70
commit
d2159076c8
@ -4,7 +4,7 @@
|
||||
|
||||
static const char* FootDataLayoutStr =
|
||||
"e-"
|
||||
"p:16:32-"
|
||||
"p:32:32-"
|
||||
"n8:16:32-"
|
||||
"i64:64:64-i32:32:32-i16:16:32-"
|
||||
"f32:32:32-"
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
#include "FootISelLowering.h"
|
||||
#include "Foot.h"
|
||||
#include "FootTargetMachine.h"
|
||||
#include "MCTargetDesc/FootMCTargetDesc.h"
|
||||
#include "llvm/CodeGen/SelectionDAGISel.h"
|
||||
|
||||
using namespace llvm;
|
||||
@ -9,6 +11,10 @@ public:
|
||||
explicit FootDAGToDAGISel(TargetMachine &TM) : SelectionDAGISel(TM) {}
|
||||
|
||||
private:
|
||||
void SelectStore(SDNode *N, SDLoc &DL);
|
||||
void SelectAdd(SDNode *N, SDLoc &DL);
|
||||
void SelectReturnGlue(SDNode *N, SDLoc &DL);
|
||||
|
||||
void Select(SDNode *N) override;
|
||||
#include "FootGenDAGISel.inc"
|
||||
};
|
||||
@ -20,12 +26,81 @@ public:
|
||||
: SelectionDAGISelLegacy(ID, std::make_unique<FootDAGToDAGISel>(TM)) {}
|
||||
};
|
||||
|
||||
void FootDAGToDAGISel::SelectAdd(SDNode *N, SDLoc &DL) {
|
||||
SDValue LHS = N->getOperand(0);
|
||||
SDValue RHS = N->getOperand(1);
|
||||
}
|
||||
|
||||
void FootDAGToDAGISel::SelectStore(SDNode *N, SDLoc &DL) {
|
||||
StoreSDNode *SN = cast<StoreSDNode>(N);
|
||||
SDValue Val = SN->getValue();
|
||||
SDValue Addr = SN->getBasePtr();
|
||||
SDValue Chain = SN->getChain();
|
||||
|
||||
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
||||
Addr = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
||||
}
|
||||
else if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Addr)) {
|
||||
Addr = CurDAG->getTargetGlobalAddress(GAN->getGlobal(), DL, MVT::i32);
|
||||
}
|
||||
|
||||
SDNode *NewNode;
|
||||
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
|
||||
SDValue Imm = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32);
|
||||
|
||||
SDValue Ops[] = { Addr, Imm, Chain };
|
||||
NewNode = CurDAG->getMachineNode(Foot::CNST_I_A, DL, MVT::Other, Ops);
|
||||
}
|
||||
else {
|
||||
SDValue Zero = CurDAG->getRegister(Foot::R0, MVT::i32);
|
||||
|
||||
SDValue Ops[] = { Addr, Val, Zero, Chain };
|
||||
NewNode = CurDAG->getMachineNode(Foot::BWOR_I_D_M_A, DL, MVT::Other, Ops);
|
||||
}
|
||||
|
||||
ReplaceNode(N, NewNode);
|
||||
}
|
||||
|
||||
void FootDAGToDAGISel::SelectReturnGlue(SDNode *N, SDLoc &DL) {
|
||||
SDValue Chain = N->getOperand(0);
|
||||
SDValue RetVal = N->getOperand(1);
|
||||
|
||||
SDValue R0Val = CurDAG->getCopyToReg(Chain, DL, Foot::R0, RetVal);
|
||||
|
||||
SDValue RetAddr = CurDAG->getTargetFrameIndex(0, MVT::i32);
|
||||
|
||||
SDValue PC = CurDAG->getRegister(Foot::RPC, MVT::i32);
|
||||
SDValue Zero = CurDAG->getRegister(Foot::R0, MVT::i32);
|
||||
SDValue Ops[] = { PC, RetAddr, Zero, R0Val.getOperand(1) };
|
||||
SDNode *NewNode = CurDAG->getMachineNode(Foot::BWOR_D_I_M_A, DL, MVT::Other, Ops);
|
||||
|
||||
ReplaceNode(N, NewNode);
|
||||
}
|
||||
|
||||
void FootDAGToDAGISel::Select(SDNode *N) {
|
||||
if (N->isMachineOpcode()) {
|
||||
return;
|
||||
}
|
||||
|
||||
SelectCode(N);
|
||||
SDLoc DL(N);
|
||||
|
||||
switch (N->getOpcode()) {
|
||||
case ISD::ADD:
|
||||
SelectAdd(N, DL);
|
||||
break;
|
||||
|
||||
case ISD::STORE:
|
||||
SelectStore(N, DL);
|
||||
break;
|
||||
|
||||
case FootISD::RETURN_GLUE:
|
||||
SelectReturnGlue(N, DL);
|
||||
break;
|
||||
|
||||
default:
|
||||
SelectCode(N);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
char FootDAGToDAGISelLegacy::ID = 0;
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
#include "FootCallingConvention.h"
|
||||
#include "FootISelLowering.h"
|
||||
#include "FootSubtarget.h"
|
||||
#include "MCTargetDesc/FootMCTargetDesc.h"
|
||||
#include "llvm/CodeGen/CallingConvLower.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "FootSubtarget.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -11,8 +11,47 @@ FootTargetLowering::FootTargetLowering(const TargetMachine &TM,
|
||||
const FootSubtarget &STI)
|
||||
: TargetLowering(TM), Subtarget(STI) {
|
||||
addRegisterClass(MVT::i32, &Foot::GP32RegClass);
|
||||
addRegisterClass(MVT::v2i16, &Foot::GP32RegClass);
|
||||
addRegisterClass(MVT::v4i8, &Foot::GP32RegClass);
|
||||
//addRegisterClass(MVT::v2i16, &Foot::GP32RegClass);
|
||||
//addRegisterClass(MVT::v4i8, &Foot::GP32RegClass);
|
||||
|
||||
setOperationAction(ISD::ADD, MVT::i32, Legal);
|
||||
setOperationAction(ISD::SUB, MVT::i32, Legal);
|
||||
setOperationAction(ISD::MUL, MVT::i32, Legal);
|
||||
setOperationAction(ISD::UDIV, MVT::i32, Legal);
|
||||
setOperationAction(ISD::UREM, MVT::i32, Legal);
|
||||
setOperationAction(ISD::SHL, MVT::i32, Legal);
|
||||
setOperationAction(ISD::ROTL, MVT::i32, Legal);
|
||||
setOperationAction(ISD::SRA, MVT::i32, Legal);
|
||||
setOperationAction(ISD::OR, MVT::i32, Legal);
|
||||
setOperationAction(ISD::AND, MVT::i32, Legal);
|
||||
setOperationAction(ISD::XOR, MVT::i32, Legal);
|
||||
setOperationAction(ISD::STORE, MVT::i32, Legal);
|
||||
setOperationAction(ISD::LOAD, MVT::i32, Legal);
|
||||
|
||||
/*
|
||||
setOperationAction(ISD::ADD, MVT::v2i16, Legal);
|
||||
setOperationAction(ISD::SUB, MVT::v2i16, Legal);
|
||||
setOperationAction(ISD::MUL, MVT::v2i16, Legal);
|
||||
setOperationAction(ISD::UDIV, MVT::v2i16, Legal);
|
||||
setOperationAction(ISD::OR, MVT::v2i16, Legal);
|
||||
setOperationAction(ISD::AND, MVT::v2i16, Legal);
|
||||
setOperationAction(ISD::XOR, MVT::v2i16, Legal);
|
||||
|
||||
setOperationAction(ISD::ADD, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::SUB, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::MUL, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::UDIV, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::UREM, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::OR, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::AND, MVT::v4i8, Legal);
|
||||
setOperationAction(ISD::XOR, MVT::v4i8, Legal);
|
||||
|
||||
setOperationAction(ISD::FADD, MVT::f32, LibCall);
|
||||
setOperationAction(ISD::FSUB, MVT::f32, LibCall);
|
||||
setOperationAction(ISD::FMUL, MVT::f32, LibCall);
|
||||
setOperationAction(ISD::FDIV, MVT::f32, LibCall);
|
||||
setOperationAction(ISD::FREM, MVT::f32, LibCall);
|
||||
*/
|
||||
|
||||
computeRegisterProperties(Subtarget.getRegisterInfo());
|
||||
}
|
||||
@ -200,6 +239,7 @@ SDValue FootTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDV
|
||||
DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
|
||||
|
||||
SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo);
|
||||
MemOpChains.push_back(Store);
|
||||
}
|
||||
|
||||
if (!MemOpChains.empty()) {
|
||||
@ -256,7 +296,7 @@ SDValue FootTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDV
|
||||
for (size_t I = 0, E = RetValLocs.size(); I != E; ++I) {
|
||||
CCValAssign &VA = RetValLocs[I];
|
||||
assert(VA.isRegLoc() && "stack return not yet implemented");
|
||||
assert(VA.getLocInf() == CCValAssign::Full && "extension/truncation not yet implemented");
|
||||
assert(VA.getLocInfo() == CCValAssign::Full && "extension/truncation not yet implemented");
|
||||
|
||||
Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getValVT(), InGlue)
|
||||
.getValue(1);
|
||||
|
||||
@ -232,7 +232,7 @@ multiclass _mmmFootInstructionC<string asm, string operands,
|
||||
bits<4> opcode,
|
||||
bits<2> dstmode, bits<2> amode,
|
||||
bits<2> bmode,
|
||||
dag oops = (outs), dag iops = (ins)> {
|
||||
dag oops, dag iops> {
|
||||
def _A : _FootInstructionC<asm, operands, opcode, dstmode, amode, bmode, 0b0, oops, iops> {
|
||||
let Condition = 0b000;
|
||||
}
|
||||
@ -291,25 +291,28 @@ multiclass _mmmFootInstructionC<string asm, string operands,
|
||||
}
|
||||
|
||||
multiclass _mmFootInstructionC<string asm, string operands,
|
||||
bits<4> opcode,
|
||||
bits<2> amode, bits<2> bmode> {
|
||||
defm _M : _mmmFootInstructionC<!strconcat(asm, ".m"), operands, opcode, 0b00, amode, bmode, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm _D : _mmmFootInstructionC<!strconcat(asm, ".d"), operands, opcode, 0b01, amode, bmode, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm _I : _mmmFootInstructionC<!strconcat(asm, ".i"), operands, opcode, 0b10, amode, bmode, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm _A : _mmmFootInstructionC<!strconcat(asm, ".a"), operands, opcode, 0b11, amode, bmode, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
bits<4> opcode,
|
||||
bits<2> amode, bits<2> bmode,
|
||||
dag oops, dag iops> {
|
||||
defm _M : _mmmFootInstructionC<!strconcat(asm, ".m"), operands, opcode, 0b00, amode, bmode, oops, iops>;
|
||||
defm _D : _mmmFootInstructionC<!strconcat(asm, ".d"), operands, opcode, 0b01, amode, bmode, oops, iops>;
|
||||
defm _I : _mmmFootInstructionC<!strconcat(asm, ".i"), operands, opcode, 0b10, amode, bmode, oops, iops>;
|
||||
defm _A : _mmmFootInstructionC<!strconcat(asm, ".a"), operands, opcode, 0b11, amode, bmode, oops, iops>;
|
||||
}
|
||||
|
||||
multiclass _mFootInstructionC<string asm, string operands,
|
||||
bits<4> opcode, bits<2> bmode> {
|
||||
defm _M : _mmFootInstructionC<!strconcat(asm, ".m"), operands, opcode, 0b00, bmode>;
|
||||
defm _D : _mmFootInstructionC<!strconcat(asm, ".d"), operands, opcode, 0b01, bmode>;
|
||||
defm _I : _mmFootInstructionC<!strconcat(asm, ".i"), operands, opcode, 0b10, bmode>;
|
||||
defm _A : _mmFootInstructionC<!strconcat(asm, ".a"), operands, opcode, 0b11, bmode>;
|
||||
bits<4> opcode, bits<2> bmode,
|
||||
dag oops, dag iops> {
|
||||
defm _M : _mmFootInstructionC<!strconcat(asm, ".m"), operands, opcode, 0b00, bmode, oops, iops>;
|
||||
defm _D : _mmFootInstructionC<!strconcat(asm, ".d"), operands, opcode, 0b01, bmode, oops, iops>;
|
||||
defm _I : _mmFootInstructionC<!strconcat(asm, ".i"), operands, opcode, 0b10, bmode, oops, iops>;
|
||||
defm _A : _mmFootInstructionC<!strconcat(asm, ".a"), operands, opcode, 0b11, bmode, oops, iops>;
|
||||
}
|
||||
|
||||
multiclass FootInstructionC<string asm, bits<4> opcode> {
|
||||
defm _M : _mFootInstructionC<!strconcat(asm, ".m"), "$dst, $a, $b", opcode, 0b00>;
|
||||
defm _D : _mFootInstructionC<!strconcat(asm, ".d"), "$dst, $a, $b", opcode, 0b01>;
|
||||
defm _I : _mFootInstructionC<!strconcat(asm, ".i"), "$dst, $a, $b", opcode, 0b10>;
|
||||
defm _A : _mFootInstructionC<!strconcat(asm, ".a"), "$dst, $a, $b", opcode, 0b11>;
|
||||
multiclass FootInstructionC<string asm, bits<4> opcode,
|
||||
dag oops = (outs), dag iops = (ins)> {
|
||||
defm _M : _mFootInstructionC<!strconcat(asm, ".m"), "$dst, $a, $b", opcode, 0b00, oops, iops>;
|
||||
defm _D : _mFootInstructionC<!strconcat(asm, ".d"), "$dst, $a, $b", opcode, 0b01, oops, iops>;
|
||||
defm _I : _mFootInstructionC<!strconcat(asm, ".i"), "$dst, $a, $b", opcode, 0b10, oops, iops>;
|
||||
defm _A : _mFootInstructionC<!strconcat(asm, ".a"), "$dst, $a, $b", opcode, 0b11, oops, iops>;
|
||||
}
|
||||
|
||||
@ -1,8 +1,60 @@
|
||||
#include "FootInstrInfo.h"
|
||||
|
||||
#include "MCTargetDesc/FootMCTargetDesc.h"
|
||||
|
||||
#define GET_INSTRINFO_CTOR_DTOR
|
||||
#include "FootGenInstrInfo.inc"
|
||||
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
FootInstrInfo::FootInstrInfo() : FootGenInstrInfo() {}
|
||||
|
||||
void FootInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
Register SrcReg, bool IsKill, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI,
|
||||
Register VReg,
|
||||
MachineInstr::MIFlag Flag) const {
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
|
||||
MachineMemOperand *MMO =
|
||||
MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
|
||||
MFI.getObjectSize(FrameIndex), MFI.getObjectAlign(FrameIndex));
|
||||
|
||||
unsigned Opc = Foot::ADDI_I_D_M_A;
|
||||
MFI.setStackID(FrameIndex, TargetStackID::Default);
|
||||
BuildMI(MBB, MI, DebugLoc(), get(Opc))
|
||||
.addReg(SrcReg, getKillRegState(IsKill))
|
||||
.addFrameIndex(FrameIndex)
|
||||
// this needs some refactoring. this is technically an immediate for this format
|
||||
.addReg(0)
|
||||
.addMemOperand(MMO);
|
||||
}
|
||||
|
||||
void FootInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
Register DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI,
|
||||
Register VReg,
|
||||
MachineInstr::MIFlag Flag) const {
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
|
||||
MachineMemOperand *MMO =
|
||||
MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
|
||||
MFI.getObjectSize(FrameIndex), MFI.getObjectAlign(FrameIndex));
|
||||
|
||||
unsigned Opc = Foot::ADDI_D_I_M_A;
|
||||
MFI.setStackID(FrameIndex, TargetStackID::Default);
|
||||
BuildMI(MBB, MI, DebugLoc(), get(Opc))
|
||||
.addReg(DestReg)
|
||||
.addFrameIndex(FrameIndex)
|
||||
// this needs some refactoring. this is technically an immediate for this format
|
||||
.addReg(0)
|
||||
.addMemOperand(MMO);
|
||||
}
|
||||
|
||||
@ -11,6 +11,22 @@ namespace llvm {
|
||||
class FootInstrInfo : public FootGenInstrInfo {
|
||||
public:
|
||||
FootInstrInfo();
|
||||
|
||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
Register SrcReg, bool IsKill, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI,
|
||||
Register VReg,
|
||||
MachineInstr::MIFlag Flags) const override;
|
||||
|
||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
Register DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI,
|
||||
Register VReg,
|
||||
MachineInstr::MIFlag Flags) const override;
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
@ -5,27 +5,32 @@ defm CNST_D : FootInstructionA<"CNST.d", "$dst, $imm", 0b0000, 0b01, (outs GP32:
|
||||
defm CNST_I : FootInstructionA<"CNST.i", "$dst, $imm", 0b0000, 0b10, (outs GP32:$dst), (ins i16imm:$imm)>;
|
||||
defm CNST_A : FootInstructionA<"CNST.a", "$dst, $imm", 0b0000, 0b11, (outs GP32:$dst), (ins i16imm:$imm)>;
|
||||
|
||||
defm PC_CNST_M : FootInstructionA<"CNST.m", "$dst, $imm", 0b0000, 0b00, (outs PC32:$dst), (ins i16imm:$imm)>;
|
||||
defm PC_CNST_D : FootInstructionA<"CNST.d", "$dst, $imm", 0b0000, 0b01, (outs PC32:$dst), (ins i16imm:$imm)>;
|
||||
defm PC_CNST_I : FootInstructionA<"CNST.i", "$dst, $imm", 0b0000, 0b10, (outs PC32:$dst), (ins i16imm:$imm)>;
|
||||
defm PC_CNST_A : FootInstructionA<"CNST.a", "$dst, $imm", 0b0000, 0b11, (outs PC32:$dst), (ins i16imm:$imm)>;
|
||||
|
||||
defm CMPR : FootInstructionB<"CMPR", 0b00000000>;
|
||||
defm BWNG : FootInstructionB<"BWNG", 0b00000001>;
|
||||
defm ARNG : FootInstructionB<"ARNG", 0b00000010>;
|
||||
defm LONG : FootInstructionB<"LONG", 0b00000011>;
|
||||
defm CONF : FootInstructionB<"CONF", 0b00000100>;
|
||||
|
||||
defm BWOR : FootInstructionC<"BWOR", 0b0010>;
|
||||
defm BAND : FootInstructionC<"BAND", 0b0011>;
|
||||
defm BXOR : FootInstructionC<"BXOR", 0b0100>;
|
||||
defm SRSH : FootInstructionC<"SRSH", 0b0110>;
|
||||
defm ZLSH : FootInstructionC<"ZLSH", 0b0111>;
|
||||
defm CLSH : FootInstructionC<"CLSH", 0b1000>;
|
||||
defm ADDI : FootInstructionC<"ADDI", 0b1001>;
|
||||
defm SUBT : FootInstructionC<"SUBT", 0b1010>;
|
||||
defm MULT : FootInstructionC<"MULT", 0b1011>;
|
||||
defm DIVI : FootInstructionC<"DIVI", 0b1100>;
|
||||
defm MODU : FootInstructionC<"MODU", 0b1101>;
|
||||
defm BWOR : FootInstructionC<"BWOR", 0b0010, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm BAND : FootInstructionC<"BAND", 0b0011, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm BXOR : FootInstructionC<"BXOR", 0b0100, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm SRSH : FootInstructionC<"SRSH", 0b0110, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm ZLSH : FootInstructionC<"ZLSH", 0b0111, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm CLSH : FootInstructionC<"CLSH", 0b1000, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm ADDI : FootInstructionC<"ADDI", 0b1001, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm SUBT : FootInstructionC<"SUBT", 0b1010, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm MULT : FootInstructionC<"MULT", 0b1011, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm DIVI : FootInstructionC<"DIVI", 0b1100, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
defm MODU : FootInstructionC<"MODU", 0b1101, (outs GP32:$dst), (ins GP32:$a, GP32:$b)>;
|
||||
|
||||
def Footreturnglue : SDNode<"Foot::RETURN_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
||||
def Footreturnglue : SDNode<"FootISD::RETURN_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
||||
|
||||
def Footcall : SDNode<"Foot::CALL",
|
||||
def Footcall : SDNode<"FootISD::CALL",
|
||||
SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
|
||||
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
|
||||
SDNPVariadic]>;
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
#include "MCTargetDesc/FootMCTargetDesc.h"
|
||||
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
||||
|
||||
@ -12,10 +13,18 @@
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
namespace {
|
||||
|
||||
MCPhysReg CSR_SaveList[] = {
|
||||
0
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
FootRegisterInfo::FootRegisterInfo() : FootGenRegisterInfo(Foot::RRA) {}
|
||||
|
||||
const MCPhysReg *FootRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
|
||||
return nullptr;
|
||||
return CSR_SaveList;
|
||||
}
|
||||
|
||||
BitVector FootRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
@ -24,8 +33,30 @@ BitVector FootRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
}
|
||||
|
||||
bool FootRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
/*
|
||||
MachineInstr &MI = *II;
|
||||
MachineBasicBlock &MBB = *MI.getParent();
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
const MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
|
||||
MachineOperand &FIOp = MI.getOperand(FIOperandNum);
|
||||
int Index = FIOp.getIndex();
|
||||
int64_t Offset = MFI.getObjectOffset(Index);
|
||||
// adjust to account for stack pointer adjusted before load/store
|
||||
Offset += MFI.getStackSize();
|
||||
assert(FIOperandNum == 1 && "Stack argument is expected to be the second"
|
||||
"operand for both loads and stores");
|
||||
|
||||
switch (MI.getOpcode()) {
|
||||
case Foot::ADDI_D_D_D_A:
|
||||
case Foot::SUBT_D_D_D_A:
|
||||
}
|
||||
*/
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#ifndef LLVM_LIB_TARGET_FOOT_FOOTTARGETMACHINE_H
|
||||
#define LLVM_LIB_TARGET_FOOT_FOOTTARGETMACHINE_H
|
||||
#ifndef LLVM_LIB_TARGET_FOOT_FOOTREGISTERINFO_H
|
||||
#define LLVM_LIB_TARGET_FOOT_FOOTREGISTERINFO_H
|
||||
|
||||
#include "llvm/CodeGen/TargetRegisterInfo.h"
|
||||
|
||||
@ -11,7 +11,7 @@ namespace llvm {
|
||||
struct FootRegisterInfo : public FootGenRegisterInfo {
|
||||
FootRegisterInfo();
|
||||
|
||||
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
||||
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
||||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
|
||||
@ -24,4 +24,4 @@ struct FootRegisterInfo : public FootGenRegisterInfo {
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_FOOT_FOOTTARGETMACHINE_H
|
||||
#endif // LLVM_LIB_TARGET_FOOT_FOOTREGISTERINFO_H
|
||||
|
||||
@ -41,5 +41,6 @@ def RLC : FootRegister<30, "rlc">; /* loop counter */
|
||||
def RPC : FootRegister<31, "rpc">; /* program counter */
|
||||
|
||||
def GP32 : RegisterClass<"Foot", [i32], 32, (sequence "R%u", 0, 27)>;
|
||||
def PC32 : RegisterClass<"Foot", [i32], 32, (add RPC)>;
|
||||
|
||||
}
|
||||
|
||||
@ -7,8 +7,8 @@ using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "foot-subtarget"
|
||||
|
||||
#define GET_SUBTARGET_TARGET_DESC
|
||||
#define GET_SUBTARGET_CTOR
|
||||
#define GET_SUBTARGETINFO_TARGET_DESC
|
||||
#define GET_SUBTARGETINFO_CTOR
|
||||
#include "FootGenSubtargetInfo.inc"
|
||||
|
||||
// Pin the vtable to this file.
|
||||
|
||||
@ -1,14 +1,15 @@
|
||||
#include "Foot.h"
|
||||
#include "FootTargetMachine.h"
|
||||
#include "TargetInfo/FootTargetInfo.h"
|
||||
#include "FootTargetObjectFile.h"
|
||||
#include "TargetInfo/FootTargetInfo.h"
|
||||
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
|
||||
#include "llvm/MC/TargetRegistry.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
static const char* FootDataLayoutStr =
|
||||
"e-"
|
||||
"p:16:32-"
|
||||
"p:32:32-"
|
||||
"n8:16:32-"
|
||||
"i64:64:64-i32:32:32-i16:16:32-"
|
||||
"f32:32:32-"
|
||||
@ -39,6 +40,20 @@ TargetLoweringObjectFile *FootTargetMachine::getObjFileLowering() const {
|
||||
return &TLOF;
|
||||
}
|
||||
|
||||
const FootSubtarget *FootTargetMachine::getSubtargetImpl(const Function &F) const {
|
||||
Attribute CPUAttr = F.getFnAttribute("target-cpu");
|
||||
Attribute FSAttr = F.getFnAttribute("target-features");
|
||||
|
||||
StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
|
||||
StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
|
||||
|
||||
if (!SubtargetSingleton) {
|
||||
SubtargetSingleton = std::make_unique<FootSubtarget>(TargetTriple, CPU, FS, *this);
|
||||
}
|
||||
|
||||
return SubtargetSingleton.get();
|
||||
}
|
||||
|
||||
FootPassConfig::FootPassConfig(TargetMachine &TM, PassManagerBase &PM) :
|
||||
TargetPassConfig(TM, PM) {}
|
||||
|
||||
|
||||
@ -1,12 +1,14 @@
|
||||
#ifndef LLVM_LIB_TARGET_FOOT_FOOTTARGETMACHINE_H
|
||||
#define LLVM_LIB_TARGET_FOOT_FOOTTARGETMACHINE_H
|
||||
|
||||
#include "FootSubtarget.h"
|
||||
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
|
||||
#include "llvm/CodeGen/TargetPassConfig.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class FootTargetMachine : public CodeGenTargetMachineImpl {
|
||||
mutable std::unique_ptr<FootSubtarget> SubtargetSingleton;
|
||||
public:
|
||||
FootTargetMachine(const Target &T, const Triple &TT,
|
||||
StringRef CPU, StringRef FS,
|
||||
@ -19,6 +21,8 @@ public:
|
||||
|
||||
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
||||
TargetLoweringObjectFile *getObjFileLowering() const override;
|
||||
|
||||
const FootSubtarget *getSubtargetImpl(const Function &) const override;
|
||||
};
|
||||
|
||||
class FootPassConfig : public TargetPassConfig {
|
||||
|
||||
@ -1,10 +1,12 @@
|
||||
add_llvm_component_library(LLVMFootDesc
|
||||
FootMCAsmBackend.cpp
|
||||
FootMCTargetDesc.cpp
|
||||
FootAsmInfo.cpp
|
||||
FootMCCodeEmitter.cpp
|
||||
FootInstPrinter.cpp
|
||||
|
||||
LINK_COMPONENTS
|
||||
BinaryFormat
|
||||
Support
|
||||
|
||||
ADD_TO_COMPONENT
|
||||
|
||||
@ -38,8 +38,7 @@ void FootInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
||||
else if (Op.isImm()) {
|
||||
printImm(MI, OpNo, O);
|
||||
}
|
||||
else {
|
||||
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
||||
else if (Op.isExpr()) {
|
||||
MAI.printExpr(O, *Op.getExpr());
|
||||
}
|
||||
}
|
||||
|
||||
57
llvm/lib/Target/Foot/MCTargetDesc/FootMCAsmBackend.cpp
Normal file
57
llvm/lib/Target/Foot/MCTargetDesc/FootMCAsmBackend.cpp
Normal file
@ -0,0 +1,57 @@
|
||||
#include "MCTargetDesc/FootMCTargetDesc.h"
|
||||
#include "llvm/MC/MCAsmBackend.h"
|
||||
#include "llvm/MC/MCELFObjectWriter.h"
|
||||
#include "llvm/MC/MCSubtargetInfo.h"
|
||||
#include "llvm/MC/TargetRegistry.h"
|
||||
#include "llvm/Support/CodeGen.h"
|
||||
#include "llvm/TargetParser/Triple.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
namespace {
|
||||
|
||||
class FootELFObjectWriter : public MCELFObjectTargetWriter {
|
||||
public:
|
||||
FootELFObjectWriter()
|
||||
: MCELFObjectTargetWriter(false, ELF::ELFOSABI_NONE, 0, false) {}
|
||||
|
||||
unsigned getRelocType(const MCFixup &Fixup, const MCValue &Target, bool IsPcRel) const override {
|
||||
return Reloc::Static;
|
||||
}
|
||||
};
|
||||
|
||||
class FootAsmBackend : public MCAsmBackend {
|
||||
Triple TheTriple;
|
||||
|
||||
public:
|
||||
FootAsmBackend(const Triple &TT)
|
||||
: MCAsmBackend(endianness::little), TheTriple(TT) {}
|
||||
|
||||
std::unique_ptr<MCObjectTargetWriter>
|
||||
createObjectTargetWriter() const override {
|
||||
return std::make_unique<FootELFObjectWriter>();
|
||||
}
|
||||
|
||||
void applyFixup(const MCFragment &, const MCFixup &Fixup,
|
||||
const MCValue &Target, uint8_t* Data, uint64_t Value,
|
||||
bool IsResolved) override {}
|
||||
|
||||
bool writeNopData(raw_ostream &OS, uint64_t Count,
|
||||
const MCSubtargetInfo *STI) const override {
|
||||
for (uint64_t I = 0; I != Count; ++I) {
|
||||
OS.write("\x00\x00\x00\x00", 4);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
MCAsmBackend *llvm::createFootAsmBackend(const Target &T,
|
||||
const MCSubtargetInfo &STI,
|
||||
const MCRegisterInfo &,
|
||||
const MCTargetOptions &) {
|
||||
const Triple &TheTriple = STI.getTargetTriple();
|
||||
return new FootAsmBackend(TheTriple);
|
||||
}
|
||||
@ -60,5 +60,6 @@ extern "C" LLVM_C_ABI void LLVMInitializeFootTargetMC() {
|
||||
TargetRegistry::RegisterMCRegInfo(TheTarget, createFootRegisterInfo);
|
||||
TargetRegistry::RegisterMCInstPrinter(TheTarget, createFootMCInstPrinter);
|
||||
TargetRegistry::RegisterMCCodeEmitter(TheTarget, createFootMCCodeEmitter);
|
||||
TargetRegistry::RegisterMCAsmBackend(TheTarget, createFootAsmBackend);
|
||||
RegisterMCAsmInfoFn X(TheTarget, createFootMCAsmInfo);
|
||||
}
|
||||
|
||||
@ -1,7 +1,9 @@
|
||||
#ifndef LLVM_LIB_TARGET_FOOT_MC_TARGET_DESC_H
|
||||
#define LLVM_LIB_TARGET_FOOT_MC_TARGET_DESC_H
|
||||
|
||||
#include "llvm/MC/MCAsmBackend.h"
|
||||
#include "llvm/MC/MCInstrInfo.h"
|
||||
#include "llvm/MC/TargetRegistry.h"
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
@ -11,7 +13,12 @@ class MCContext;
|
||||
class MCCodeEmitter;
|
||||
|
||||
MCCodeEmitter *createFootMCCodeEmitter(const MCInstrInfo &MII,
|
||||
MCContext &MCCtxt);
|
||||
MCContext &MCCtxt);
|
||||
|
||||
MCAsmBackend *createFootAsmBackend(const Target &T,
|
||||
const MCSubtargetInfo &STI,
|
||||
const MCRegisterInfo &,
|
||||
const MCTargetOptions &);
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user