Revert "[WebAssembly] Combine i128 to v16i8 for setcc & expand memcmp for 16 byte loads with simd128" (#153360)
Reverts llvm/llvm-project#149461 The first test w/ memcmp in `test/neon/test_neon_wasm_simd.cpp` in the Emscripten test suite has failed. This PR applies a revert so I can take a closer look at it Test case link: https://github.com/emscripten-core/emscripten/blob/main/test/neon/test_neon_wasm_simd.cpp Compile option: `em++ test_neon_wasm_simd.cpp -O2 -mfpu=neon -msimd128 -o something.js` Original comment report: https://github.com/llvm/llvm-project/pull/149461#issuecomment-3181652746
This commit is contained in:
Jasmine Tang
GitHub
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@ -3383,55 +3383,8 @@ static SDValue TryMatchTrue(SDNode *N, EVT VecVT, SelectionDAG &DAG) {
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return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
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}
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/// Try to convert a i128 comparison to a v16i8 comparison before type
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/// legalization splits it up into chunks
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static SDValue
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combineVectorSizedSetCCEquality(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
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const WebAssemblySubtarget *Subtarget) {
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SDLoc DL(N);
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SDValue X = N->getOperand(0);
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SDValue Y = N->getOperand(1);
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EVT VT = N->getValueType(0);
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EVT OpVT = X.getValueType();
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SelectionDAG &DAG = DCI.DAG;
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if (DCI.DAG.getMachineFunction().getFunction().hasFnAttribute(
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Attribute::NoImplicitFloat))
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return SDValue();
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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// We're looking for an oversized integer equality comparison with SIMD
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if (!OpVT.isScalarInteger() || !OpVT.isByteSized() || OpVT != MVT::i128 ||
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!Subtarget->hasSIMD128() || !isIntEqualitySetCC(CC))
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return SDValue();
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// Don't perform this combine if constructing the vector will be expensive.
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auto IsVectorBitCastCheap = [](SDValue X) {
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X = peekThroughBitcasts(X);
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return isa<ConstantSDNode>(X) || X.getOpcode() == ISD::LOAD;
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};
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if (!IsVectorBitCastCheap(X) || !IsVectorBitCastCheap(Y))
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return SDValue();
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SDValue VecX = DAG.getBitcast(MVT::v16i8, X);
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SDValue VecY = DAG.getBitcast(MVT::v16i8, Y);
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SDValue Cmp = DAG.getSetCC(DL, MVT::v16i8, VecX, VecY, CC);
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SDValue Intr =
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DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
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{DAG.getConstant(CC == ISD::SETEQ ? Intrinsic::wasm_alltrue
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: Intrinsic::wasm_anytrue,
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DL, MVT::i32),
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Cmp});
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return DAG.getSetCC(DL, VT, Intr, DAG.getConstant(0, DL, MVT::i32), CC);
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}
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static SDValue performSETCCCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const WebAssemblySubtarget *Subtarget) {
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TargetLowering::DAGCombinerInfo &DCI) {
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if (!DCI.isBeforeLegalize())
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return SDValue();
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@ -3439,9 +3392,6 @@ static SDValue performSETCCCombine(SDNode *N,
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if (!VT.isScalarInteger())
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return SDValue();
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if (SDValue V = combineVectorSizedSetCCEquality(N, DCI, Subtarget))
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return V;
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SDValue LHS = N->getOperand(0);
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if (LHS->getOpcode() != ISD::BITCAST)
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return SDValue();
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@ -3621,7 +3571,7 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::BITCAST:
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return performBitcastCombine(N, DCI);
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case ISD::SETCC:
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return performSETCCCombine(N, DCI, Subtarget);
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return performSETCCCombine(N, DCI);
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case ISD::VECTOR_SHUFFLE:
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return performVECTOR_SHUFFLECombine(N, DCI);
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case ISD::SIGN_EXTEND:
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@ -147,8 +147,7 @@ WebAssemblyTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
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Options.AllowOverlappingLoads = true;
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if (ST->hasSIMD128())
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Options.LoadSizes.push_back(16);
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// TODO: Teach WebAssembly backend about load v128.
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Options.LoadSizes.append({8, 4, 2, 1});
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Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
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@ -1,5 +1,5 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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@ -127,16 +127,24 @@ define i1 @memcmp_expand_8(ptr %a, ptr %b) {
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ret i1 %res
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}
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; TODO: Should be using a single load i64x2 or equivalent in bitsizes
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define i1 @memcmp_expand_16(ptr %a, ptr %b) {
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; CHECK-LABEL: memcmp_expand_16:
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; CHECK: .functype memcmp_expand_16 (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push1=, 0($0):p2align=0
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; CHECK-NEXT: v128.load $push0=, 0($1):p2align=0
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; CHECK-NEXT: i8x16.eq $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.all_true $push3=, $pop2
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; CHECK-NEXT: i32.eqz $push4=, $pop3
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; CHECK-NEXT: return $pop4
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; CHECK-NEXT: i64.load $push7=, 0($0):p2align=0
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; CHECK-NEXT: i64.load $push6=, 0($1):p2align=0
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; CHECK-NEXT: i64.xor $push8=, $pop7, $pop6
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; CHECK-NEXT: i32.const $push0=, 8
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; CHECK-NEXT: i32.add $push3=, $0, $pop0
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; CHECK-NEXT: i64.load $push4=, 0($pop3):p2align=0
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; CHECK-NEXT: i32.const $push11=, 8
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; CHECK-NEXT: i32.add $push1=, $1, $pop11
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; CHECK-NEXT: i64.load $push2=, 0($pop1):p2align=0
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; CHECK-NEXT: i64.xor $push5=, $pop4, $pop2
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; CHECK-NEXT: i64.or $push9=, $pop8, $pop5
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; CHECK-NEXT: i64.eqz $push10=, $pop9
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; CHECK-NEXT: return $pop10
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%cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
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%res = icmp eq i32 %cmp_16, 0
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ret i1 %res
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@ -1,89 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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declare i32 @memcmp(ptr, ptr, i32)
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define i1 @setcc_load(ptr %a, ptr %b) {
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; CHECK-LABEL: setcc_load:
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; CHECK: .functype setcc_load (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push1=, 0($0):p2align=0
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; CHECK-NEXT: v128.load $push0=, 0($1):p2align=0
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; CHECK-NEXT: i8x16.eq $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.all_true $push3=, $pop2
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; CHECK-NEXT: i32.eqz $push4=, $pop3
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; CHECK-NEXT: return $pop4
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%cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
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%res = icmp eq i32 %cmp_16, 0
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ret i1 %res
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}
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; INFO: Negative test: noimplicitfloat disables simd
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define i1 @setcc_load_should_not_vectorize(ptr %a, ptr %b) noimplicitfloat {
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; CHECK-LABEL: setcc_load_should_not_vectorize:
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; CHECK: .functype setcc_load_should_not_vectorize (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i64.load $push4=, 0($0):p2align=0
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; CHECK-NEXT: i64.load $push3=, 0($1):p2align=0
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; CHECK-NEXT: i64.xor $push5=, $pop4, $pop3
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; CHECK-NEXT: i64.load $push1=, 8($0):p2align=0
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; CHECK-NEXT: i64.load $push0=, 8($1):p2align=0
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; CHECK-NEXT: i64.xor $push2=, $pop1, $pop0
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; CHECK-NEXT: i64.or $push6=, $pop5, $pop2
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; CHECK-NEXT: i64.eqz $push7=, $pop6
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; CHECK-NEXT: return $pop7
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%cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
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%res = icmp eq i32 %cmp_16, 0
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ret i1 %res
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}
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define i1 @setcc_eq_const_i128(ptr %ptr) {
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; CHECK-LABEL: setcc_eq_const_i128:
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; CHECK: .functype setcc_eq_const_i128 (i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push0=, 0($0)
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; CHECK-NEXT: v128.const $push1=, 6, 0
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; CHECK-NEXT: i8x16.eq $push2=, $pop0, $pop1
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; CHECK-NEXT: i8x16.all_true $push3=, $pop2
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; CHECK-NEXT: i32.eqz $push4=, $pop3
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; CHECK-NEXT: return $pop4
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%l = load i128, ptr %ptr
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%res = icmp eq i128 %l, 6
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ret i1 %res
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}
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define i1 @setcc_ne_const_i128(ptr %ptr) {
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; CHECK-LABEL: setcc_ne_const_i128:
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; CHECK: .functype setcc_ne_const_i128 (i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push0=, 0($0)
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; CHECK-NEXT: v128.const $push1=, 16, 0
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; CHECK-NEXT: i8x16.ne $push2=, $pop0, $pop1
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; CHECK-NEXT: v128.any_true $push3=, $pop2
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; CHECK-NEXT: return $pop3
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%l = load i128, ptr %ptr
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%res = icmp ne i128 %l, 16
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ret i1 %res
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}
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; INFO: Negative test: only eq and ne works
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define i1 @setcc_slt_const_i128(ptr %ptr) {
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; CHECK-LABEL: setcc_slt_const_i128:
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; CHECK: .functype setcc_slt_const_i128 (i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i64.load $push2=, 0($0)
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; CHECK-NEXT: i64.const $push3=, 25
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; CHECK-NEXT: i64.lt_u $push4=, $pop2, $pop3
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; CHECK-NEXT: i64.load $push8=, 8($0)
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; CHECK-NEXT: local.tee $push7=, $1=, $pop8
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; CHECK-NEXT: i64.const $push0=, 0
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; CHECK-NEXT: i64.lt_s $push1=, $pop7, $pop0
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; CHECK-NEXT: i64.eqz $push5=, $1
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; CHECK-NEXT: i32.select $push6=, $pop4, $pop1, $pop5
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; CHECK-NEXT: return $pop6
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%l = load i128, ptr %ptr
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%res = icmp slt i128 %l, 25
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ret i1 %res
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}
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