AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_exp/exp_row (#181956)
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vangthao95
GitHub
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@ -1188,6 +1188,7 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
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switch (ID) {
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case SgprB32:
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case VgprB32:
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case SgprB32_M0:
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case UniInVgprB32:
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if (Ty == LLT::scalar(32) || Ty == LLT::fixed_vector(2, 16) ||
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isAnyPtr(Ty, 32))
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@ -1640,6 +1641,16 @@ bool RegBankLegalizeHelper::applyMappingSrc(
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}
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break;
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}
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case SgprB32_M0: {
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assert(Ty == getBTyFromID(MethodIDs[i], Ty));
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if (RB == SgprRB)
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break;
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assert(RB == VgprRB);
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Register NewSGPR32 = MRI.createVirtualRegister({SgprRB, Ty});
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buildReadFirstLane(B, NewSGPR32, Op.getReg(), RBI);
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Op.setReg(NewSGPR32);
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break;
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}
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// sgpr and vgpr scalars with extend
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case Sgpr32AExt: {
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// Note: this ext allows S1, and it is meant to be combined away.
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@ -1430,6 +1430,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
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.Uni(S64, {{Sgpr64}, {IntrId, Vcc, Sgpr64}})
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.Uni(S32, {{Sgpr32}, {IntrId, Vcc, Sgpr32}});
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addRulesForIOpcs({amdgcn_exp})
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.Any({{_, _, _, S32, S32, S32, S32},
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{{}, {IntrId, Imm, Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32}}});
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addRulesForIOpcs({amdgcn_exp_row})
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.Any({{_, _, _, S32, S32, S32, S32, _, S32},
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{{},
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{IntrId, Imm, Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Imm,
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SgprB32_M0}}});
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addRulesForIOpcs({amdgcn_mbcnt_lo, amdgcn_mbcnt_hi}, Standard)
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.Div(S32, {{}, {Vgpr32, None, Vgpr32, Vgpr32}});
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@ -226,6 +226,10 @@ enum RegBankLLTMappingApplyID {
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SgprP0Call_WF,
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SgprP4Call_WF,
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// Src only modifiers: for operands that must end up in M0. If divergent,
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// readfirstlane to SGPR. The result can then be copied to M0 in ISel.
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SgprB32_M0,
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// Src only modifiers: extends
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Sgpr32AExt,
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Sgpr32AExtBoolInReg,
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@ -1,18 +1,26 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
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--- |
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define void @exp_s() {
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call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0)
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define amdgpu_ps void @exp_s(float inreg %v0, float inreg %v1, float inreg %v2, float inreg %v3) {
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v0, float %v1, float %v2, float %v3, i1 false, i1 false)
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ret void
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}
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define void @exp_v() {
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call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0)
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define amdgpu_ps void @exp_v(float %v0, float %v1, float %v2, float %v3) {
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v0, float %v1, float %v2, float %v3, i1 false, i1 false)
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ret void
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}
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define amdgpu_ps void @exp_row_s(i32 inreg %row, float inreg %val) {
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call void @llvm.amdgcn.exp.row.f32(i32 12, i32 1, float %val, float %val, float %val, float %val, i1 true, i32 %row)
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ret void
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}
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define amdgpu_ps void @exp_row_v(float %val, i32 %row) {
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call void @llvm.amdgcn.exp.row.f32(i32 12, i32 1, float %val, float %val, float %val, float %val, i1 true, i32 %row)
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ret void
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}
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)
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declare void @llvm.amdgcn.exp.row.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i32)
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...
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---
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@ -33,12 +41,12 @@ body: |
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 0, [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), 0, 0
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), 0, 0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = COPY $sgpr3
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), 0, 0, %0, %1, %2, %3, 0, 0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, %0(s32), %1(s32), %2(s32), %3(s32), 0, 0
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...
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---
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name: exp_v
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@ -54,10 +62,49 @@ body: |
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 0, [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), 0, 0
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), 0, 0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(s32) = COPY $vgpr3
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), 0, 0, %0, %1, %2, %3, 0, 0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, %0(s32), %1(s32), %2(s32), %3(s32), 0, 0
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...
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---
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name: exp_row_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: exp_row_s
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), -1, [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, %1(s32), %1(s32), %1(s32), %1(s32), -1, %0(s32)
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...
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---
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name: exp_row_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: exp_row_v
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), -1, [[INTRINSIC_CONVERGENT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.row), 12, 1, %0(s32), %0(s32), %0(s32), %0(s32), -1, %1(s32)
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...
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@ -1,7 +1,11 @@
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX8,PREGFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX10,PREGFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX8,PREGFX11 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX8,PREGFX11 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX10,PREGFX11 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX10,PREGFX11 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX11 %s
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
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declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1
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@ -554,7 +558,7 @@ end:
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; GFX8-DAG: v_mov_b32_e32 [[X:v[0-9]+]], s1
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; GFX8-DAG: v_mov_b32_e32 [[Y:v[0-9]+]], s0
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; GFX8-DAG: v_add_f32_e{{32|64}} [[Z0:v[0-9]+]]
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; GFX8-DAG: v_sub_f32_e{{32|64}} [[Z1:v[0-9]+]]
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; GFX8-DAG: v_{{sub|subrev}}_f32_e{{32|64}} [[Z1:v[0-9]+]]
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; GFX8: {{exp|export}} param0, [[Y]], [[X]], [[Z0]], [[W0]]{{$}}
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; GFX8-NEXT: {{exp|export}} param1, [[Y]], [[X]], [[Z1]], [[W1]] done{{$}}
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@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX12
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX12
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX12
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declare void @llvm.amdgcn.exp.row.i32(i32, i32, i32, i32, i32, i32, i1, i32)
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declare void @llvm.amdgcn.exp.row.f32(i32, i32, float, float, float, float, i1, i32)
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