From d49d24ca978d8130c2e440fb42fea8f237c5203e Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Tue, 24 Mar 2026 18:55:38 -0700 Subject: [PATCH] [RISCV] Remove the experimental XRivosVisni extension (#188370) --- .../Driver/print-supported-extensions-riscv.c | 1 - llvm/docs/RISCVUsage.rst | 3 - llvm/docs/ReleaseNotes.md | 1 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 1 - llvm/lib/Target/RISCV/RISCVFeatures.td | 7 - llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 30 -- llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 87 +--- llvm/lib/Target/RISCV/RISCVInstrPredicates.td | 6 - .../Target/RISCV/RISCVTargetTransformInfo.cpp | 3 - .../Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp | 9 +- .../CostModel/RISCV/rvv-extractelement.ll | 293 ------------- .../CostModel/RISCV/rvv-insertelement.ll | 291 ------------- llvm/test/CodeGen/RISCV/features-info.ll | 1 - llvm/test/CodeGen/RISCV/pr148084.ll | 2 +- .../RISCV/rvv/fixed-vectors-extract.ll | 399 ------------------ .../CodeGen/RISCV/rvv/fixed-vectors-insert.ll | 331 --------------- llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll | 6 +- llvm/test/MC/RISCV/xrivosvisni-valid.s | 43 -- .../TargetParser/RISCVISAInfoTest.cpp | 1 - 19 files changed, 7 insertions(+), 1508 deletions(-) delete mode 100644 llvm/test/MC/RISCV/xrivosvisni-valid.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index f9d1bfa2c205..4ee470a76f21 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -255,7 +255,6 @@ // CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data) // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) -// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New) // CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) // CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 860c9b67f548..c1aff252eeac 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -537,9 +537,6 @@ The current vendor extensions supported are: ``Xmipslsp`` LLVM implements load/store pair instructions for the `p8700 processor `__ by MIPS. -``experimental-XRivosVisni`` - LLVM implements `version 0.1 of the Rivos Vector Integer Small New Instructions extension specification `__. - ``experimental-XRivosVizip`` LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification `__. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index e26d5acb601e..6be21fd2baf9 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -181,6 +181,7 @@ Changes to the RISC-V Backend * Adds experimental assembler support for the 'Zvzip` (RISC-V Vector Reordering Structured Data) extension. * `-mcpu=sifive-x160` and `-mcpu=sifive-x180` were added. +* Support for the experimental `XRivosVisni` vendor extension has been removed. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 52a993decd8c..30a5d65a901d 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -462,7 +462,6 @@ static constexpr FeatureBitset XCVFeatureGroup = { RISCV::FeatureVendorXCVbi}; static constexpr FeatureBitset XRivosFeatureGroup = { - RISCV::FeatureVendorXRivosVisni, RISCV::FeatureVendorXRivosVizip, }; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index afd3f3d3380c..0fe89072e5aa 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1670,13 +1670,6 @@ def FeatureVendorXqci // Rivos Extension(s) -def FeatureVendorXRivosVisni - : RISCVExperimentalExtension<0, 1, "Rivos Vector Integer Small New">; -def HasVendorXRivosVisni - : Predicate<"Subtarget->hasVendorXRivosVisni()">, - AssemblerPredicate<(all_of FeatureVendorXRivosVisni), - "'XRivosVisni' (Rivos Vector Integer Small New)">; - def FeatureVendorXRivosVizip : RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">; def HasVendorXRivosVizip diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index fbb4e32333e0..b1641ae34c3e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -10899,13 +10899,6 @@ getSmallestVTForIndex(MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG, return SmallerVT; } -static bool isValidVisniInsertExtractIndex(SDValue Idx) { - auto *IdxC = dyn_cast(Idx); - if (!IdxC || isNullConstant(Idx)) - return false; - return isUInt<5>(IdxC->getZExtValue()); -} - // Custom-legalize INSERT_VECTOR_ELT so that the value is inserted into the // first position of a vector, and that vector is slid up to the insert index. // By limiting the active vector length to index+1 and merging with the @@ -11063,21 +11056,6 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, return convertFromScalableVector(VecVT, Vec, DAG, Subtarget); } - // Use ri.vinsert.v.x if available. - if (Subtarget.hasVendorXRivosVisni() && VecVT.isInteger() && - isValidVisniInsertExtractIndex(Idx)) { - // Tail policy applies to elements past VLMAX (by assumption Idx < VLMAX) - SDValue PolicyOp = - DAG.getTargetConstant(RISCVVType::TAIL_AGNOSTIC, DL, XLenVT); - Vec = DAG.getNode(RISCVISD::RI_VINSERT_VL, DL, ContainerVT, Vec, Val, Idx, - VL, PolicyOp); - if (AlignedIdx) - Vec = DAG.getInsertSubvector(DL, OrigVec, Vec, *AlignedIdx); - if (!VecVT.isFixedLengthVector()) - return Vec; - return convertFromScalableVector(VecVT, Vec, DAG, Subtarget); - } - ValInVec = lowerScalarInsert(Val, VL, ContainerVT, DL, DAG, Subtarget); } else { // On RV32, i64-element vectors must be specially handled to place the @@ -11283,14 +11261,6 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, } } - // Use ri.vextract.x.v if available. - // TODO: Avoid index 0 and just use the vmv.x.s - if (Subtarget.hasVendorXRivosVisni() && EltVT.isInteger() && - isValidVisniInsertExtractIndex(Idx)) { - SDValue Elt = DAG.getNode(RISCVISD::RI_VEXTRACT, DL, XLenVT, Vec, Idx); - return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt); - } - // If after narrowing, the required slide is still greater than LMUL2, // fallback to generic expansion and go through the stack. This is done // for a subtle reason: extracting *all* elements out of a vector is diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td index 94eccf8dd450..c6b8fcdf605e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td @@ -113,89 +113,4 @@ defm : RIVPatBinaryVL_VV; defm : RIVPatBinaryVL_VV; defm : RIVPatBinaryVL_VV; defm : RIVPatBinaryVL_VV; -defm : RIVPatBinaryVL_VV; - -//===----------------------------------------------------------------------===// -// XRivosVisni -//===----------------------------------------------------------------------===// - -let Predicates = [HasVendorXRivosVisni], DecoderNamespace = "XRivos", - mayLoad = false, mayStore = false, hasSideEffects = false, - ElementsDependOn = EltDepsNone in { - -let isReMaterializable = 1, isAsCheapAsAMove = 1 in -def RI_VZERO : RVInstVUnary<0b000000, 0b00000, OPCFG, (outs VR:$vd), - (ins), "ri.vzero.v", "$vd"> { - let vm = 0; - let vs2 = 0; - - let Inst{6-0} = OPC_CUSTOM_2.Value; - - let VMConstraint = false; -} - -def RI_VINSERT : CustomRivosVXI<0b010000, OPMVX, (outs VR:$vd_wb), - (ins VR:$vd, GPR:$rs1, uimm5:$imm), - "ri.vinsert.v.x", "$vd, $rs1, $imm">; - -let ReadsPastVL = 1 in -def RI_VEXTRACT : CustomRivosXVI<0b010111, OPMVV, (outs GPR:$rd), - (ins VR:$vs2, uimm5:$imm), - "ri.vextract.x.v", "$rd, $vs2, $imm">; -} - -// RI_VEXTRACT matches the semantics of ri.vextract.x.v. The result is always -// XLenVT sign extended from the vector element size. VEXTRACT does *not* -// have a VL operand. -def ri_vextract : RVSDNode<"RI_VEXTRACT", - SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<1>, - SDTCisInt<2>, - SDTCisInt<1>]>>; - -// RI_VINSERT_VL matches the semantics of ri.vinsert.v.x. It carries a VL operand. -def ri_vinsert_vl : RVSDNode<"RI_VINSERT_VL", - SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, - SDTCisInt<0>, - SDTCisVT<2, XLenVT>, - SDTCisVT<3, XLenVT>, - SDTCisVT<4, XLenVT>]>>; - -let Predicates = [HasVendorXRivosVisni], mayLoad = 0, mayStore = 0, - hasSideEffects = 0, HasSEWOp = 1 in -foreach m = MxList in { - defvar mx = m.MX; - let VLMul = m.value in { - let BaseInstr = RI_VEXTRACT in - def PseudoRI_VEXTRACT_ # mx : - RISCVVPseudo<(outs GPR:$rd), - (ins m.vrclass:$rs2, uimm5:$idx, sew:$sew), - []>; - - let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1, - Constraints = "$rd = $rs1" in - def PseudoRI_VINSERT_ # mx : - RISCVVPseudo<(outs m.vrclass:$rd), - (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl, - sew:$sew, vec_policy:$policy), - []>; - } -} - - - -foreach vti = AllIntegerVectors in - let Predicates = GetVTypePredicates.Predicates in { - def : Pat<(XLenVT (ri_vextract (vti.Vector vti.RegClass:$vs2), uimm5:$imm)), - (!cast("PseudoRI_VEXTRACT_" # vti.LMul.MX) - $vs2, uimm5:$imm, vti.Log2SEW)>; - - def : Pat<(vti.Vector (ri_vinsert_vl (vti.Vector vti.RegClass:$merge), - vti.ScalarRegClass:$rs1, - uimm5:$imm, - VLOpFrag, - (XLenVT timm:$policy))), - (!cast("PseudoRI_VINSERT_" # vti.LMul.MX) - $merge, vti.ScalarRegClass:$rs1, uimm5:$imm, - GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>; - - } +defm : RIVPatBinaryVL_VV; \ No newline at end of file diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td index 4d6fc05b7316..bfe8dc9f92d6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td +++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td @@ -146,12 +146,6 @@ def isScalarExtractInstr !instances("^PseudoVFMV_F.*_S.*") ])>>>; -def isVExtractInstr - : TIIPredicate<"isVExtractInstr", - MCReturnStatement< - CheckOpcode< - !instances("^PseudoRI_VEXTRACT.*")>>>; - def isScalarInsertInstr : TIIPredicate<"isScalarInsertInstr", MCReturnStatement< diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index ab1483e2cc40..70b2a3d8f9b4 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -2586,9 +2586,6 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost( if (Index == 0) // We can extract/insert the first element without vslidedown/vslideup. SlideCost = 0; - else if (ST->hasVendorXRivosVisni() && isUInt<5>(Index) && - Val->getScalarType()->isIntegerTy()) - SlideCost = 0; // With ri.vinsert/ri.vextract there is no slide needed else if (Opcode == Instruction::InsertElement) SlideCost = 1; // With a constant index, we do not need to use addi. } diff --git a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp index ff2d8b09ed25..f13b8246662b 100644 --- a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp +++ b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp @@ -313,12 +313,6 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) { Res.MaskPolicy = false; } - if (RISCVInstrInfo::isVExtractInstr(MI)) { - assert(!RISCVII::hasVLOp(TSFlags)); - // TODO: LMUL can be any larger value (without cost) - Res.TailPolicy = false; - } - Res.AltFmt = RISCVII::getAltFmtType(MI.getDesc().TSFlags) != RISCVII::AltFmtType::DontCare; Res.TWiden = RISCVII::hasTWidenOp(MI.getDesc().TSFlags) || @@ -481,8 +475,7 @@ RISCVVSETVLIInfoAnalysis::computeInfoForInstr(const MachineInstr &MI) const { InstrInfo.setAVLRegDef(VNI, VLOp.getReg()); } } else { - assert(RISCVInstrInfo::isScalarExtractInstr(MI) || - RISCVInstrInfo::isVExtractInstr(MI)); + assert(RISCVInstrInfo::isScalarExtractInstr(MI)); // Pick a random value for state tracking purposes, will be ignored via // the demanded fields mechanism InstrInfo.setAVLImm(1); diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll index bca1624d279e..f3cbe25655a8 100644 --- a/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV32V ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV64V -; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh,+experimental-xrivosvisni < %s | FileCheck %s --check-prefixes=VISNI ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV32ZVE64X ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV64ZVE64X ; Check that we don't crash querying costs when vectors are not enabled. @@ -338,170 +337,6 @@ define void @extractelement_int(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv16i64_x = extractelement undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'extractelement_int' -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i1_0 = extractelement <2 x i1> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i1_0 = extractelement <4 x i1> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i1_0 = extractelement <8 x i1> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i1_0 = extractelement <16 x i1> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v32i1_0 = extractelement <32 x i1> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i1_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i1_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i1_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv16i1_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %nxv32i1_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = extractelement <2 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = extractelement <4 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = extractelement <8 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = extractelement <16 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = extractelement <32 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = extractelement <64 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_0 = extractelement <128 x i8> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv128i8_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_0 = extractelement <2 x i16> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16_0 = extractelement <4 x i16> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_0 = extractelement <8 x i16> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_0 = extractelement <16 x i16> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i16_0 = extractelement <32 x i16> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i16_0 = extractelement <64 x i16> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = extractelement <2 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = extractelement <4 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = extractelement <8 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = extractelement <16 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = extractelement <32 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = extractelement <2 x i64> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = extractelement <4 x i64> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = extractelement <8 x i64> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i64_0 = extractelement <16 x i64> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i1_1 = extractelement <2 x i1> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i1_1 = extractelement <4 x i1> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i1_1 = extractelement <8 x i1> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i1_1 = extractelement <16 x i1> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v32i1_1 = extractelement <32 x i1> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i1_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i1_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i1_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv16i1_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %nxv32i1_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_1 = extractelement <2 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8_1 = extractelement <4 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8_1 = extractelement <8 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8_1 = extractelement <16 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i8_1 = extractelement <32 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i8_1 = extractelement <64 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_1 = extractelement <128 x i8> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv128i8_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_1 = extractelement <2 x i16> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16_1 = extractelement <4 x i16> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_1 = extractelement <8 x i16> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_1 = extractelement <16 x i16> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i16_1 = extractelement <32 x i16> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i16_1 = extractelement <64 x i16> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = extractelement <2 x i32> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32_1 = extractelement <4 x i32> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i32_1 = extractelement <8 x i32> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i32_1 = extractelement <16 x i32> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_1 = extractelement <32 x i32> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = extractelement <2 x i64> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i64_1 = extractelement <4 x i64> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i64_1 = extractelement <8 x i64> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i64_1 = extractelement <16 x i64> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i1_x = extractelement <2 x i1> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i1_x = extractelement <4 x i1> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i1_x = extractelement <8 x i1> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i1_x = extractelement <16 x i1> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v32i1_x = extractelement <32 x i1> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %nxv2i1_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %nxv4i1_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %nxv8i1_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %nxv16i1_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %nxv32i1_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8_x = extractelement <2 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8_x = extractelement <4 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8_x = extractelement <8 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8_x = extractelement <16 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8_x = extractelement <32 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_x = extractelement <64 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_x = extractelement <128 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv64i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv128i8_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16_x = extractelement <2 x i16> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16_x = extractelement <4 x i16> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16_x = extractelement <8 x i16> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i16_x = extractelement <16 x i16> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i16_x = extractelement <32 x i16> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i16_x = extractelement <64 x i16> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2i16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4i16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8i16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16i16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32i16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv64i16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_x = extractelement <2 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_x = extractelement <4 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_x = extractelement <8 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_x = extractelement <16 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_x = extractelement <32 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2i32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4i32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8i32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16i32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv32i32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i64_x = extractelement <2 x i64> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64_x = extractelement <4 x i64> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i64_x = extractelement <8 x i64> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i64_x = extractelement <16 x i64> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2i64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4i64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8i64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv16i64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'extractelement_int' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i1_0 = extractelement <2 x i1> undef, i32 0 @@ -1064,22 +899,6 @@ define void @extractelement_int_lmul(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v64i32 = extractelement <64 x i32> undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'extractelement_int_lmul' -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_31 = extractelement <128 x i8> undef, i32 31 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_63 = extractelement <128 x i8> undef, i32 63 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_127 = extractelement <128 x i8> undef, i32 127 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v256i8_127 = extractelement <256 x i8> undef, i32 127 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v256i8_255 = extractelement <256 x i8> undef, i32 255 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_3 = extractelement <32 x i32> undef, i32 3 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_7 = extractelement <32 x i32> undef, i32 7 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_15 = extractelement <32 x i32> undef, i32 15 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_31 = extractelement <32 x i32> undef, i32 31 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = extractelement <64 x i32> undef, i32 63 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8 = extractelement <128 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v256i8 = extractelement <256 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32 = extractelement <32 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v64i32 = extractelement <64 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'extractelement_int_lmul' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_31 = extractelement <128 x i8> undef, i32 31 @@ -1324,98 +1143,6 @@ define void @extractelement_fp(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv16f64_x = extractelement undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'extractelement_fp' -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f16_0 = extractelement <2 x half> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f16_0 = extractelement <4 x half> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8f16_0 = extractelement <8 x half> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16f16_0 = extractelement <16 x half> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32f16_0 = extractelement <32 x half> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64f16_0 = extractelement <64 x half> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2f16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4f16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8f16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16f16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32f16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64f16_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32_0 = extractelement <2 x float> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f32_0 = extractelement <4 x float> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8f32_0 = extractelement <8 x float> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16f32_0 = extractelement <16 x float> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32f32_0 = extractelement <32 x float> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2f32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4f32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8f32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16f32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32f32_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64_0 = extractelement <2 x double> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f64_0 = extractelement <4 x double> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8f64_0 = extractelement <8 x double> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16f64_0 = extractelement <16 x double> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2f64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4f64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8f64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16f64_0 = extractelement undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16_1 = extractelement <2 x half> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f16_1 = extractelement <4 x half> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f16_1 = extractelement <8 x half> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f16_1 = extractelement <16 x half> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32f16_1 = extractelement <32 x half> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64f16_1 = extractelement <64 x half> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32f16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv64f16_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f32_1 = extractelement <2 x float> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32_1 = extractelement <4 x float> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f32_1 = extractelement <8 x float> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f32_1 = extractelement <16 x float> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32f32_1 = extractelement <32 x float> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32f32_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f64_1 = extractelement <2 x double> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f64_1 = extractelement <4 x double> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f64_1 = extractelement <8 x double> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f64_1 = extractelement <16 x double> undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f64_1 = extractelement undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16_x = extractelement <2 x half> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f16_x = extractelement <4 x half> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f16_x = extractelement <8 x half> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f16_x = extractelement <16 x half> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32f16_x = extractelement <32 x half> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64f16_x = extractelement <64 x half> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32f16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv64f16_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f32_x = extractelement <2 x float> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32_x = extractelement <4 x float> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f32_x = extractelement <8 x float> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f32_x = extractelement <16 x float> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32f32_x = extractelement <32 x float> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv32f32_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f64_x = extractelement <2 x double> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f64_x = extractelement <4 x double> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f64_x = extractelement <8 x double> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f64_x = extractelement <16 x double> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv16f64_x = extractelement undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'extractelement_fp' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16_0 = extractelement <2 x half> undef, i32 0 @@ -1740,17 +1467,6 @@ define void @extractelement_int_nonpoweroftwo(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v31i32_0 = extractelement <31 x i32> undef, i32 0 ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'extractelement_int_nonpoweroftwo' -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i8 = extractelement <3 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v7i8 = extractelement <7 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v15i8 = extractelement <15 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v31i8 = extractelement <31 x i8> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i32 = extractelement <3 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v7i32 = extractelement <7 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v15i32 = extractelement <15 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v31i32 = extractelement <31 x i32> undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v31i32_0 = extractelement <31 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'extractelement_int_nonpoweroftwo' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i8 = extractelement <3 x i8> undef, i32 %x @@ -1811,15 +1527,6 @@ define void @extractelement_vls(i32 %x) vscale_range(2,2) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_12 = extractelement <32 x i32> undef, i32 12 ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'extractelement_vls' -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = extractelement <32 x i32> undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_4 = extractelement <32 x i32> undef, i32 4 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_5 = extractelement <32 x i32> undef, i32 5 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_8 = extractelement <32 x i32> undef, i32 8 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_9 = extractelement <32 x i32> undef, i32 9 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_11 = extractelement <32 x i32> undef, i32 11 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_12 = extractelement <32 x i32> undef, i32 12 -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'extractelement_vls' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = extractelement <32 x i32> undef, i32 0 diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll index 39b7e01f6941..cdc1fd336b76 100644 --- a/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV32V ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV64V -; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh,+experimental-xrivosvisni < %s | FileCheck %s --check-prefixes=VISNI ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV32ZVE64X ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV64ZVE64X ; Check that we don't crash querying costs when vectors are not enabled. @@ -338,170 +337,6 @@ define void @insertelement_int(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv16i64_x = insertelement undef, i64 undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'insertelement_int' -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v2i1_0 = insertelement <2 x i1> undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i1_0 = insertelement <4 x i1> undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i1_0 = insertelement <8 x i1> undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v16i1_0 = insertelement <16 x i1> undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v32i1_0 = insertelement <32 x i1> undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv2i1_0 = insertelement undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv4i1_0 = insertelement undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv8i1_0 = insertelement undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %nxv16i1_0 = insertelement undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %nxv32i1_0 = insertelement undef, i1 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = insertelement <2 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = insertelement <4 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = insertelement <8 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = insertelement <16 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = insertelement <32 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = insertelement <64 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_0 = insertelement <128 x i8> undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv128i8_0 = insertelement undef, i8 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_0 = insertelement <2 x i16> undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16_0 = insertelement <4 x i16> undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_0 = insertelement <8 x i16> undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_0 = insertelement <16 x i16> undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i16_0 = insertelement <32 x i16> undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i16_0 = insertelement <64 x i16> undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i16_0 = insertelement undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i16_0 = insertelement undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i16_0 = insertelement undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i16_0 = insertelement undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i16_0 = insertelement undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i16_0 = insertelement undef, i16 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = insertelement <2 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = insertelement <4 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = insertelement <8 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = insertelement <16 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = insertelement <32 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i32_0 = insertelement undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i32_0 = insertelement undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i32_0 = insertelement undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i32_0 = insertelement undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i32_0 = insertelement undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = insertelement <2 x i64> undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = insertelement <4 x i64> undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = insertelement <8 x i64> undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i64_0 = insertelement <16 x i64> undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i64_0 = insertelement undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i64_0 = insertelement undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i64_0 = insertelement undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i64_0 = insertelement undef, i64 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v2i1_1 = insertelement <2 x i1> undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i1_1 = insertelement <4 x i1> undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i1_1 = insertelement <8 x i1> undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v16i1_1 = insertelement <16 x i1> undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v32i1_1 = insertelement <32 x i1> undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv2i1_1 = insertelement undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv4i1_1 = insertelement undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv8i1_1 = insertelement undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %nxv16i1_1 = insertelement undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %nxv32i1_1 = insertelement undef, i1 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_1 = insertelement <2 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8_1 = insertelement <4 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8_1 = insertelement <8 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8_1 = insertelement <16 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i8_1 = insertelement <32 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i8_1 = insertelement <64 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_1 = insertelement <128 x i8> undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv128i8_1 = insertelement undef, i8 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_1 = insertelement <2 x i16> undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16_1 = insertelement <4 x i16> undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_1 = insertelement <8 x i16> undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_1 = insertelement <16 x i16> undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i16_1 = insertelement <32 x i16> undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i16_1 = insertelement <64 x i16> undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i16_1 = insertelement undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i16_1 = insertelement undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i16_1 = insertelement undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i16_1 = insertelement undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i16_1 = insertelement undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i16_1 = insertelement undef, i16 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = insertelement <2 x i32> undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32_1 = insertelement <4 x i32> undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i32_1 = insertelement <8 x i32> undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i32_1 = insertelement <16 x i32> undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_1 = insertelement <32 x i32> undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i32_1 = insertelement undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i32_1 = insertelement undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i32_1 = insertelement undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i32_1 = insertelement undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i32_1 = insertelement undef, i32 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = insertelement <2 x i64> undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i64_1 = insertelement <4 x i64> undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i64_1 = insertelement <8 x i64> undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i64_1 = insertelement <16 x i64> undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i64_1 = insertelement undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i64_1 = insertelement undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i64_1 = insertelement undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i64_1 = insertelement undef, i64 undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v2i1_x = insertelement <2 x i1> undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v4i1_x = insertelement <4 x i1> undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v8i1_x = insertelement <8 x i1> undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v16i1_x = insertelement <16 x i1> undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v32i1_x = insertelement <32 x i1> undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %nxv2i1_x = insertelement undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %nxv4i1_x = insertelement undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %nxv8i1_x = insertelement undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %nxv16i1_x = insertelement undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %nxv32i1_x = insertelement undef, i1 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_x = insertelement <2 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i8_x = insertelement <4 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i8_x = insertelement <8 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i8_x = insertelement <16 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32i8_x = insertelement <32 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v64i8_x = insertelement <64 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v128i8_x = insertelement <128 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv16i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv32i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv64i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv128i8_x = insertelement undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i16_x = insertelement <2 x i16> undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i16_x = insertelement <4 x i16> undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i16_x = insertelement <8 x i16> undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i16_x = insertelement <16 x i16> undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32i16_x = insertelement <32 x i16> undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v64i16_x = insertelement <64 x i16> undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i16_x = insertelement undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i16_x = insertelement undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i16_x = insertelement undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv16i16_x = insertelement undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv32i16_x = insertelement undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv64i16_x = insertelement undef, i16 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_x = insertelement <2 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_x = insertelement <4 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_x = insertelement <8 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_x = insertelement <16 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32i32_x = insertelement <32 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i32_x = insertelement undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i32_x = insertelement undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i32_x = insertelement undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv16i32_x = insertelement undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv32i32_x = insertelement undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i64_x = insertelement <2 x i64> undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i64_x = insertelement <4 x i64> undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i64_x = insertelement <8 x i64> undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i64_x = insertelement <16 x i64> undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i64_x = insertelement undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i64_x = insertelement undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i64_x = insertelement undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv16i64_x = insertelement undef, i64 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'insertelement_int' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v2i1_0 = insertelement <2 x i1> undef, i1 undef, i32 0 @@ -1064,22 +899,6 @@ define void @insertelement_int_lmul(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'insertelement_int_lmul' -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_63 = insertelement <128 x i8> undef, i8 undef, i32 63 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_127 = insertelement <128 x i8> undef, i8 undef, i32 127 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v256i8_127 = insertelement <256 x i8> undef, i8 undef, i32 127 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v256i8_255 = insertelement <256 x i8> undef, i8 undef, i32 255 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_3 = insertelement <32 x i32> undef, i32 undef, i32 3 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_7 = insertelement <32 x i32> undef, i32 undef, i32 7 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_15 = insertelement <32 x i32> undef, i32 undef, i32 15 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_31 = insertelement <32 x i32> undef, i32 undef, i32 31 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = insertelement <64 x i32> undef, i32 undef, i32 63 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v128i8 = insertelement <128 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v256i8 = insertelement <256 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32i32 = insertelement <32 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'insertelement_int_lmul' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31 @@ -1324,98 +1143,6 @@ define void @insertelement_fp(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv16f64_x = insertelement undef, double undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'insertelement_fp' -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f16_0 = insertelement <2 x half> undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f16_0 = insertelement <4 x half> undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8f16_0 = insertelement <8 x half> undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16f16_0 = insertelement <16 x half> undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32f16_0 = insertelement <32 x half> undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64f16_0 = insertelement <64 x half> undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2f16_0 = insertelement undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4f16_0 = insertelement undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8f16_0 = insertelement undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16f16_0 = insertelement undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32f16_0 = insertelement undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64f16_0 = insertelement undef, half undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32_0 = insertelement <2 x float> undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f32_0 = insertelement <4 x float> undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8f32_0 = insertelement <8 x float> undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16f32_0 = insertelement <16 x float> undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32f32_0 = insertelement <32 x float> undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2f32_0 = insertelement undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4f32_0 = insertelement undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8f32_0 = insertelement undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16f32_0 = insertelement undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32f32_0 = insertelement undef, float undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64_0 = insertelement <2 x double> undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f64_0 = insertelement <4 x double> undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8f64_0 = insertelement <8 x double> undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16f64_0 = insertelement <16 x double> undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2f64_0 = insertelement undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4f64_0 = insertelement undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8f64_0 = insertelement undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16f64_0 = insertelement undef, double undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16_1 = insertelement <2 x half> undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f16_1 = insertelement <4 x half> undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f16_1 = insertelement <8 x half> undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f16_1 = insertelement <16 x half> undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32f16_1 = insertelement <32 x half> undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64f16_1 = insertelement <64 x half> undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f16_1 = insertelement undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f16_1 = insertelement undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f16_1 = insertelement undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f16_1 = insertelement undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32f16_1 = insertelement undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv64f16_1 = insertelement undef, half undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f32_1 = insertelement <2 x float> undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32_1 = insertelement <4 x float> undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f32_1 = insertelement <8 x float> undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f32_1 = insertelement <16 x float> undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32f32_1 = insertelement <32 x float> undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f32_1 = insertelement undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f32_1 = insertelement undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f32_1 = insertelement undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f32_1 = insertelement undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv32f32_1 = insertelement undef, float undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f64_1 = insertelement <2 x double> undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f64_1 = insertelement <4 x double> undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f64_1 = insertelement <8 x double> undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16f64_1 = insertelement <16 x double> undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv2f64_1 = insertelement undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv4f64_1 = insertelement undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv8f64_1 = insertelement undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %nxv16f64_1 = insertelement undef, double undef, i32 1 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2f16_x = insertelement <2 x half> undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4f16_x = insertelement <4 x half> undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8f16_x = insertelement <8 x half> undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16f16_x = insertelement <16 x half> undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32f16_x = insertelement <32 x half> undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v64f16_x = insertelement <64 x half> undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2f16_x = insertelement undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4f16_x = insertelement undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8f16_x = insertelement undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv16f16_x = insertelement undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv32f16_x = insertelement undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv64f16_x = insertelement undef, half undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2f32_x = insertelement <2 x float> undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4f32_x = insertelement <4 x float> undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8f32_x = insertelement <8 x float> undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16f32_x = insertelement <16 x float> undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32f32_x = insertelement <32 x float> undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2f32_x = insertelement undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4f32_x = insertelement undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8f32_x = insertelement undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv16f32_x = insertelement undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv32f32_x = insertelement undef, float undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2f64_x = insertelement <2 x double> undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4f64_x = insertelement <4 x double> undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8f64_x = insertelement <8 x double> undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16f64_x = insertelement <16 x double> undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2f64_x = insertelement undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4f64_x = insertelement undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8f64_x = insertelement undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %nxv16f64_x = insertelement undef, double undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'insertelement_fp' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16_0 = insertelement <2 x half> undef, half undef, i32 0 @@ -1736,15 +1463,6 @@ define void @insertelement_int_nonpoweroftwo(i32 %x) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v15i32 = insertelement <15 x i32> undef, i32 undef, i32 %x ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'insertelement_int_nonpoweroftwo' -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i8 = insertelement <3 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v7i8 = insertelement <7 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v15i8 = insertelement <15 x i8> undef, i8 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3i32_0 = insertelement <3 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = insertelement <3 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v7i32 = insertelement <7 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v15i32 = insertelement <15 x i32> undef, i32 undef, i32 %x -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'insertelement_int_nonpoweroftwo' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i8 = insertelement <3 x i8> undef, i8 undef, i32 %x @@ -1799,15 +1517,6 @@ define void @insertelement_vls(i32 %x) vscale_range(2,2) { ; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_12 = insertelement <32 x i32> undef, i32 undef, i32 12 ; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; VISNI-LABEL: 'insertelement_vls' -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = insertelement <32 x i32> undef, i32 undef, i32 0 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_4 = insertelement <32 x i32> undef, i32 undef, i32 4 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_5 = insertelement <32 x i32> undef, i32 undef, i32 5 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_8 = insertelement <32 x i32> undef, i32 undef, i32 8 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_9 = insertelement <32 x i32> undef, i32 undef, i32 9 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_11 = insertelement <32 x i32> undef, i32 undef, i32 11 -; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_12 = insertelement <32 x i32> undef, i32 undef, i32 12 -; VISNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; RV32ZVE64X-LABEL: 'insertelement_vls' ; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = insertelement <32 x i32> undef, i32 undef, i32 0 diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 51d63ac15f36..9d875299776e 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -26,7 +26,6 @@ ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. ; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). -; CHECK-NEXT: experimental-xrivosvisni - 'XRivosVisni' (Rivos Vector Integer Small New). ; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). ; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs). diff --git a/llvm/test/CodeGen/RISCV/pr148084.ll b/llvm/test/CodeGen/RISCV/pr148084.ll index b207374d4d41..0c1d29f06b4a 100644 --- a/llvm/test/CodeGen/RISCV/pr148084.ll +++ b/llvm/test/CodeGen/RISCV/pr148084.ll @@ -276,4 +276,4 @@ get_tx_mask.exit: ; preds = %._crit_edge.i, %bb ret void } -attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" } +attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll index be60f758ea9b..2515004952ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -7,8 +7,6 @@ ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32,RV32M ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64,RV64M -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d,+m,+experimental-xrivosvisni -verify-machineinstrs < %s | FileCheck %s --check-prefixes=VISNI - define i8 @extractelt_v16i8(<16 x i8> %a) nounwind { ; CHECK-LABEL: extractelt_v16i8: ; CHECK: # %bb.0: @@ -16,12 +14,6 @@ define i8 @extractelt_v16i8(<16 x i8> %a) nounwind { ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret -; -; VISNI-LABEL: extractelt_v16i8: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 7 -; VISNI-NEXT: ret %b = extractelement <16 x i8> %a, i32 7 ret i8 %b } @@ -33,12 +25,6 @@ define i16 @extractelt_v8i16(<8 x i16> %a) nounwind { ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret -; -; VISNI-LABEL: extractelt_v8i16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 7 -; VISNI-NEXT: ret %b = extractelement <8 x i16> %a, i32 7 ret i16 %b } @@ -50,12 +36,6 @@ define i32 @extractelt_v4i32(<4 x i32> %a) nounwind { ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret -; -; VISNI-LABEL: extractelt_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 2 -; VISNI-NEXT: ret %b = extractelement <4 x i32> %a, i32 2 ret i32 %b } @@ -75,12 +55,6 @@ define i64 @extractelt_v2i64(<2 x i64> %a) nounwind { ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret -; -; VISNI-LABEL: extractelt_v2i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = extractelement <2 x i64> %a, i32 0 ret i64 %b } @@ -93,13 +67,6 @@ define bfloat @extractelt_v8bf16(<8 x bfloat> %a) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: fmv.h.x fa0, a0 ; CHECK-NEXT: ret -; -; VISNI-LABEL: extractelt_v8bf16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 7 -; VISNI-NEXT: fmv.h.x fa0, a0 -; VISNI-NEXT: ret %b = extractelement <8 x bfloat> %a, i32 7 ret bfloat %b } @@ -119,13 +86,6 @@ define half @extractelt_v8f16(<8 x half> %a) nounwind { ; ZVFHMIN-NEXT: vmv.x.s a0, v8 ; ZVFHMIN-NEXT: fmv.h.x fa0, a0 ; ZVFHMIN-NEXT: ret -; -; VISNI-LABEL: extractelt_v8f16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 7 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = extractelement <8 x half> %a, i32 7 ret half %b } @@ -138,12 +98,6 @@ define float @extractelt_v4f32(<4 x float> %a) nounwind { ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v4f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 2 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = extractelement <4 x float> %a, i32 2 ret float %b } @@ -155,11 +109,6 @@ define double @extractelt_v2f64(<2 x double> %a) nounwind { ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v2f64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = extractelement <2 x double> %a, i32 0 ret double %b } @@ -172,11 +121,6 @@ define i8 @extractelt_v32i8(<32 x i8> %a) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v32i8: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 7 -; VISNI-NEXT: ret %b = extractelement <32 x i8> %a, i32 7 ret i8 %b } @@ -189,11 +133,6 @@ define i16 @extractelt_v16i16(<16 x i16> %a) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16i16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 7 -; VISNI-NEXT: ret %b = extractelement <16 x i16> %a, i32 7 ret i16 %b } @@ -206,11 +145,6 @@ define i32 @extractelt_v8i32(<8 x i32> %a) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v8i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m2, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 6 -; VISNI-NEXT: ret %b = extractelement <8 x i32> %a, i32 6 ret i32 %b } @@ -233,11 +167,6 @@ define i64 @extractelt_v4i64(<4 x i64> %a) nounwind { ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v4i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m2, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 3 -; VISNI-NEXT: ret %b = extractelement <4 x i64> %a, i32 3 ret i64 %b } @@ -251,12 +180,6 @@ define bfloat @extractelt_v16bf16(<16 x bfloat> %a) nounwind { ; CHECK-NEXT: fmv.h.x fa0, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16bf16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 7 -; VISNI-NEXT: fmv.h.x fa0, a0 -; VISNI-NEXT: ret %b = extractelement <16 x bfloat> %a, i32 7 ret bfloat %b } @@ -277,12 +200,6 @@ define half @extractelt_v16f16(<16 x half> %a) nounwind { ; ZVFHMIN-NEXT: fmv.h.x fa0, a0 ; ZVFHMIN-NEXT: ret ; -; VISNI-LABEL: extractelt_v16f16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 7 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = extractelement <16 x half> %a, i32 7 ret half %b } @@ -295,12 +212,6 @@ define float @extractelt_v8f32(<8 x float> %a) nounwind { ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v8f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 2 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = extractelement <8 x float> %a, i32 2 ret float %b } @@ -312,11 +223,6 @@ define double @extractelt_v4f64(<4 x double> %a) nounwind { ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v4f64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = extractelement <4 x double> %a, i32 0 ret double %b } @@ -342,11 +248,6 @@ define i64 @extractelt_v3i64(<3 x i64> %a) nounwind { ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v3i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m2, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 2 -; VISNI-NEXT: ret %b = extractelement <3 x i64> %a, i32 2 ret i64 %b } @@ -389,11 +290,6 @@ define i32 @extractelt_v32i32(<32 x i32> %a) nounwind { ; RV64-NEXT: addi sp, sp, 256 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v32i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m8, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 31 -; VISNI-NEXT: ret %b = extractelement <32 x i32> %a, i32 31 ret i32 %b } @@ -436,11 +332,6 @@ define i32 @extractelt_v64i32(<64 x i32> %a) nounwind { ; RV64-NEXT: addi sp, sp, 256 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v64i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m8, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v16, 31 -; VISNI-NEXT: ret %b = extractelement <64 x i32> %a, i32 63 ret i32 %b } @@ -453,12 +344,6 @@ define i8 @extractelt_v16i8_idx(<16 x i8> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16i8_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = extractelement <16 x i8> %a, i32 %idx ret i8 %b } @@ -471,12 +356,6 @@ define i16 @extractelt_v8i16_idx(<8 x i16> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v8i16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = extractelement <8 x i16> %a, i32 %idx ret i16 %b } @@ -490,13 +369,6 @@ define i32 @extractelt_v4i32_idx(<4 x i32> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v4i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = add <4 x i32> %a, %a %c = extractelement <4 x i32> %b, i32 %idx ret i32 %c @@ -523,13 +395,6 @@ define i64 @extractelt_v2i64_idx(<2 x i64> %a, i32 zeroext %idx) nounwind { ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v2i64_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = add <2 x i64> %a, %a %c = extractelement <2 x i64> %b, i32 %idx ret i64 %c @@ -549,18 +414,6 @@ define bfloat @extractelt_v8bf16_idx(<8 x bfloat> %a, i32 zeroext %idx) nounwind ; CHECK-NEXT: fmv.h.x fa0, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v8bf16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; VISNI-NEXT: vfwcvtbf16.f.f.v v10, v8 -; VISNI-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; VISNI-NEXT: vfadd.vv v8, v10, v10 -; VISNI-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; VISNI-NEXT: vfncvtbf16.f.f.w v10, v8 -; VISNI-NEXT: vslidedown.vx v8, v10, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: fmv.h.x fa0, a0 -; VISNI-NEXT: ret %b = fadd <8 x bfloat> %a, %a %c = extractelement <8 x bfloat> %b, i32 %idx ret bfloat %c @@ -588,13 +441,6 @@ define half @extractelt_v8f16_idx(<8 x half> %a, i32 zeroext %idx) nounwind { ; ZVFHMIN-NEXT: fmv.h.x fa0, a0 ; ZVFHMIN-NEXT: ret ; -; VISNI-LABEL: extractelt_v8f16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; VISNI-NEXT: vfadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = fadd <8 x half> %a, %a %c = extractelement <8 x half> %b, i32 %idx ret half %c @@ -609,13 +455,6 @@ define float @extractelt_v4f32_idx(<4 x float> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v4f32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; VISNI-NEXT: vfadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = fadd <4 x float> %a, %a %c = extractelement <4 x float> %b, i32 %idx ret float %c @@ -630,13 +469,6 @@ define double @extractelt_v2f64_idx(<2 x double> %a, i32 zeroext %idx) nounwind ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v2f64_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; VISNI-NEXT: vfadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = fadd <2 x double> %a, %a %c = extractelement <2 x double> %b, i32 %idx ret double %c @@ -650,12 +482,6 @@ define i8 @extractelt_v32i8_idx(<32 x i8> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v32i8_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e8, m2, ta, ma -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = extractelement <32 x i8> %a, i32 %idx ret i8 %b } @@ -668,12 +494,6 @@ define i16 @extractelt_v16i16_idx(<16 x i16> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16i16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m2, ta, ma -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = extractelement <16 x i16> %a, i32 %idx ret i16 %b } @@ -687,13 +507,6 @@ define i32 @extractelt_v8i32_idx(<8 x i32> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v8i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = add <8 x i32> %a, %a %c = extractelement <8 x i32> %b, i32 %idx ret i32 %c @@ -720,13 +533,6 @@ define i64 @extractelt_v4i64_idx(<4 x i64> %a, i32 zeroext %idx) nounwind { ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v4i64_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = add <4 x i64> %a, %a %c = extractelement <4 x i64> %b, i32 %idx ret i64 %c @@ -746,18 +552,6 @@ define bfloat @extractelt_v16bf16_idx(<16 x bfloat> %a, i32 zeroext %idx) nounwi ; CHECK-NEXT: fmv.h.x fa0, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16bf16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; VISNI-NEXT: vfwcvtbf16.f.f.v v12, v8 -; VISNI-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; VISNI-NEXT: vfadd.vv v8, v12, v12 -; VISNI-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; VISNI-NEXT: vfncvtbf16.f.f.w v12, v8 -; VISNI-NEXT: vslidedown.vx v8, v12, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: fmv.h.x fa0, a0 -; VISNI-NEXT: ret %b = fadd <16 x bfloat> %a, %a %c = extractelement <16 x bfloat> %b, i32 %idx ret bfloat %c @@ -785,13 +579,6 @@ define half @extractelt_v16f16_idx(<16 x half> %a, i32 zeroext %idx) nounwind { ; ZVFHMIN-NEXT: fmv.h.x fa0, a0 ; ZVFHMIN-NEXT: ret ; -; VISNI-LABEL: extractelt_v16f16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; VISNI-NEXT: vfadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = fadd <16 x half> %a, %a %c = extractelement <16 x half> %b, i32 %idx ret half %c @@ -806,13 +593,6 @@ define float @extractelt_v8f32_idx(<8 x float> %a, i32 zeroext %idx) nounwind { ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v8f32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; VISNI-NEXT: vfadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = fadd <8 x float> %a, %a %c = extractelement <8 x float> %b, i32 %idx ret float %c @@ -827,13 +607,6 @@ define double @extractelt_v4f64_idx(<4 x double> %a, i32 zeroext %idx) nounwind ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v4f64_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; VISNI-NEXT: vfadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vfmv.f.s fa0, v8 -; VISNI-NEXT: ret %b = fadd <4 x double> %a, %a %c = extractelement <4 x double> %b, i32 %idx ret double %c @@ -865,13 +638,6 @@ define i64 @extractelt_v3i64_idx(<3 x i64> %a, i32 zeroext %idx) nounwind { ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v3i64_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vslidedown.vx v8, v8, a0 -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: ret %b = add <3 x i64> %a, %a %c = extractelement <3 x i64> %b, i32 %idx ret i64 %c @@ -978,28 +744,6 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind { ; RV64M-NEXT: addi sp, sp, 256 ; RV64M-NEXT: ret ; -; VISNI-LABEL: extractelt_v32i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: addi sp, sp, -256 -; VISNI-NEXT: sd ra, 248(sp) # 8-byte Folded Spill -; VISNI-NEXT: sd s0, 240(sp) # 8-byte Folded Spill -; VISNI-NEXT: addi s0, sp, 256 -; VISNI-NEXT: andi sp, sp, -128 -; VISNI-NEXT: andi a1, a1, 31 -; VISNI-NEXT: li a2, 32 -; VISNI-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; VISNI-NEXT: vle32.v v8, (a0) -; VISNI-NEXT: slli a1, a1, 2 -; VISNI-NEXT: mv a0, sp -; VISNI-NEXT: or a1, a0, a1 -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vse32.v v8, (a0) -; VISNI-NEXT: lw a0, 0(a1) -; VISNI-NEXT: addi sp, s0, -256 -; VISNI-NEXT: ld ra, 248(sp) # 8-byte Folded Reload -; VISNI-NEXT: ld s0, 240(sp) # 8-byte Folded Reload -; VISNI-NEXT: addi sp, sp, 256 -; VISNI-NEXT: ret %a = load <32 x i32>, ptr %x %b = add <32 x i32> %a, %a %c = extractelement <32 x i32> %b, i32 %idx @@ -1057,30 +801,6 @@ define i32 @extractelt_v64i32_idx(<64 x i32> %a, i32 zeroext %idx) nounwind { ; RV64-NEXT: addi sp, sp, 384 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_v64i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: addi sp, sp, -384 -; VISNI-NEXT: sd ra, 376(sp) # 8-byte Folded Spill -; VISNI-NEXT: sd s0, 368(sp) # 8-byte Folded Spill -; VISNI-NEXT: addi s0, sp, 384 -; VISNI-NEXT: andi sp, sp, -128 -; VISNI-NEXT: andi a0, a0, 63 -; VISNI-NEXT: mv a1, sp -; VISNI-NEXT: li a2, 32 -; VISNI-NEXT: addi a3, sp, 128 -; VISNI-NEXT: slli a0, a0, 2 -; VISNI-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v8 -; VISNI-NEXT: vadd.vv v16, v16, v16 -; VISNI-NEXT: add a0, a1, a0 -; VISNI-NEXT: vse32.v v16, (a3) -; VISNI-NEXT: vse32.v v8, (a1) -; VISNI-NEXT: lw a0, 0(a0) -; VISNI-NEXT: addi sp, s0, -384 -; VISNI-NEXT: ld ra, 376(sp) # 8-byte Folded Reload -; VISNI-NEXT: ld s0, 368(sp) # 8-byte Folded Reload -; VISNI-NEXT: addi sp, sp, 384 -; VISNI-NEXT: ret %b = add <64 x i32> %a, %a %c = extractelement <64 x i32> %b, i32 %idx ret i32 %c @@ -1094,12 +814,6 @@ define void @store_extractelt_v16i8(<16 x i8> %a, ptr %p) nounwind { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: store_extractelt_v16i8: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a1, v8, 7 -; VISNI-NEXT: sb a1, 0(a0) -; VISNI-NEXT: ret %b = extractelement <16 x i8> %a, i32 7 store i8 %b, ptr %p ret void @@ -1113,12 +827,6 @@ define void @store_extractelt_v8i16(<8 x i16> %a, ptr %p) nounwind { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: store_extractelt_v8i16: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a1, v8, 7 -; VISNI-NEXT: sh a1, 0(a0) -; VISNI-NEXT: ret %b = extractelement <8 x i16> %a, i32 7 store i16 %b, ptr %p ret void @@ -1132,12 +840,6 @@ define void @store_extractelt_v4i32(<4 x i32> %a, ptr %p) nounwind { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: store_extractelt_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a1, v8, 2 -; VISNI-NEXT: sw a1, 0(a0) -; VISNI-NEXT: ret %b = extractelement <4 x i32> %a, i32 2 store i32 %b, ptr %p ret void @@ -1164,12 +866,6 @@ define void @store_extractelt_v2i64(<2 x i64> %a, ptr %p) nounwind { ; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: store_extractelt_v2i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a1, v8, 1 -; VISNI-NEXT: sd a1, 0(a0) -; VISNI-NEXT: ret %b = extractelement <2 x i64> %a, i64 1 store i64 %b, ptr %p ret void @@ -1183,12 +879,6 @@ define void @store_extractelt_v2f64(<2 x double> %a, ptr %p) nounwind { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: store_extractelt_v2f64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 1 -; VISNI-NEXT: vse64.v v8, (a0) -; VISNI-NEXT: ret %b = extractelement <2 x double> %a, i64 1 store double %b, ptr %p ret void @@ -1211,12 +901,6 @@ define i32 @extractelt_add_v4i32(<4 x i32> %x) { ; RV64-NEXT: addiw a0, a0, 13 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_add_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 2 -; VISNI-NEXT: addiw a0, a0, 13 -; VISNI-NEXT: ret %bo = add <4 x i32> %x, %ext = extractelement <4 x i32> %bo, i32 2 ret i32 %ext @@ -1241,13 +925,6 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) { ; RV64-NEXT: subw a0, a1, a0 ; RV64-NEXT: ret ; -; VISNI-LABEL: extractelt_sub_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 2 -; VISNI-NEXT: li a1, 13 -; VISNI-NEXT: subw a0, a1, a0 -; VISNI-NEXT: ret %bo = sub <4 x i32> , %x %ext = extractelement <4 x i32> %bo, i32 2 ret i32 %ext @@ -1290,13 +967,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) { ; RV64M-NEXT: mulw a0, a0, a1 ; RV64M-NEXT: ret ; -; VISNI-LABEL: extractelt_mul_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 2 -; VISNI-NEXT: li a1, 13 -; VISNI-NEXT: mulw a0, a0, a1 -; VISNI-NEXT: ret %bo = mul <4 x i32> %x, %ext = extractelement <4 x i32> %bo, i32 2 ret i32 %ext @@ -1375,18 +1045,6 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) { ; RV64M-NEXT: add a0, a0, a1 ; RV64M-NEXT: ret ; -; VISNI-LABEL: extractelt_sdiv_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v8, 2 -; VISNI-NEXT: lui a1, 322639 -; VISNI-NEXT: sext.w a0, a0 -; VISNI-NEXT: addi a1, a1, -945 -; VISNI-NEXT: mul a0, a0, a1 -; VISNI-NEXT: srli a1, a0, 63 -; VISNI-NEXT: srai a0, a0, 34 -; VISNI-NEXT: add a0, a0, a1 -; VISNI-NEXT: ret %bo = sdiv <4 x i32> %x, %ext = extractelement <4 x i32> %bo, i32 2 ret i32 %ext @@ -1442,17 +1100,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) { ; RV64M-NEXT: srli a0, a0, 34 ; RV64M-NEXT: ret ; -; VISNI-LABEL: extractelt_udiv_v4i32: -; VISNI: # %bb.0: -; VISNI-NEXT: lui a0, 322639 -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a1, v8, 2 -; VISNI-NEXT: addi a0, a0, -945 -; VISNI-NEXT: slli a0, a0, 32 -; VISNI-NEXT: slli a1, a1, 32 -; VISNI-NEXT: mulhu a0, a1, a0 -; VISNI-NEXT: srli a0, a0, 34 -; VISNI-NEXT: ret %bo = udiv <4 x i32> %x, %ext = extractelement <4 x i32> %bo, i32 2 ret i32 %ext @@ -1469,15 +1116,6 @@ define float @extractelt_fadd_v4f32(<4 x float> %x) { ; CHECK-NEXT: fadd.s fa0, fa5, fa4 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_fadd_v4f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 2 -; VISNI-NEXT: lui a0, 267520 -; VISNI-NEXT: vfmv.f.s fa5, v8 -; VISNI-NEXT: fmv.w.x fa4, a0 -; VISNI-NEXT: fadd.s fa0, fa5, fa4 -; VISNI-NEXT: ret %bo = fadd <4 x float> %x, %ext = extractelement <4 x float> %bo, i32 2 ret float %ext @@ -1494,15 +1132,6 @@ define float @extractelt_fsub_v4f32(<4 x float> %x) { ; CHECK-NEXT: fsub.s fa0, fa4, fa5 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_fsub_v4f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 2 -; VISNI-NEXT: lui a0, 267520 -; VISNI-NEXT: vfmv.f.s fa5, v8 -; VISNI-NEXT: fmv.w.x fa4, a0 -; VISNI-NEXT: fsub.s fa0, fa4, fa5 -; VISNI-NEXT: ret %bo = fsub <4 x float> , %x %ext = extractelement <4 x float> %bo, i32 2 ret float %ext @@ -1519,15 +1148,6 @@ define float @extractelt_fmul_v4f32(<4 x float> %x) { ; CHECK-NEXT: fmul.s fa0, fa5, fa4 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_fmul_v4f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 2 -; VISNI-NEXT: lui a0, 267520 -; VISNI-NEXT: vfmv.f.s fa5, v8 -; VISNI-NEXT: fmv.w.x fa4, a0 -; VISNI-NEXT: fmul.s fa0, fa5, fa4 -; VISNI-NEXT: ret %bo = fmul <4 x float> %x, %ext = extractelement <4 x float> %bo, i32 2 ret float %ext @@ -1544,15 +1164,6 @@ define float @extractelt_fdiv_v4f32(<4 x float> %x) { ; CHECK-NEXT: fdiv.s fa0, fa5, fa4 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_fdiv_v4f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: vslidedown.vi v8, v8, 2 -; VISNI-NEXT: lui a0, 267520 -; VISNI-NEXT: vfmv.f.s fa5, v8 -; VISNI-NEXT: fmv.w.x fa4, a0 -; VISNI-NEXT: fdiv.s fa0, fa5, fa4 -; VISNI-NEXT: ret %bo = fdiv <4 x float> %x, %ext = extractelement <4 x float> %bo, i32 2 ret float %ext @@ -1566,11 +1177,6 @@ define i32 @extractelt_v16i32_idx7_exact_vlen(<16 x i32> %a) nounwind vscale_ran ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16i32_idx7_exact_vlen: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v9, 3 -; VISNI-NEXT: ret %b = extractelement <16 x i32> %a, i32 7 ret i32 %b } @@ -1583,11 +1189,6 @@ define i32 @extractelt_v16i32_idx15_exact_vlen(<16 x i32> %a) nounwind vscale_ra ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret ; -; VISNI-LABEL: extractelt_v16i32_idx15_exact_vlen: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a0, v11, 3 -; VISNI-NEXT: ret %b = extractelement <16 x i32> %a, i32 15 ret i32 %b } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll index b95a12ff6257..af0a3b296dfc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -4,7 +4,6 @@ ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVFHMIN,ZVFHMINRV32 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVFHMIN,ZVFHMINRV64 ; -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d,+experimental-xrivosvisni -verify-machineinstrs < %s | FileCheck %s --check-prefixes=VISNI define <4 x i32> @insertelt_v4i32_0(<4 x i32> %a, i32 %y) { ; CHECK-LABEL: insertelt_v4i32_0: @@ -13,11 +12,6 @@ define <4 x i32> @insertelt_v4i32_0(<4 x i32> %a, i32 %y) { ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v4i32_0: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e32, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %b = insertelement <4 x i32> %a, i32 %y, i32 0 ret <4 x i32> %b } @@ -30,11 +24,6 @@ define <4 x i32> @insertelt_v4i32_3(<4 x i32> %a, i32 %y) { ; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v4i32_3: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 3 -; VISNI-NEXT: ret %b = insertelement <4 x i32> %a, i32 %y, i32 3 ret <4 x i32> %b } @@ -49,14 +38,6 @@ define <4 x i32> @insertelt_v4i32_idx(<4 x i32> %a, i32 %y, i32 zeroext %idx) { ; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v4i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: addi a2, a1, 1 -; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; VISNI-NEXT: vmv.s.x v9, a0 -; VISNI-NEXT: vsetvli zero, a2, e32, m1, tu, ma -; VISNI-NEXT: vslideup.vx v8, v9, a1 -; VISNI-NEXT: ret %b = insertelement <4 x i32> %a, i32 %y, i32 %idx ret <4 x i32> %b } @@ -69,12 +50,6 @@ define <32 x i32> @insertelt_v32i32_0(<32 x i32> %a, i32 %y) { ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v32i32_0: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, 32 -; VISNI-NEXT: vsetvli zero, a1, e32, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %b = insertelement <32 x i32> %a, i32 %y, i32 0 ret <32 x i32> %b } @@ -87,12 +62,6 @@ define <32 x i32> @insertelt_v32i32_4(<32 x i32> %a, i32 %y) { ; CHECK-NEXT: vslideup.vi v8, v16, 4 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v32i32_4: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, 32 -; VISNI-NEXT: vsetvli zero, a1, e32, m2, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 4 -; VISNI-NEXT: ret %b = insertelement <32 x i32> %a, i32 %y, i32 4 ret <32 x i32> %b } @@ -106,12 +75,6 @@ define <32 x i32> @insertelt_v32i32_31(<32 x i32> %a, i32 %y) { ; CHECK-NEXT: vslideup.vi v8, v16, 31 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v32i32_31: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, 32 -; VISNI-NEXT: vsetvli zero, a1, e32, m8, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 31 -; VISNI-NEXT: ret %b = insertelement <32 x i32> %a, i32 %y, i32 31 ret <32 x i32> %b } @@ -127,15 +90,6 @@ define <32 x i32> @insertelt_v32i32_idx(<32 x i32> %a, i32 %y, i32 zeroext %idx) ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v32i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: li a2, 32 -; VISNI-NEXT: vsetvli zero, a2, e32, m1, ta, ma -; VISNI-NEXT: vmv.s.x v16, a0 -; VISNI-NEXT: addi a0, a1, 1 -; VISNI-NEXT: vsetvli zero, a0, e32, m8, tu, ma -; VISNI-NEXT: vslideup.vx v8, v16, a1 -; VISNI-NEXT: ret %b = insertelement <32 x i32> %a, i32 %y, i32 %idx ret <32 x i32> %b } @@ -148,12 +102,6 @@ define <64 x i32> @insertelt_v64i32_0(<64 x i32> %a, i32 %y) { ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v64i32_0: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, 32 -; VISNI-NEXT: vsetvli zero, a1, e32, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %b = insertelement <64 x i32> %a, i32 %y, i32 0 ret <64 x i32> %b } @@ -167,12 +115,6 @@ define <64 x i32> @insertelt_v64i32_63(<64 x i32> %a, i32 %y) { ; CHECK-NEXT: vslideup.vi v16, v24, 31 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v64i32_63: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, 32 -; VISNI-NEXT: vsetvli zero, a1, e32, m8, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v16, a0, 31 -; VISNI-NEXT: ret %b = insertelement <64 x i32> %a, i32 %y, i32 63 ret <64 x i32> %b } @@ -244,38 +186,6 @@ define <64 x i32> @insertelt_v64i32_idx(<64 x i32> %a, i32 %y, i32 zeroext %idx) ; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v64i32_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: addi sp, sp, -384 -; VISNI-NEXT: .cfi_def_cfa_offset 384 -; VISNI-NEXT: sd ra, 376(sp) # 8-byte Folded Spill -; VISNI-NEXT: sd s0, 368(sp) # 8-byte Folded Spill -; VISNI-NEXT: .cfi_offset ra, -8 -; VISNI-NEXT: .cfi_offset s0, -16 -; VISNI-NEXT: addi s0, sp, 384 -; VISNI-NEXT: .cfi_def_cfa s0, 0 -; VISNI-NEXT: andi sp, sp, -128 -; VISNI-NEXT: andi a1, a1, 63 -; VISNI-NEXT: mv a2, sp -; VISNI-NEXT: addi a3, sp, 128 -; VISNI-NEXT: li a4, 32 -; VISNI-NEXT: slli a1, a1, 2 -; VISNI-NEXT: vsetvli zero, a4, e32, m8, ta, ma -; VISNI-NEXT: vse32.v v16, (a3) -; VISNI-NEXT: vse32.v v8, (a2) -; VISNI-NEXT: add a1, a2, a1 -; VISNI-NEXT: sw a0, 0(a1) -; VISNI-NEXT: vle32.v v8, (a2) -; VISNI-NEXT: vle32.v v16, (a3) -; VISNI-NEXT: addi sp, s0, -384 -; VISNI-NEXT: .cfi_def_cfa sp, 384 -; VISNI-NEXT: ld ra, 376(sp) # 8-byte Folded Reload -; VISNI-NEXT: ld s0, 368(sp) # 8-byte Folded Reload -; VISNI-NEXT: .cfi_restore ra -; VISNI-NEXT: .cfi_restore s0 -; VISNI-NEXT: addi sp, sp, 384 -; VISNI-NEXT: .cfi_def_cfa_offset 0 -; VISNI-NEXT: ret %b = insertelement <64 x i32> %a, i32 %y, i32 %idx ret <64 x i32> %b } @@ -300,11 +210,6 @@ define <4 x i64> @insertelt_v4i64(<4 x i64> %a, i64 %y) { ; RV64-NEXT: vslideup.vi v8, v10, 3 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v4i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 3 -; VISNI-NEXT: ret %b = insertelement <4 x i64> %a, i64 %y, i32 3 ret <4 x i64> %b } @@ -321,10 +226,6 @@ define void @insertelt_v4i64_store(ptr %x, i64 %y) { ; RV64-NEXT: sd a1, 24(a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v4i64_store: -; VISNI: # %bb.0: -; VISNI-NEXT: sd a1, 24(a0) -; VISNI-NEXT: ret %a = load <4 x i64>, ptr %x %b = insertelement <4 x i64> %a, i64 %y, i32 3 store <4 x i64> %b, ptr %x @@ -369,17 +270,6 @@ define <3 x i64> @insertelt_v3i64(<3 x i64> %a, i64 %y) { ; RV64-NEXT: vslidedown.vi v8, v8, 1 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v3i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: ri.vextract.x.v a1, v8, 1 -; VISNI-NEXT: vmv.x.s a2, v8 -; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; VISNI-NEXT: vmv.v.x v8, a2 -; VISNI-NEXT: vslide1down.vx v8, v8, a1 -; VISNI-NEXT: vslide1down.vx v8, v8, a0 -; VISNI-NEXT: vslidedown.vi v8, v8, 1 -; VISNI-NEXT: ret %b = insertelement <3 x i64> %a, i64 %y, i32 2 ret <3 x i64> %b } @@ -396,10 +286,6 @@ define void @insertelt_v3i64_store(ptr %x, i64 %y) { ; RV64-NEXT: sd a1, 16(a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v3i64_store: -; VISNI: # %bb.0: -; VISNI-NEXT: sd a1, 16(a0) -; VISNI-NEXT: ret %a = load <3 x i64>, ptr %x, align 8 %b = insertelement <3 x i64> %a, i64 %y, i32 2 store <3 x i64> %b, ptr %x @@ -414,11 +300,6 @@ define <16 x i8> @insertelt_v16i8(<16 x i8> %a, i8 %y) { ; CHECK-NEXT: vslideup.vi v8, v9, 14 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v16i8: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 14 -; VISNI-NEXT: ret %b = insertelement <16 x i8> %a, i8 %y, i32 14 ret <16 x i8> %b } @@ -429,10 +310,6 @@ define void @insertelt_v16i8_store(ptr %x, i8 %y) { ; CHECK-NEXT: sb a1, 14(a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v16i8_store: -; VISNI: # %bb.0: -; VISNI-NEXT: sb a1, 14(a0) -; VISNI-NEXT: ret %a = load <16 x i8>, ptr %x %b = insertelement <16 x i8> %a, i8 %y, i32 14 store <16 x i8> %b, ptr %x @@ -462,17 +339,6 @@ define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) { ; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v32i16: -; VISNI: # %bb.0: -; VISNI-NEXT: li a2, 32 -; VISNI-NEXT: slli a1, a1, 32 -; VISNI-NEXT: vsetvli zero, a2, e16, m1, ta, ma -; VISNI-NEXT: vmv.s.x v12, a0 -; VISNI-NEXT: srli a1, a1, 32 -; VISNI-NEXT: addi a0, a1, 1 -; VISNI-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; VISNI-NEXT: vslideup.vx v8, v12, a1 -; VISNI-NEXT: ret %b = insertelement <32 x i16> %a, i16 %y, i32 %idx ret <32 x i16> %b } @@ -486,13 +352,6 @@ define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) { ; CHECK-NEXT: sh a1, 0(a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v32i16_store: -; VISNI: # %bb.0: -; VISNI-NEXT: andi a2, a2, 31 -; VISNI-NEXT: slli a2, a2, 1 -; VISNI-NEXT: add a0, a0, a2 -; VISNI-NEXT: sh a1, 0(a0) -; VISNI-NEXT: ret %a = load <32 x i16>, ptr %x %b = insertelement <32 x i16> %a, i16 %y, i32 %idx store <32 x i16> %b, ptr %x @@ -520,16 +379,6 @@ define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) { ; RV64-NEXT: vslideup.vx v8, v10, a0 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v8f32: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e32, m1, ta, ma -; VISNI-NEXT: vfmv.s.f v10, fa0 -; VISNI-NEXT: slli a0, a0, 32 -; VISNI-NEXT: srli a0, a0, 32 -; VISNI-NEXT: addi a1, a0, 1 -; VISNI-NEXT: vsetvli zero, a1, e32, m2, tu, ma -; VISNI-NEXT: vslideup.vx v8, v10, a0 -; VISNI-NEXT: ret %b = insertelement <8 x float> %a, float %y, i32 %idx ret <8 x float> %b } @@ -543,13 +392,6 @@ define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) { ; CHECK-NEXT: fsw fa0, 0(a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v8f32_store: -; VISNI: # %bb.0: -; VISNI-NEXT: andi a1, a1, 7 -; VISNI-NEXT: slli a1, a1, 2 -; VISNI-NEXT: add a0, a0, a1 -; VISNI-NEXT: fsw fa0, 0(a0) -; VISNI-NEXT: ret %a = load <8 x float>, ptr %x %b = insertelement <8 x float> %a, float %y, i32 %idx store <8 x float> %b, ptr %x @@ -564,12 +406,6 @@ define <8 x i64> @insertelt_v8i64_0(<8 x i64> %a, ptr %x) { ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v8i64_0: -; VISNI: # %bb.0: -; VISNI-NEXT: li a0, -1 -; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %b = insertelement <8 x i64> %a, i64 -1, i32 0 ret <8 x i64> %b } @@ -581,11 +417,6 @@ define <8 x i64> @insertelt_v8i64_sext_0(<8 x i64> %a, ptr %x, i32 signext %elt) ; CHECK-NEXT: vmv.s.x v8, a1 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v8i64_sext_0: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a1 -; VISNI-NEXT: ret %sext = sext i32 %elt to i64 %b = insertelement <8 x i64> %a, i64 %sext, i32 0 ret <8 x i64> %b @@ -605,11 +436,6 @@ define void @insertelt_v8i64_0_store(ptr %x) { ; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v8i64_0_store: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, -1 -; VISNI-NEXT: sd a1, 0(a0) -; VISNI-NEXT: ret %a = load <8 x i64>, ptr %x %b = insertelement <8 x i64> %a, i64 -1, i32 0 store <8 x i64> %b, ptr %x @@ -637,16 +463,6 @@ define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) { ; RV64-NEXT: vslideup.vx v8, v12, a0 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v8i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e64, m1, ta, ma -; VISNI-NEXT: vmv.v.i v12, -1 -; VISNI-NEXT: slli a0, a0, 32 -; VISNI-NEXT: srli a0, a0, 32 -; VISNI-NEXT: addi a1, a0, 1 -; VISNI-NEXT: vsetvli zero, a1, e64, m4, tu, ma -; VISNI-NEXT: vslideup.vx v8, v12, a0 -; VISNI-NEXT: ret %b = insertelement <8 x i64> %a, i64 -1, i32 %idx ret <8 x i64> %b } @@ -671,14 +487,6 @@ define void @insertelt_v8i64_store(ptr %x, i32 %idx) { ; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_v8i64_store: -; VISNI: # %bb.0: -; VISNI-NEXT: andi a1, a1, 7 -; VISNI-NEXT: slli a1, a1, 3 -; VISNI-NEXT: add a0, a0, a1 -; VISNI-NEXT: li a1, -1 -; VISNI-NEXT: sd a1, 0(a0) -; VISNI-NEXT: ret %a = load <8 x i64>, ptr %x %b = insertelement <8 x i64> %a, i64 -1, i32 %idx store <8 x i64> %b, ptr %x @@ -693,12 +501,6 @@ define <8 x i64> @insertelt_c6_v8i64_0(<8 x i64> %a, ptr %x) { ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c6_v8i64_0: -; VISNI: # %bb.0: -; VISNI-NEXT: li a0, 6 -; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %b = insertelement <8 x i64> %a, i64 6, i32 0 ret <8 x i64> %b } @@ -717,11 +519,6 @@ define void @insertelt_c6_v8i64_0_store(ptr %x) { ; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_c6_v8i64_0_store: -; VISNI: # %bb.0: -; VISNI-NEXT: li a1, 6 -; VISNI-NEXT: sd a1, 0(a0) -; VISNI-NEXT: ret %a = load <8 x i64>, ptr %x %b = insertelement <8 x i64> %a, i64 6, i32 0 store <8 x i64> %b, ptr %x @@ -749,16 +546,6 @@ define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) { ; RV64-NEXT: vslideup.vx v8, v12, a0 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_c6_v8i64: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e64, m1, ta, ma -; VISNI-NEXT: vmv.v.i v12, 6 -; VISNI-NEXT: slli a0, a0, 32 -; VISNI-NEXT: srli a0, a0, 32 -; VISNI-NEXT: addi a1, a0, 1 -; VISNI-NEXT: vsetvli zero, a1, e64, m4, tu, ma -; VISNI-NEXT: vslideup.vx v8, v12, a0 -; VISNI-NEXT: ret %b = insertelement <8 x i64> %a, i64 6, i32 %idx ret <8 x i64> %b } @@ -783,14 +570,6 @@ define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) { ; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_c6_v8i64_store: -; VISNI: # %bb.0: -; VISNI-NEXT: andi a1, a1, 7 -; VISNI-NEXT: slli a1, a1, 3 -; VISNI-NEXT: add a0, a0, a1 -; VISNI-NEXT: li a1, 6 -; VISNI-NEXT: sd a1, 0(a0) -; VISNI-NEXT: ret %a = load <8 x i64>, ptr %x %b = insertelement <8 x i64> %a, i64 6, i32 %idx store <8 x i64> %b, ptr %x @@ -813,18 +592,6 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c6_v8i64_0_add: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; VISNI-NEXT: vle64.v v8, (a0) -; VISNI-NEXT: vle64.v v12, (a1) -; VISNI-NEXT: li a1, 6 -; VISNI-NEXT: vsetvli zero, zero, e64, m4, tu, ma -; VISNI-NEXT: vmv.s.x v8, a1 -; VISNI-NEXT: vsetvli zero, zero, e64, m4, ta, ma -; VISNI-NEXT: vadd.vv v8, v8, v12 -; VISNI-NEXT: vse64.v v8, (a0) -; VISNI-NEXT: ret %a = load <8 x i64>, ptr %x %b = insertelement <8 x i64> %a, i64 6, i32 0 %c = load <8 x i64>, ptr %y @@ -843,11 +610,6 @@ define <16 x i32> @insertelt_c0_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_ra ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c0_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 0 ret <16 x i32> %v } @@ -860,11 +622,6 @@ define <16 x i32> @insertelt_c1_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_ra ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c1_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 1 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 1 ret <16 x i32> %v } @@ -877,11 +634,6 @@ define <16 x i32> @insertelt_c2_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_ra ; CHECK-NEXT: vslideup.vi v8, v12, 2 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c2_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 2 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 2 ret <16 x i32> %v } @@ -894,11 +646,6 @@ define <16 x i32> @insertelt_c3_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_ra ; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c3_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 3 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 3 ret <16 x i32> %v } @@ -910,11 +657,6 @@ define <16 x i32> @insertelt_c12_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_r ; CHECK-NEXT: vmv.s.x v11, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c12_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, tu, ma -; VISNI-NEXT: vmv.s.x v11, a0 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 12 ret <16 x i32> %v } @@ -927,11 +669,6 @@ define <16 x i32> @insertelt_c13_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_r ; CHECK-NEXT: vslideup.vi v11, v12, 1 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c13_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v11, a0, 1 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 13 ret <16 x i32> %v } @@ -944,11 +681,6 @@ define <16 x i32> @insertelt_c14_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_r ; CHECK-NEXT: vslideup.vi v11, v12, 2 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c14_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v11, a0, 2 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 14 ret <16 x i32> %v } @@ -961,11 +693,6 @@ define <16 x i32> @insertelt_c15_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_r ; CHECK-NEXT: vslideup.vi v11, v12, 3 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_c15_v16xi32_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v11, a0, 3 -; VISNI-NEXT: ret %v = insertelement <16 x i32> %vin, i32 %a, i32 15 ret <16 x i32> %v } @@ -984,11 +711,6 @@ define <8 x i64> @insertelt_c4_v8xi64_exact(<8 x i64> %vin, i64 %a) vscale_range ; RV64-NEXT: vmv.s.x v10, a0 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_c4_v8xi64_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma -; VISNI-NEXT: vmv.s.x v10, a0 -; VISNI-NEXT: ret %v = insertelement <8 x i64> %vin, i64 %a, i32 4 ret <8 x i64> %v } @@ -1010,11 +732,6 @@ define <8 x i64> @insertelt_c5_v8xi64_exact(<8 x i64> %vin, i64 %a) vscale_range ; RV64-NEXT: vslideup.vi v10, v12, 1 ; RV64-NEXT: ret ; -; VISNI-LABEL: insertelt_c5_v8xi64_exact: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 8, e64, m1, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v10, a0, 1 -; VISNI-NEXT: ret %v = insertelement <8 x i64> %vin, i64 %a, i32 5 ret <8 x i64> %v } @@ -1027,12 +744,6 @@ define <4 x bfloat> @insertelt_v4bf16_0(<4 x bfloat> %a, bfloat %y) { ; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v4bf16_0: -; VISNI: # %bb.0: -; VISNI-NEXT: fmv.x.h a0, fa0 -; VISNI-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; VISNI-NEXT: vmv.s.x v8, a0 -; VISNI-NEXT: ret %b = insertelement <4 x bfloat> %a, bfloat %y, i32 0 ret <4 x bfloat> %b } @@ -1046,12 +757,6 @@ define <4 x bfloat> @insertelt_v4bf16_3(<4 x bfloat> %a, bfloat %y) { ; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v4bf16_3: -; VISNI: # %bb.0: -; VISNI-NEXT: fmv.x.h a0, fa0 -; VISNI-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; VISNI-NEXT: ri.vinsert.v.x v8, a0, 3 -; VISNI-NEXT: ret %b = insertelement <4 x bfloat> %a, bfloat %y, i32 3 ret <4 x bfloat> %b } @@ -1067,15 +772,6 @@ define <4 x bfloat> @insertelt_v4bf16_idx(<4 x bfloat> %a, bfloat %y, i32 zeroex ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret ; -; VISNI-LABEL: insertelt_v4bf16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: addi a1, a0, 1 -; VISNI-NEXT: fmv.x.h a2, fa0 -; VISNI-NEXT: vsetivli zero, 4, e16, m1, ta, ma -; VISNI-NEXT: vmv.s.x v9, a2 -; VISNI-NEXT: vsetvli zero, a1, e16, mf2, tu, ma -; VISNI-NEXT: vslideup.vx v8, v9, a0 -; VISNI-NEXT: ret %b = insertelement <4 x bfloat> %a, bfloat %y, i32 %idx ret <4 x bfloat> %b } @@ -1094,11 +790,6 @@ define <4 x half> @insertelt_v4f16_0(<4 x half> %a, half %y) { ; ZVFHMIN-NEXT: vmv.s.x v8, a0 ; ZVFHMIN-NEXT: ret ; -; VISNI-LABEL: insertelt_v4f16_0: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; VISNI-NEXT: vfmv.s.f v8, fa0 -; VISNI-NEXT: ret %b = insertelement <4 x half> %a, half %y, i32 0 ret <4 x half> %b } @@ -1119,12 +810,6 @@ define <4 x half> @insertelt_v4f16_3(<4 x half> %a, half %y) { ; ZVFHMIN-NEXT: vslideup.vi v8, v9, 3 ; ZVFHMIN-NEXT: ret ; -; VISNI-LABEL: insertelt_v4f16_3: -; VISNI: # %bb.0: -; VISNI-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; VISNI-NEXT: vfmv.s.f v9, fa0 -; VISNI-NEXT: vslideup.vi v8, v9, 3 -; VISNI-NEXT: ret %b = insertelement <4 x half> %a, half %y, i32 3 ret <4 x half> %b } @@ -1149,14 +834,6 @@ define <4 x half> @insertelt_v4f16_idx(<4 x half> %a, half %y, i32 zeroext %idx) ; ZVFHMIN-NEXT: vslideup.vx v8, v9, a0 ; ZVFHMIN-NEXT: ret ; -; VISNI-LABEL: insertelt_v4f16_idx: -; VISNI: # %bb.0: -; VISNI-NEXT: addi a1, a0, 1 -; VISNI-NEXT: vsetivli zero, 4, e16, m1, ta, ma -; VISNI-NEXT: vfmv.s.f v9, fa0 -; VISNI-NEXT: vsetvli zero, a1, e16, mf2, tu, ma -; VISNI-NEXT: vslideup.vx v8, v9, a0 -; VISNI-NEXT: ret %b = insertelement <4 x half> %a, half %y, i32 %idx ret <4 x half> %b } @@ -1171,14 +848,6 @@ define <2 x i8> @pr169017(<4 x i16> %vecinit, <2 x i8> %dst_vec) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; VISNI-LABEL: pr169017: -; VISNI: # %bb.0: # %entry -; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; VISNI-NEXT: vmv.x.s a0, v8 -; VISNI-NEXT: vsetvli zero, zero, e8, mf8, tu, ma -; VISNI-NEXT: vmv.s.x v9, a0 -; VISNI-NEXT: vmv1r.v v8, v9 -; VISNI-NEXT: ret entry: %cast = bitcast <4 x i16> %vecinit to i64 %trunc = trunc i64 %cast to i8 diff --git a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll index 36d2c75ce527..3cc6f8c5c5ab 100644 --- a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll +++ b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll @@ -158,9 +158,9 @@ define dso_local noundef signext i32 @main() #2 !dbg !28 { ret i32 %6, !dbg !36 } -attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } -attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } -attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!2, !3, !4, !5, !6, !8, !9} diff --git a/llvm/test/MC/RISCV/xrivosvisni-valid.s b/llvm/test/MC/RISCV/xrivosvisni-valid.s deleted file mode 100644 index 9dbea6ecb590..000000000000 --- a/llvm/test/MC/RISCV/xrivosvisni-valid.s +++ /dev/null @@ -1,43 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvisni -M no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvisni < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvisni -M no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvisni < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: ri.vzero.v v0 -# CHECK-ASM: encoding: [0x5b,0x70,0x00,0x00] -ri.vzero.v v0 -# CHECK-ASM-AND-OBJ: ri.vzero.v v1 -# CHECK-ASM: encoding: [0xdb,0x70,0x00,0x00] -ri.vzero.v v1 -# CHECK-ASM-AND-OBJ: ri.vzero.v v2 -# CHECK-ASM: encoding: [0x5b,0x71,0x00,0x00] -ri.vzero.v v2 -# CHECK-ASM-AND-OBJ: ri.vzero.v v3 -# CHECK-ASM: encoding: [0xdb,0x71,0x00,0x00] -ri.vzero.v v3 - -# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v0, zero, 0 -# CHECK-ASM: encoding: [0x5b,0x60,0x00,0x40] -ri.vinsert.v.x v0, x0, 0 -# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v1, s4, 13 -# CHECK-ASM: encoding: [0xdb,0x60,0xda,0x40] -ri.vinsert.v.x v1, x20, 13 -# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v1, zero, 1 -# CHECK-ASM: encoding: [0xdb,0x60,0x10,0x40] -ri.vinsert.v.x v1, x0, 1 -# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v23, ra, 1 -# CHECK-ASM: encoding: [0xdb,0xeb,0x10,0x40] -ri.vinsert.v.x v23, x1, 1 - -# CHECK-ASM-AND-OBJ: ri.vextract.x.v s4, v1, 13 -# CHECK-ASM: encoding: [0x5b,0xaa,0x16,0x5e] -ri.vextract.x.v x20, v1, 13 -# CHECK-ASM-AND-OBJ: ri.vextract.x.v s5, v2, 31 -# CHECK-ASM: encoding: [0xdb,0xaa,0x2f,0x5e] -ri.vextract.x.v x21, v2, 31 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 38efdb87ee88..374db30891ba 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1386,7 +1386,6 @@ Experimental extensions zvzip 0.1 smpmpmt 0.6 svukte 0.3 - xrivosvisni 0.1 xrivosvizip 0.1 xsfmclic 0.1 xsfsclic 0.1