diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 1cd1a9a0f733..8d3134c14775 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -982,6 +982,7 @@ class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
   : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
   bits<4> Ra;
   let Inst{15-12} = Ra;
+  let hasSideEffects = 0;
 }
 
 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index ddc89415cfb2..b72aa4b28736 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -1797,6 +1797,7 @@ multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
     let Inst{3-0} = Rm;
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
+    let hasSideEffects = 0;
   }
 
   def rsi : AsI1<opcod, (outs GPR:$Rd),
@@ -2735,6 +2736,7 @@ let isBranch = 1, isTerminator = 1 in {
     bits<24> target;
     let Inst{23-0} = target;
     let DecoderMethod = "DecodeBranchImmInstruction";
+    let hasSideEffects = 0;
   }
 
   let isBarrier = 1 in {
@@ -3964,6 +3966,7 @@ def SBFX  : I<(outs GPRnopc:$Rd),
   let Inst{15-12} = Rd;
   let Inst{11-7}  = lsb;
   let Inst{3-0}   = Rn;
+  let hasSideEffects = 0;
 }
 
 def UBFX  : I<(outs GPRnopc:$Rd),
@@ -3981,6 +3984,7 @@ def UBFX  : I<(outs GPRnopc:$Rd),
   let Inst{15-12} = Rd;
   let Inst{11-7}  = lsb;
   let Inst{3-0}   = Rn;
+  let hasSideEffects = 0;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 462ac8bea45f..a4e90204705b 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -2638,6 +2638,7 @@ class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
         [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
 
 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
+let hasSideEffects = 0 in {
 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
   : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
         (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
@@ -2648,6 +2649,7 @@ class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
   : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
         (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
         "$src1 = $Vd, $src2 = $Vm", []>;
+}
 
 // Basic 3-register operations: double- and quad-register.
 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
@@ -4867,6 +4869,7 @@ multiclass DOTI<string opc, string dt, bit Q, bit U, RegisterClass Ty,
     let Constraints = "$dst = $Vd";
     let Predicates = [HasDotProd];
     let DecoderNamespace = "VFPV8";
+    let hasSideEffects = 0;
   }
 
   def : Pat<
@@ -5087,9 +5090,11 @@ multiclass N3VCP8ComplexTiedLane<bit op4, string OpcodeStr> {
   }
 }
 
+let hasSideEffects = 0 in {
 defm VCMLA : N3VCP8ComplexTied<1, 0, "vcmla">;
 defm VCADD : N3VCP8ComplexOdd<1, 0, 0, "vcadd">;
 defm VCMLA : N3VCP8ComplexTiedLane<0, "vcmla">;
+}
 
 let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
   def : Pat<(v4f16 (int_arm_neon_vcadd_rot90 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm))),
@@ -5627,6 +5632,8 @@ def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
           (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
 }
 
+let hasSideEffects = 0 in {
+
 //   VBSL     : Vector Bitwise Select
 def  VBSLd    : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
                      (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
@@ -5666,6 +5673,8 @@ def  VBITq    : N3VX<1, 0, 0b10, 0b0001, 1, 1,
                      "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      []>;
 
+} // hasSideEffects = 0
+
 // Vector Absolute Differences.
 
 //   VABD     : Vector Absolute Difference
@@ -9233,6 +9242,7 @@ multiclass BF16VDOTI<bit Q, RegisterClass RegTy, string opc, ValueType AccumTy,
     let Constraints = "$dst = $Vd";
     let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm$lane");
     let DecoderNamespace = "VFPV8";
+    let hasSideEffects = 0;
   }
 
   def : Pat<
@@ -9289,6 +9299,7 @@ multiclass VBF16MALQI<bit T, string suffix, SDPatternOperator OpNode> {
   let Inst{3} = idx{0};
   let Constraints = "$dst = $Vd";
   let DecoderNamespace = "VFPV8";
+  let hasSideEffects = 0;
   }
 
   def : Pat<
@@ -9306,8 +9317,9 @@ multiclass VBF16MALQI<bit T, string suffix, SDPatternOperator OpNode> {
 defm VBF16MALTQI: VBF16MALQI<1, "t", int_arm_neon_bfmlalt>;
 defm VBF16MALBQI: VBF16MALQI<0, "b", int_arm_neon_bfmlalb>;
 
+let hasSideEffects = 0 in
 def BF16_VCVT :  N2V<0b11, 0b11, 0b01, 0b10, 0b01100, 1, 0,
                     (outs DPR:$Vd), (ins QPR:$Vm),
                     NoItinerary, "vcvt", "bf16.f32", "$Vd, $Vm", "", []>;
-}
+} // Predicates = [HasBF16, HasNEON]
 // End of BFloat16 instructions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 4c5d81012da3..7512922e1cff 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -427,6 +427,7 @@ def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
   bits<7> imm;
   let Inst{6-0} = imm;
   let DecoderMethod = "DecodeThumbAddSPImm";
+  let hasSideEffects = 0;
 }
 
 // SUB sp, sp, #<imm7>
@@ -438,6 +439,7 @@ def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
   bits<7> imm;
   let Inst{6-0} = imm;
   let DecoderMethod = "DecodeThumbAddSPImm";
+  let hasSideEffects = 0;
 }
 
 def : tInstSubst<"add${p} sp, $imm",
@@ -461,6 +463,7 @@ def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
   let Inst{6-3} = 0b1101;
   let Inst{2-0} = Rdn{2-0};
   let DecoderMethod = "DecodeThumbAddSPReg";
+  let hasSideEffects = 0;
 }
 
 // ADD sp, <Rm>
@@ -473,6 +476,7 @@ def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
   let Inst{6-3} = Rm;
   let Inst{2-0} = 0b101;
   let DecoderMethod = "DecodeThumbAddSPReg";
+  let hasSideEffects = 0;
 }
 
 //===----------------------------------------------------------------------===//
@@ -480,7 +484,7 @@ def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
 //
 
 // Indirect branches
-let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, hasSideEffects = 0 in {
   def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
             T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
     // A6.2.3 & A8.6.25
@@ -633,7 +637,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 
 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let isBranch = 1, isTerminator = 1 in
+let isBranch = 1, isTerminator = 1, hasSideEffects = 0 in
   def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br,
                  "b${p}\t$target",
                  [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
@@ -973,7 +977,7 @@ class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
   let Inst{7-0}  = imm8;
 }
 
-let isAdd = 1 in {
+let isAdd = 1, hasSideEffects = 0 in {
   // Add with carry register
   let isCommutable = 1, Uses = [CPSR] in
   def tADC :                      // A8.6.2
@@ -1130,7 +1134,7 @@ def tCMNz :                     // A8.6.33
 } // isCompare = 1, Defs = [CPSR]
 
 // CMP immediate
-let isCompare = 1, Defs = [CPSR] in {
+let isCompare = 1, Defs = [CPSR], hasSideEffects = 0 in {
 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
                   "cmp", "\t$Rn, $imm8",
                   [(set CPSR, (ARMcmp tGPR:$Rn, imm0_255:$imm8))]>,
@@ -1319,7 +1323,7 @@ def tRSB :                      // A8.6.141
                [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
 
 // Subtract with carry register
-let Uses = [CPSR] in
+let Uses = [CPSR], hasSideEffects = 0 in
 def tSBC :                      // A8.6.151
   T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iALUr,
@@ -1495,6 +1499,7 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
   let Inst{10-8} = Rd;
   let Inst{7-0} = addr;
   let DecoderMethod = "DecodeThumbAddSpecialReg";
+  let hasSideEffects = 0;
 }
 
 let hasSideEffects = 0, isReMaterializable = 1 in
@@ -1679,7 +1684,7 @@ def : T1Pat<(extloadi16 t_addrmode_rr:$addr),  (tLDRHr t_addrmode_rr:$addr)>;
 // post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
 // different to how ISel expects them for a post-inc load, so use a pseudo
 // and expand it just after ISel.
-let usesCustomInserter = 1, mayLoad =1,
+let usesCustomInserter = 1, mayLoad = 1, hasSideEffects = 0,
     Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in
  def tLDR_postidx: tPseudoInst<(outs tGPR:$Rt, tGPR:$Rn_wb),
                                (ins tGPR:$Rn, pred:$p),
@@ -1798,6 +1803,7 @@ def : tInstAlias<"asr${s}${p} $Rdm, $imm",
              (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
 
 // Pseudo instruction ldr Rt, =immediate
+let hasSideEffects = 0 in
 def tLDRConstPool
   : tAsmPseudo<"ldr${p} $Rt, $immediate",
                (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 596196c4d042..4c281ca87976 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -848,6 +848,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
      let Inst{14-12} = 0b000; // imm3
      let Inst{7-6} = 0b00; // imm2
      let Inst{5-4} = 0b00; // type
+     let hasSideEffects = 0;
    }
    // shifted register
    def rs : T2sTwoRegShiftedReg<
@@ -938,6 +939,7 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
     let Inst{15}    = 0;
 
     let DecoderMethod = "DecodeT2AddSubSPImm";
+    let hasSideEffects = 0;
    }
 
    def ri : T2sTwoRegImm<
@@ -991,6 +993,7 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
        let Inst{11-8} = Rd;
        let Inst{7-0} = imm{7-0};
        let DecoderMethod = "DecodeT2AddSubSPImm";
+       let hasSideEffects = 0;
      }
    // register
    def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
@@ -1440,6 +1443,7 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
   let Inst{7-0}   = addr{7-0};
 
   let DecoderMethod = "DecodeT2Adr";
+  let hasSideEffects = 0;
 }
 
 let hasSideEffects = 0, isReMaterializable = 1 in
@@ -2549,7 +2553,7 @@ def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
 }
 
 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
-// And Miscellaneous operations -- for disassembly only
+// And Miscellaneous operations
 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
               list<dag> pat, dag iops, string asm>
   : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
@@ -3126,6 +3130,8 @@ class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = op22_20;
   let Inst{7-4} = op7_4;
+
+  let hasSideEffects = 0;
 }
 
 def t2SMMLA :   T2FourRegSMMLA<0b101, 0b0000, "smmla",
@@ -3673,15 +3679,14 @@ def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary,
   let Inst{31-0} = 0xf3af8012;
   let DecoderMethod = "DecodeTSBInstruction";
 }
-}
 
 // Armv8.5-A speculation barrier
 def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
            Requires<[IsThumb2, HasSB]>, Sched<[]> {
   let Inst{31-0} = 0xf3bf8f70;
   let Unpredictable = 0x000f2f0f;
-  let hasSideEffects = 1;
 }
+} // hasSideEffects = 1
 
 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
                 InstrItinClass itin, string opc, string asm, string cstr,
@@ -4037,7 +4042,7 @@ def t2TBH : T2I<(outs), (ins (addrmode_tbh $Rn, $Rm):$addr), IIC_Br,
 
 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
 // a two-value operand where a dag node expects ", "two operands. :(
-let isBranch = 1, isTerminator = 1 in
+let isBranch = 1, isTerminator = 1, hasSideEffects = 0 in
 def t2Bcc : Thumb2XI<(outs), (ins brtarget:$target, pred:$p),
                      AddrModeNone, 4, IIC_Br,
                      "b${p}.w\t$target", "",
@@ -4107,7 +4112,7 @@ def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
 def : t2InstAlias<"bl${p}.w $func", (tBL pred:$p, thumb_bl_target:$func), 0>;
 
 // Compare and branch on zero / non-zero
-let isBranch = 1, isTerminator = 1 in {
+let isBranch = 1, isTerminator = 1, hasSideEffects = 0 in {
   def tCBZ  : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
                   "cbz\t$Rn, $target", []>,
               T1Misc<{0,0,?,1,?,?,?}>,
@@ -5419,6 +5424,7 @@ def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
 // these, unfortunately.
 // FIXME: LSL #0 in the shift should allow SP to be used as either the
 // source or destination (but not both).
+let hasSideEffects = 0 in {
 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
                          (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
@@ -5428,6 +5434,7 @@ def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
                          (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
                           (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
+}
 
 // Aliases for the above with the .w qualifier
 def : t2InstAlias<"mov${p}.w $Rd, $shift",
diff --git a/llvm/test/CodeGen/ARM/bfx.ll b/llvm/test/CodeGen/ARM/bfx.ll
index 2c152be6d764..6c505bea12e7 100644
--- a/llvm/test/CodeGen/ARM/bfx.ll
+++ b/llvm/test/CodeGen/ARM/bfx.ll
@@ -37,11 +37,11 @@ define i32 @ubfx2(i32 %a) {
 define i32 @ubfx_opt(ptr nocapture %ctx, i32 %x) nounwind readonly ssp {
 ; CHECK-LABEL: ubfx_opt:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    lsr r2, r1, #24
-; CHECK-NEXT:    ldr r2, [r0, r2, lsl #2]
 ; CHECK-NEXT:    ubfx r3, r1, #16, #8
-; CHECK-NEXT:    ldr r3, [r0, r3, lsl #2]
+; CHECK-NEXT:    lsr r2, r1, #24
 ; CHECK-NEXT:    ubfx r1, r1, #8, #8
+; CHECK-NEXT:    ldr r2, [r0, r2, lsl #2]
+; CHECK-NEXT:    ldr r3, [r0, r3, lsl #2]
 ; CHECK-NEXT:    ldr r0, [r0, r1, lsl #2]
 ; CHECK-NEXT:    add r2, r3, r2
 ; CHECK-NEXT:    add r0, r2, r0
diff --git a/llvm/test/CodeGen/ARM/extract-bits.ll b/llvm/test/CodeGen/ARM/extract-bits.ll
index d717806098fb..e900fb737c73 100644
--- a/llvm/test/CodeGen/ARM/extract-bits.ll
+++ b/llvm/test/CodeGen/ARM/extract-bits.ll
@@ -4479,10 +4479,9 @@ define void @c5_i64(i64 %arg, ptr %ptr) nounwind {
 ;
 ; V7A-LABEL: c5_i64:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    mov r0, #0
-; V7A-NEXT:    str r0, [r2, #4]
 ; V7A-NEXT:    ubfx r0, r1, #19, #10
-; V7A-NEXT:    str r0, [r2]
+; V7A-NEXT:    mov r3, #0
+; V7A-NEXT:    stm r2, {r0, r3}
 ; V7A-NEXT:    bx lr
 ;
 ; V7A-T-LABEL: c5_i64:
@@ -4517,10 +4516,9 @@ define void @c6_i64(i64 %arg, ptr %ptr) nounwind {
 ;
 ; V7A-LABEL: c6_i64:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    mov r0, #0
-; V7A-NEXT:    str r0, [r2, #4]
 ; V7A-NEXT:    ubfx r0, r1, #19, #12
-; V7A-NEXT:    str r0, [r2]
+; V7A-NEXT:    mov r3, #0
+; V7A-NEXT:    stm r2, {r0, r3}
 ; V7A-NEXT:    bx lr
 ;
 ; V7A-T-LABEL: c6_i64:
diff --git a/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll b/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
index e439dfda08e0..40b360e9158f 100644
--- a/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
@@ -34,6 +34,7 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) {
 ; CHECK-NEXT:    sbcs r0, r1, #0
 ; CHECK-NEXT:    vmov.32 d8[1], r1
 ; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    adr r4, .LCPI0_1
 ; CHECK-NEXT:    movwlt r0, #1
 ; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    vdup.32 d19, r5
@@ -42,7 +43,6 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) {
 ; CHECK-NEXT:    mov r2, #0
 ; CHECK-NEXT:    vdup.32 d18, r0
 ; CHECK-NEXT:    vbit q8, q4, q9
-; CHECK-NEXT:    adr r4, .LCPI0_1
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r4:128]
 ; CHECK-NEXT:    vmov r0, r1, d17
 ; CHECK-NEXT:    vmov r3, r5, d16
@@ -261,11 +261,11 @@ define <4 x i32> @stest_f32i32(<4 x float> %x) {
 ; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    mvnne r0, #0
 ; CHECK-NEXT:    vmov.32 d12[1], r1
+; CHECK-NEXT:    adr r1, .LCPI3_1
 ; CHECK-NEXT:    rsbs r3, r11, #-2147483648
 ; CHECK-NEXT:    vdup.32 d16, r0
 ; CHECK-NEXT:    mvn r0, #0
 ; CHECK-NEXT:    vbsl q8, q6, q5
-; CHECK-NEXT:    adr r1, .LCPI3_1
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r1:128]
 ; CHECK-NEXT:    sbcs r3, r0, r10
 ; CHECK-NEXT:    mov r3, #0
@@ -582,11 +582,11 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
 ; CHECK-NEON-NEXT:    cmp r0, #0
 ; CHECK-NEON-NEXT:    mvnne r0, #0
 ; CHECK-NEON-NEXT:    vmov.32 d12[1], r1
+; CHECK-NEON-NEXT:    adr r1, .LCPI6_1
 ; CHECK-NEON-NEXT:    rsbs r3, r11, #-2147483648
 ; CHECK-NEON-NEXT:    vdup.32 d16, r0
 ; CHECK-NEON-NEXT:    mvn r0, #0
 ; CHECK-NEON-NEXT:    vbsl q8, q6, q4
-; CHECK-NEON-NEXT:    adr r1, .LCPI6_1
 ; CHECK-NEON-NEXT:    vld1.64 {d18, d19}, [r1:128]
 ; CHECK-NEON-NEXT:    sbcs r3, r0, r10
 ; CHECK-NEON-NEXT:    mov r3, #0
@@ -699,11 +699,11 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
 ; CHECK-FP16-NEXT:    cmp r0, #0
 ; CHECK-FP16-NEXT:    mvnne r0, #0
 ; CHECK-FP16-NEXT:    vmov.32 d12[1], r1
+; CHECK-FP16-NEXT:    adr r1, .LCPI6_1
 ; CHECK-FP16-NEXT:    rsbs r3, r9, #-2147483648
 ; CHECK-FP16-NEXT:    vdup.32 d16, r0
 ; CHECK-FP16-NEXT:    mvn r0, #0
 ; CHECK-FP16-NEXT:    vbsl q8, q6, q5
-; CHECK-FP16-NEXT:    adr r1, .LCPI6_1
 ; CHECK-FP16-NEXT:    vld1.64 {d18, d19}, [r1:128]
 ; CHECK-FP16-NEXT:    sbcs r3, r0, r8
 ; CHECK-FP16-NEXT:    mov r3, #0
diff --git a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
index 920742fffcf1..be20eec80f40 100644
--- a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -166,16 +166,15 @@ define void @andVec(ptr %A) nounwind {
 ; CHECK-NEXT:    vmov.i16 d17, #0x7
 ; CHECK-NEXT:    str r1, [sp, #4]
 ; CHECK-NEXT:    add r1, sp, #4
+; CHECK-NEXT:    mov r2, sp
 ; CHECK-NEXT:    vld1.32 {d16[0]}, [r1:32]
-; CHECK-NEXT:    mov r1, sp
 ; CHECK-NEXT:    vmovl.u8 q9, d16
 ; CHECK-NEXT:    vand d16, d18, d17
-; CHECK-NEXT:    vorr d17, d16, d16
-; CHECK-NEXT:    vuzp.8 d17, d18
-; CHECK-NEXT:    vst1.32 {d17[0]}, [r1:32]
-; CHECK-NEXT:    vld1.32 {d17[0]}, [r1:32]
 ; CHECK-NEXT:    vmov.u16 r1, d16[2]
-; CHECK-NEXT:    vmovl.u16 q8, d17
+; CHECK-NEXT:    vuzp.8 d16, d17
+; CHECK-NEXT:    vst1.32 {d16[0]}, [r2:32]
+; CHECK-NEXT:    vld1.32 {d16[0]}, [r2:32]
+; CHECK-NEXT:    vmovl.u16 q8, d16
 ; CHECK-NEXT:    vmov.32 r2, d16[0]
 ; CHECK-NEXT:    strb r1, [r0, #2]
 ; CHECK-NEXT:    strh r2, [r0]
@@ -195,18 +194,17 @@ define void @orVec(ptr %A) nounwind {
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, sp, #8
 ; CHECK-NEXT:    ldr r1, [r0]
+; CHECK-NEXT:    mov r2, sp
 ; CHECK-NEXT:    str r1, [sp, #4]
 ; CHECK-NEXT:    add r1, sp, #4
 ; CHECK-NEXT:    vld1.32 {d16[0]}, [r1:32]
-; CHECK-NEXT:    mov r1, sp
 ; CHECK-NEXT:    vmovl.u8 q8, d16
 ; CHECK-NEXT:    vorr.i16 d16, #0x7
-; CHECK-NEXT:    vorr d18, d16, d16
-; CHECK-NEXT:    vuzp.8 d18, d19
-; CHECK-NEXT:    vst1.32 {d18[0]}, [r1:32]
-; CHECK-NEXT:    vld1.32 {d18[0]}, [r1:32]
 ; CHECK-NEXT:    vmov.u16 r1, d16[2]
-; CHECK-NEXT:    vmovl.u16 q8, d18
+; CHECK-NEXT:    vuzp.8 d16, d18
+; CHECK-NEXT:    vst1.32 {d16[0]}, [r2:32]
+; CHECK-NEXT:    vld1.32 {d16[0]}, [r2:32]
+; CHECK-NEXT:    vmovl.u16 q8, d16
 ; CHECK-NEXT:    vmov.32 r2, d16[0]
 ; CHECK-NEXT:    strb r1, [r0, #2]
 ; CHECK-NEXT:    strh r2, [r0]
diff --git a/llvm/test/CodeGen/ARM/vector-store.ll b/llvm/test/CodeGen/ARM/vector-store.ll
index a0a801d2b6d2..b989a6b8d873 100644
--- a/llvm/test/CodeGen/ARM/vector-store.ll
+++ b/llvm/test/CodeGen/ARM/vector-store.ll
@@ -539,11 +539,11 @@ define void @truncstore_v4i32tov4i8(ptr %ptr, <4 x i32> %val) {
 ; CHECK-BE:       @ %bb.0:
 ; CHECK-BE-NEXT:    vldr d17, [sp]
 ; CHECK-BE-NEXT:    vmov d16, r3, r2
+; CHECK-BE-NEXT:    ldr r0, [r0]
 ; CHECK-BE-NEXT:    vrev64.32 q8, q8
 ; CHECK-BE-NEXT:    vmovn.i32 d16, q8
 ; CHECK-BE-NEXT:    vrev16.8 d16, d16
 ; CHECK-BE-NEXT:    vuzp.8 d16, d17
-; CHECK-BE-NEXT:    ldr r0, [r0]
 ; CHECK-BE-NEXT:    vrev32.8 d16, d17
 ; CHECK-BE-NEXT:    vst1.32 {d16[0]}, [r0:32]
 ; CHECK-BE-NEXT:    bx lr
@@ -570,12 +570,12 @@ define void @truncstore_v4i32tov4i8_fake_update(ptr %ptr, <4 x i32> %val) {
 ; CHECK-BE:       @ %bb.0:
 ; CHECK-BE-NEXT:    vldr d17, [sp]
 ; CHECK-BE-NEXT:    vmov d16, r3, r2
+; CHECK-BE-NEXT:    ldr r1, [r0]
 ; CHECK-BE-NEXT:    movs r2, #16
 ; CHECK-BE-NEXT:    vrev64.32 q8, q8
 ; CHECK-BE-NEXT:    vmovn.i32 d16, q8
 ; CHECK-BE-NEXT:    vrev16.8 d16, d16
 ; CHECK-BE-NEXT:    vuzp.8 d16, d17
-; CHECK-BE-NEXT:    ldr r1, [r0]
 ; CHECK-BE-NEXT:    vrev32.8 d16, d17
 ; CHECK-BE-NEXT:    vst1.32 {d16[0]}, [r1:32], r2
 ; CHECK-BE-NEXT:    str r1, [r0]
diff --git a/llvm/test/CodeGen/ARM/vext.ll b/llvm/test/CodeGen/ARM/vext.ll
index 46f778d3c2c9..f1672643e459 100644
--- a/llvm/test/CodeGen/ARM/vext.ll
+++ b/llvm/test/CodeGen/ARM/vext.ll
@@ -221,8 +221,8 @@ define <4 x i16> @test_multisource(ptr %B) nounwind {
 ; CHECK-NEXT:    vld1.16 {d20, d21}, [r0:128]!
 ; CHECK-NEXT:    vorr d23, d20, d20
 ; CHECK-NEXT:    vldr d22, [r0]
-; CHECK-NEXT:    vzip.16 d23, d22
 ; CHECK-NEXT:    vtrn.16 d16, d18
+; CHECK-NEXT:    vzip.16 d23, d22
 ; CHECK-NEXT:    vext.16 d18, d20, d23, #2
 ; CHECK-NEXT:    vext.16 d16, d18, d16, #2
 ; CHECK-NEXT:    vext.16 d16, d16, d16, #2
diff --git a/llvm/test/CodeGen/ARM/vselect_imax.ll b/llvm/test/CodeGen/ARM/vselect_imax.ll
index bd5e3061f0d1..77f36a938c13 100644
--- a/llvm/test/CodeGen/ARM/vselect_imax.ll
+++ b/llvm/test/CodeGen/ARM/vselect_imax.ll
@@ -147,6 +147,7 @@ define void @func_blend18(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vdup.32 d25, r2
 ; CHECK-NEXT:    vdup.32 d24, r6
 ; CHECK-NEXT:    vbit q8, q11, q12
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r3:128]!
 ; CHECK-NEXT:    subs r4, r4, lr
 ; CHECK-NEXT:    sbcs r5, r5, r12
 ; CHECK-NEXT:    movlt r0, #1
@@ -155,7 +156,6 @@ define void @func_blend18(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vdup.32 d27, r0
 ; CHECK-NEXT:    vdup.32 d26, r1
 ; CHECK-NEXT:    vbit q9, q10, q13
-; CHECK-NEXT:    vst1.64 {d16, d17}, [r3:128]!
 ; CHECK-NEXT:    vst1.64 {d18, d19}, [r3:128]
 ; CHECK-NEXT:    pop {r4, r5, r6, lr}
 ; CHECK-NEXT:    mov pc, lr
@@ -214,6 +214,7 @@ define void @func_blend19(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    mvnne r0, #0
 ; CHECK-NEXT:    vdup.32 d0, r0
 ; CHECK-NEXT:    vmov r0, r1, d22
+; CHECK-NEXT:    vbit q10, q12, q0
 ; CHECK-NEXT:    subs r0, r2, r0
 ; CHECK-NEXT:    mov r2, #0
 ; CHECK-NEXT:    sbcs r0, r4, r1
@@ -241,7 +242,8 @@ define void @func_blend19(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vdup.32 d2, r0
 ; CHECK-NEXT:    vmov r0, r1, d23
 ; CHECK-NEXT:    vbit q14, q15, q1
-; CHECK-NEXT:    vbit q10, q12, q0
+; CHECK-NEXT:    vst1.64 {d28, d29}, [r3:128]!
+; CHECK-NEXT:    vst1.64 {d20, d21}, [r3:128]!
 ; CHECK-NEXT:    subs r0, r4, r0
 ; CHECK-NEXT:    sbcs r0, r5, r1
 ; CHECK-NEXT:    vmov r1, r4, d17
@@ -253,7 +255,7 @@ define void @func_blend19(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vdup.32 d31, r0
 ; CHECK-NEXT:    vdup.32 d30, r2
 ; CHECK-NEXT:    vbit q11, q13, q15
-; CHECK-NEXT:    vst1.64 {d28, d29}, [r3:128]!
+; CHECK-NEXT:    vst1.64 {d22, d23}, [r3:128]!
 ; CHECK-NEXT:    subs r1, r5, r1
 ; CHECK-NEXT:    sbcs r1, r6, r4
 ; CHECK-NEXT:    movlt lr, #1
@@ -262,8 +264,6 @@ define void @func_blend19(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vdup.32 d3, lr
 ; CHECK-NEXT:    vdup.32 d2, r12
 ; CHECK-NEXT:    vbit q8, q9, q1
-; CHECK-NEXT:    vst1.64 {d20, d21}, [r3:128]!
-; CHECK-NEXT:    vst1.64 {d22, d23}, [r3:128]!
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r3:128]
 ; CHECK-NEXT:    pop {r4, r5, r6, lr}
 ; CHECK-NEXT:    mov pc, lr
@@ -296,8 +296,9 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vmov r6, r7, d25
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [lr:128]!
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r8:128]!
-; CHECK-NEXT:    vld1.64 {d22, d23}, [r8:128]!
 ; CHECK-NEXT:    vld1.64 {d0, d1}, [lr:128]!
+; CHECK-NEXT:    vld1.64 {d22, d23}, [r8:128]!
+; CHECK-NEXT:    vld1.64 {d28, d29}, [lr:128]!
 ; CHECK-NEXT:    subs r4, r6, r4
 ; CHECK-NEXT:    sbcs r4, r7, r5
 ; CHECK-NEXT:    vmov r5, r6, d16
@@ -319,7 +320,7 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vbit q8, q12, q13
 ; CHECK-NEXT:    vld1.64 {d24, d25}, [r0:128]!
 ; CHECK-NEXT:    vld1.64 {d26, d27}, [r1:128]!
-; CHECK-NEXT:    vld1.64 {d28, d29}, [lr:128]!
+; CHECK-NEXT:    vld1.64 {d6, d7}, [r0:128]!
 ; CHECK-NEXT:    subs r2, r5, r2
 ; CHECK-NEXT:    sbcs r2, r6, r4
 ; CHECK-NEXT:    vmov r4, r5, d22
@@ -338,6 +339,8 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    cmp r4, #0
 ; CHECK-NEXT:    mvnne r4, #0
 ; CHECK-NEXT:    vdup.32 d2, r4
+; CHECK-NEXT:    vbit q11, q0, q1
+; CHECK-NEXT:    vld1.64 {d2, d3}, [r0:128]
 ; CHECK-NEXT:    subs r2, r6, r2
 ; CHECK-NEXT:    sbcs r2, r7, r5
 ; CHECK-NEXT:    vmov r6, r7, d24
@@ -356,6 +359,11 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    mvnne r2, #0
 ; CHECK-NEXT:    vdup.32 d4, r2
 ; CHECK-NEXT:    vmov r2, r5, d21
+; CHECK-NEXT:    vbit q13, q12, q2
+; CHECK-NEXT:    vld1.64 {d24, d25}, [lr:128]
+; CHECK-NEXT:    mov lr, #0
+; CHECK-NEXT:    vld1.64 {d4, d5}, [r1:128]!
+; CHECK-NEXT:    vld1.64 {d0, d1}, [r1:128]
 ; CHECK-NEXT:    subs r2, r6, r2
 ; CHECK-NEXT:    sbcs r2, r7, r5
 ; CHECK-NEXT:    vmov r6, r7, d18
@@ -367,6 +375,7 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vmov r2, r5, d20
 ; CHECK-NEXT:    subs r2, r6, r2
 ; CHECK-NEXT:    sbcs r2, r7, r5
+; CHECK-NEXT:    vmov r6, r5, d25
 ; CHECK-NEXT:    mov r2, #0
 ; CHECK-NEXT:    movlt r2, #1
 ; CHECK-NEXT:    cmp r2, #0
@@ -375,16 +384,7 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    vbif q9, q10, q15
 ; CHECK-NEXT:    vld1.64 {d30, d31}, [r8:128]!
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r8:128]
-; CHECK-NEXT:    vbit q13, q12, q2
-; CHECK-NEXT:    vld1.64 {d24, d25}, [lr:128]
 ; CHECK-NEXT:    vmov r2, r7, d21
-; CHECK-NEXT:    vbit q11, q0, q1
-; CHECK-NEXT:    mov lr, #0
-; CHECK-NEXT:    vmov r6, r5, d25
-; CHECK-NEXT:    vld1.64 {d4, d5}, [r1:128]!
-; CHECK-NEXT:    vld1.64 {d6, d7}, [r0:128]!
-; CHECK-NEXT:    vld1.64 {d0, d1}, [r1:128]
-; CHECK-NEXT:    vld1.64 {d2, d3}, [r0:128]
 ; CHECK-NEXT:    subs r1, r6, r2
 ; CHECK-NEXT:    vmov r0, r6, d2
 ; CHECK-NEXT:    sbcs r1, r5, r7
@@ -455,15 +455,15 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storea
 ; CHECK-NEXT:    movlt r12, #1
 ; CHECK-NEXT:    cmp r12, #0
 ; CHECK-NEXT:    vbsl q8, q14, q15
-; CHECK-NEXT:    vdup.32 d29, lr
-; CHECK-NEXT:    vorr q15, q3, q3
-; CHECK-NEXT:    mvnne r12, #0
-; CHECK-NEXT:    vdup.32 d28, r12
 ; CHECK-NEXT:    add r0, r3, #64
+; CHECK-NEXT:    vorr q15, q3, q3
+; CHECK-NEXT:    vdup.32 d29, lr
+; CHECK-NEXT:    mvnne r12, #0
+; CHECK-NEXT:    vst1.64 {d18, d19}, [r0:128]!
 ; CHECK-NEXT:    vbsl q15, q1, q0
+; CHECK-NEXT:    vdup.32 d28, r12
 ; CHECK-NEXT:    vst1.64 {d26, d27}, [r1:128]!
 ; CHECK-NEXT:    vbit q10, q12, q14
-; CHECK-NEXT:    vst1.64 {d18, d19}, [r0:128]!
 ; CHECK-NEXT:    vst1.64 {d22, d23}, [r0:128]!
 ; CHECK-NEXT:    vst1.64 {d4, d5}, [r1:128]!
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]!
diff --git a/llvm/test/CodeGen/ARM/vtrn.ll b/llvm/test/CodeGen/ARM/vtrn.ll
index 63774694f8a9..b3bc225d70b0 100644
--- a/llvm/test/CodeGen/ARM/vtrn.ll
+++ b/llvm/test/CodeGen/ARM/vtrn.ll
@@ -456,6 +456,7 @@ define void @test_15xi16(ptr %next.gep, ptr %next.gep13) {
 ; CHECK-NEXT:    vld1.16 {d18}, [r2]!
 ; CHECK-NEXT:    vld1.16 {d20, d21}, [r3]!
 ; CHECK-NEXT:    ldr r2, [r2]
+; CHECK-NEXT:    vtrn.16 q8, q10
 ; CHECK-NEXT:    vld1.16 {d22}, [r3]!
 ; CHECK-NEXT:    vmov.16 d19[0], r2
 ; CHECK-NEXT:    ldr r3, [r3]
@@ -463,7 +464,6 @@ define void @test_15xi16(ptr %next.gep, ptr %next.gep13) {
 ; CHECK-NEXT:    add r0, r0, #34
 ; CHECK-NEXT:    vmov.16 d19[1], r3
 ; CHECK-NEXT:    vld1.16 {d19[2]}, [r2:16]
-; CHECK-NEXT:    vtrn.16 q8, q10
 ; CHECK-NEXT:    vld1.16 {d19[3]}, [r0:16]
 ; CHECK-NEXT:    vtrn.16 d18, d22
 ; CHECK-NEXT:    vst1.16 {d16, d17}, [r1]!
diff --git a/llvm/test/CodeGen/Thumb/pr35836.ll b/llvm/test/CodeGen/Thumb/pr35836.ll
index 17378a19a9d6..44b4da5f453a 100644
--- a/llvm/test/CodeGen/Thumb/pr35836.ll
+++ b/llvm/test/CodeGen/Thumb/pr35836.ll
@@ -10,47 +10,22 @@ define void @f(i32,i32,i32,i32,ptr %x4p, ptr %x5p, ptr %x6p) {
 ; CHECK:       @ %bb.0: @ %if.end
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
-; CHECK-NEXT:    .pad #24
-; CHECK-NEXT:    sub sp, #24
-; CHECK-NEXT:    add r4, sp, #8
-; CHECK-NEXT:    stm r4!, {r0, r1, r2, r3} @ 16-byte Folded Spill
+; CHECK-NEXT:    .pad #4
+; CHECK-NEXT:    sub sp, #4
+; CHECK-NEXT:    str r3, [sp] @ 4-byte Spill
 ; CHECK-NEXT:    movs r5, #0
-; CHECK-NEXT:    ldr r0, [sp, #52]
-; CHECK-NEXT:    str r0, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT:    ldr r0, [sp, #48]
-; CHECK-NEXT:    str r0, [sp] @ 4-byte Spill
-; CHECK-NEXT:    ldr r7, [sp, #44]
+; CHECK-NEXT:    ldr r3, [sp, #32]
 ; CHECK-NEXT:  .LBB0_1: @ %while.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT:    ldr r1, [sp, #16] @ 4-byte Reload
-; CHECK-NEXT:    adds r3, r0, r1
-; CHECK-NEXT:    mov r12, r5
-; CHECK-NEXT:    mov r1, r12
-; CHECK-NEXT:    adcs r1, r5
-; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT:    ldr r2, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT:    adds r2, r0, r2
+; CHECK-NEXT:    ldr r4, [sp] @ 4-byte Reload
+; CHECK-NEXT:    adds r6, r4, r2
+; CHECK-NEXT:    adds r7, r1, r0
 ; CHECK-NEXT:    mov r12, r5
 ; CHECK-NEXT:    mov r4, r12
 ; CHECK-NEXT:    adcs r4, r5
-; CHECK-NEXT:    adds r0, r2, r5
-; CHECK-NEXT:    mov r12, r3
-; CHECK-NEXT:    mov r0, r12
-; CHECK-NEXT:    adcs r0, r4
-; CHECK-NEXT:    ldr r6, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT:    str r0, [r6]
-; CHECK-NEXT:    ldr r0, [r7]
-; CHECK-NEXT:    ldr r6, [sp] @ 4-byte Reload
-; CHECK-NEXT:    ldr r6, [r6]
-; CHECK-NEXT:    adds r0, r6, r0
-; CHECK-NEXT:    mov r12, r5
-; CHECK-NEXT:    mov r6, r12
-; CHECK-NEXT:    adcs r6, r5
-; CHECK-NEXT:    adds r2, r2, r5
-; CHECK-NEXT:    adcs r4, r3
-; CHECK-NEXT:    adcs r0, r1
-; CHECK-NEXT:    adcs r6, r5
+; CHECK-NEXT:    adds r7, r7, r5
+; CHECK-NEXT:    adcs r4, r6
+; CHECK-NEXT:    str r4, [r3]
 ; CHECK-NEXT:    b .LBB0_1
 if.end:
   br label %while.body
diff --git a/llvm/test/CodeGen/Thumb/pr35836_2.ll b/llvm/test/CodeGen/Thumb/pr35836_2.ll
index 0f21e8bc7820..9eb892425f03 100644
--- a/llvm/test/CodeGen/Thumb/pr35836_2.ll
+++ b/llvm/test/CodeGen/Thumb/pr35836_2.ll
@@ -10,77 +10,83 @@ define i128 @a(ptr nocapture readonly %z) {
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
-; CHECK-NEXT:    .pad #20
-; CHECK-NEXT:    sub sp, #20
+; CHECK-NEXT:    .pad #28
+; CHECK-NEXT:    sub sp, #28
 ; CHECK-NEXT:    ldr r1, [r0, #32]
-; CHECK-NEXT:    str r1, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT:    str r1, [sp, #16] @ 4-byte Spill
 ; CHECK-NEXT:    ldr r1, [r0, #36]
-; CHECK-NEXT:    str r1, [sp, #16] @ 4-byte Spill
-; CHECK-NEXT:    ldr r2, [r0, #40]
+; CHECK-NEXT:    str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT:    ldr r1, [r0, #40]
+; CHECK-NEXT:    str r1, [sp, #24] @ 4-byte Spill
 ; CHECK-NEXT:    ldr r3, [r0, #44]
-; CHECK-NEXT:    ldr r4, [r0, #12]
-; CHECK-NEXT:    ldm r0!, {r6, r7}
-; CHECK-NEXT:    ldr r1, [r0]
-; CHECK-NEXT:    subs r0, #8
-; CHECK-NEXT:    adds r5, r1, r6
-; CHECK-NEXT:    mov r5, r4
-; CHECK-NEXT:    adcs r5, r7
-; CHECK-NEXT:    ldr r5, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT:    adcs r2, r5
-; CHECK-NEXT:    ldr r5, [sp, #16] @ 4-byte Reload
-; CHECK-NEXT:    adcs r3, r5
-; CHECK-NEXT:    adds r6, r1, r6
-; CHECK-NEXT:    adcs r4, r7
-; CHECK-NEXT:    ldr r1, [r0, #20]
-; CHECK-NEXT:    str r1, [sp, #16] @ 4-byte Spill
-; CHECK-NEXT:    ldr r5, [r0, #28]
-; CHECK-NEXT:    ldr r1, [r0, #16]
+; CHECK-NEXT:    ldr r6, [r0]
+; CHECK-NEXT:    str r6, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT:    adds r5, r0, #4
+; CHECK-NEXT:    ldm r5, {r1, r2, r4, r5}
+; CHECK-NEXT:    str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT:    ldr r5, [r0, #20]
+; CHECK-NEXT:    str r5, [sp, #12] @ 4-byte Spill
 ; CHECK-NEXT:    ldr r7, [r0, #24]
-; CHECK-NEXT:    adcs r7, r1
+; CHECK-NEXT:    ldr r5, [r0, #28]
+; CHECK-NEXT:    adds r0, r2, r6
+; CHECK-NEXT:    mov r0, r4
+; CHECK-NEXT:    adcs r0, r1
 ; CHECK-NEXT:    ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    ldr r6, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT:    adcs r6, r0
+; CHECK-NEXT:    str r6, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT:    adcs r3, r0
+; CHECK-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT:    adds r6, r2, r0
+; CHECK-NEXT:    adcs r4, r1
+; CHECK-NEXT:    ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT:    adcs r7, r0
+; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    adcs r5, r0
 ; CHECK-NEXT:    mov r0, r6
 ; CHECK-NEXT:    mov r1, r4
+; CHECK-NEXT:    ldr r2, [sp, #24] @ 4-byte Reload
 ; CHECK-NEXT:    bl __aeabi_lmul
-; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT:    str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT:    str r1, [sp, #24] @ 4-byte Spill
 ; CHECK-NEXT:    mov r0, r7
 ; CHECK-NEXT:    mov r1, r5
 ; CHECK-NEXT:    mov r2, r6
 ; CHECK-NEXT:    mov r3, r4
 ; CHECK-NEXT:    bl __aeabi_lmul
-; CHECK-NEXT:    ldr r2, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT:    ldr r2, [sp, #20] @ 4-byte Reload
 ; CHECK-NEXT:    adds r0, r0, r2
-; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT:    ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT:    ldr r0, [sp, #24] @ 4-byte Reload
 ; CHECK-NEXT:    adcs r0, r1
-; CHECK-NEXT:    str r0, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT:    str r0, [sp, #24] @ 4-byte Spill
 ; CHECK-NEXT:    movs r7, #0
 ; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    mov r1, r7
 ; CHECK-NEXT:    mov r2, r6
 ; CHECK-NEXT:    mov r3, r7
 ; CHECK-NEXT:    bl __aeabi_lmul
-; CHECK-NEXT:    str r0, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
 ; CHECK-NEXT:    mov r5, r1
 ; CHECK-NEXT:    mov r0, r6
 ; CHECK-NEXT:    mov r1, r7
 ; CHECK-NEXT:    mov r2, r6
 ; CHECK-NEXT:    mov r3, r7
 ; CHECK-NEXT:    bl __aeabi_lmul
-; CHECK-NEXT:    str r0, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT:    str r0, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    adds r0, r0, r1
-; CHECK-NEXT:    str r0, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
 ; CHECK-NEXT:    adcs r5, r7
 ; CHECK-NEXT:    mov r0, r6
 ; CHECK-NEXT:    mov r1, r7
 ; CHECK-NEXT:    mov r2, r4
 ; CHECK-NEXT:    mov r3, r7
 ; CHECK-NEXT:    bl __aeabi_lmul
-; CHECK-NEXT:    ldr r2, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT:    ldr r2, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    adds r0, r0, r2
-; CHECK-NEXT:    str r0, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
 ; CHECK-NEXT:    adcs r1, r7
 ; CHECK-NEXT:    adds r6, r5, r1
 ; CHECK-NEXT:    mov r5, r7
@@ -92,14 +98,14 @@ define i128 @a(ptr nocapture readonly %z) {
 ; CHECK-NEXT:    bl __aeabi_lmul
 ; CHECK-NEXT:    adds r0, r0, r6
 ; CHECK-NEXT:    adcs r5, r1
-; CHECK-NEXT:    ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT:    ldr r1, [sp, #20] @ 4-byte Reload
 ; CHECK-NEXT:    adds r2, r0, r1
-; CHECK-NEXT:    ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    ldr r0, [sp, #24] @ 4-byte Reload
 ; CHECK-NEXT:    adcs r5, r0
-; CHECK-NEXT:    ldr r0, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT:    ldr r1, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT:    ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    ldr r1, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    mov r3, r5
-; CHECK-NEXT:    add sp, #20
+; CHECK-NEXT:    add sp, #28
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 entry:
   %0 = load i64, ptr %z, align 4
diff --git a/llvm/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
index 94080c02ded8..8550f39e38fa 100644
--- a/llvm/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
@@ -124,10 +124,10 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; THUMBV6-NEXT:    orrs r7, r1
 ; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
 ; THUMBV6-NEXT:    adds r0, r0, r1
-; THUMBV6-NEXT:    str r0, [sp, #32] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #40] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r4, r0
-; THUMBV6-NEXT:    str r4, [sp, #40] @ 4-byte Spill
+; THUMBV6-NEXT:    str r4, [sp, #32] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r0, [sp, #44] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r1, r5
 ; THUMBV6-NEXT:    ldr r2, [sp, #56] @ 4-byte Reload
@@ -156,12 +156,12 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    adds r0, r0, r4
 ; THUMBV6-NEXT:    adcs r1, r6
-; THUMBV6-NEXT:    ldr r2, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r2, [sp, #40] @ 4-byte Reload
 ; THUMBV6-NEXT:    adds r0, r0, r2
+; THUMBV6-NEXT:    ldr r2, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    adcs r1, r2
 ; THUMBV6-NEXT:    ldr r2, [sp, #48] @ 4-byte Reload
 ; THUMBV6-NEXT:    str r0, [r2, #8]
-; THUMBV6-NEXT:    ldr r0, [sp, #40] @ 4-byte Reload
-; THUMBV6-NEXT:    adcs r1, r0
 ; THUMBV6-NEXT:    str r1, [r2, #12]
 ; THUMBV6-NEXT:    adcs r5, r5
 ; THUMBV6-NEXT:    orrs r5, r7
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
index 9c2ae8fb2aa5..8a016c1f9598 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
@@ -1329,7 +1329,7 @@
 # CHECK-NEXT:  1      1     0.50                        rsb	r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        rsb	r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        rsb	r7, r8, #40, #2
-# CHECK-NEXT:  1      1     0.50                  U     rsb	r4, r5, r6
+# CHECK-NEXT:  1      1     0.50                        rsb	r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsblo	r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, lsr #5
@@ -1341,7 +1341,7 @@
 # CHECK-NEXT:  1      2     0.50                        rsble	r6, r7, r8, ror r9
 # CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        rsb	r5, r5, #61440
-# CHECK-NEXT:  1      1     0.50                  U     rsb	r4, r4, r5
+# CHECK-NEXT:  1      1     0.50                        rsb	r4, r4, r5
 # CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsbne	r4, r4, r5, lsr #5
@@ -1416,8 +1416,8 @@
 # CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, ror r9
-# CHECK-NEXT:  1      1     0.50                  U     sbfx	r4, r5, #16, #1
-# CHECK-NEXT:  1      1     0.50                  U     sbfxgt	r4, r5, #16, #16
+# CHECK-NEXT:  1      1     0.50                        sbfx	r4, r5, #16, #1
+# CHECK-NEXT:  1      1     0.50                        sbfxgt	r4, r5, #16, #16
 # CHECK-NEXT:  1      1     0.50    *                   sel	r9, r2, r1
 # CHECK-NEXT:  1      2     0.50    *                   selne	r9, r2, r1
 # CHECK-NEXT:  0      0     0.00                  U     setend	be
@@ -1478,9 +1478,9 @@
 # CHECK-NEXT:  1      3     1.00                        smmlar	r4, r3, r2, r1
 # CHECK-NEXT:  1      3     1.00                        smmlalo	r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmlarhs	r4, r3, r2, r1
-# CHECK-NEXT:  1      3     1.00                  U     smmls	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmls	r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmlsr	r4, r3, r2, r1
-# CHECK-NEXT:  1      3     1.00                  U     smmlslo	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmlslo	r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmlsrhs	r4, r3, r2, r1
 # CHECK-NEXT:  1      3     1.00                        smmul	r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmulr	r3, r2, r1
@@ -1644,8 +1644,8 @@
 # CHECK-NEXT:  2      4     1.00    *      *      U     uadd8le	r1, r2, r3
 # CHECK-NEXT:  2      3     1.00    *      *      U     uasx	r9, r12, r0
 # CHECK-NEXT:  2      5     1.00    *      *      U     uasxeq	r9, r12, r0
-# CHECK-NEXT:  1      1     0.50                  U     ubfx	r4, r5, #16, #1
-# CHECK-NEXT:  1      1     0.50                  U     ubfxgt	r4, r5, #16, #16
+# CHECK-NEXT:  1      1     0.50                        ubfx	r4, r5, #16, #1
+# CHECK-NEXT:  1      1     0.50                        ubfxgt	r4, r5, #16, #16
 # CHECK-NEXT:  1      2     1.00                        uhadd16	r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd16gt	r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd8	r4, r8, r2
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-neon-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-neon-instructions.s
index 1198a90dc7c0..d9883de6bcf1 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-neon-instructions.s
@@ -1265,12 +1265,12 @@
 # CHECK-NEXT:  1      3     0.50                        vorn	q8, q8, q9
 # CHECK-NEXT:  1      3     0.50                        vmvn	d16, d16
 # CHECK-NEXT:  1      3     0.50                        vmvn	q8, q8
-# CHECK-NEXT:  1      3     0.50                  U     vbsl	d18, d17, d16
-# CHECK-NEXT:  1      3     0.50                  U     vbsl	q8, q10, q9
-# CHECK-NEXT:  1      3     0.50                  U     vbit	d18, d17, d16
-# CHECK-NEXT:  1      3     0.50                  U     vbit	q8, q10, q9
-# CHECK-NEXT:  1      3     0.50                  U     vbif	d18, d17, d16
-# CHECK-NEXT:  1      3     0.50                  U     vbif	q8, q10, q9
+# CHECK-NEXT:  1      3     0.50                        vbsl	d18, d17, d16
+# CHECK-NEXT:  1      3     0.50                        vbsl	q8, q10, q9
+# CHECK-NEXT:  1      3     0.50                        vbit	d18, d17, d16
+# CHECK-NEXT:  1      3     0.50                        vbit	q8, q10, q9
+# CHECK-NEXT:  1      3     0.50                        vbif	d18, d17, d16
+# CHECK-NEXT:  1      3     0.50                        vbif	q8, q10, q9
 # CHECK-NEXT:  1      3     0.50                        vceq.i8	d16, d16, d17
 # CHECK-NEXT:  1      3     0.50                        vceq.i16	d16, d16, d17
 # CHECK-NEXT:  1      3     0.50                        vceq.i32	d16, d16, d17
@@ -1821,22 +1821,22 @@
 # CHECK-NEXT:  1      3     0.50                        vext.8	q8, q9, q8, #7
 # CHECK-NEXT:  1      3     0.50                        vext.16	d16, d17, d16, #3
 # CHECK-NEXT:  1      3     0.50                        vext.32	q8, q9, q8, #3
-# CHECK-NEXT:  2      3     1.00                  U     vtrn.8	d17, d16
-# CHECK-NEXT:  2      3     1.00                  U     vtrn.16	d17, d16
-# CHECK-NEXT:  2      3     1.00                  U     vtrn.32	d17, d16
-# CHECK-NEXT:  2      3     1.00                  U     vtrn.8	q9, q8
-# CHECK-NEXT:  2      3     1.00                  U     vtrn.16	q9, q8
-# CHECK-NEXT:  2      3     1.00                  U     vtrn.32	q9, q8
-# CHECK-NEXT:  2      3     1.00                  U     vuzp.8	d17, d16
-# CHECK-NEXT:  2      3     1.00                  U     vuzp.16	d17, d16
-# CHECK-NEXT:  2      6     1.00                  U     vuzp.8	q9, q8
-# CHECK-NEXT:  2      6     1.00                  U     vuzp.16	q9, q8
-# CHECK-NEXT:  2      6     1.00                  U     vuzp.32	q9, q8
-# CHECK-NEXT:  2      3     1.00                  U     vzip.8	d17, d16
-# CHECK-NEXT:  2      3     1.00                  U     vzip.16	d17, d16
-# CHECK-NEXT:  2      6     1.00                  U     vzip.8	q9, q8
-# CHECK-NEXT:  2      6     1.00                  U     vzip.16	q9, q8
-# CHECK-NEXT:  2      6     1.00                  U     vzip.32	q9, q8
+# CHECK-NEXT:  2      3     1.00                        vtrn.8	d17, d16
+# CHECK-NEXT:  2      3     1.00                        vtrn.16	d17, d16
+# CHECK-NEXT:  2      3     1.00                        vtrn.32	d17, d16
+# CHECK-NEXT:  2      3     1.00                        vtrn.8	q9, q8
+# CHECK-NEXT:  2      3     1.00                        vtrn.16	q9, q8
+# CHECK-NEXT:  2      3     1.00                        vtrn.32	q9, q8
+# CHECK-NEXT:  2      3     1.00                        vuzp.8	d17, d16
+# CHECK-NEXT:  2      3     1.00                        vuzp.16	d17, d16
+# CHECK-NEXT:  2      6     1.00                        vuzp.8	q9, q8
+# CHECK-NEXT:  2      6     1.00                        vuzp.16	q9, q8
+# CHECK-NEXT:  2      6     1.00                        vuzp.32	q9, q8
+# CHECK-NEXT:  2      3     1.00                        vzip.8	d17, d16
+# CHECK-NEXT:  2      3     1.00                        vzip.16	d17, d16
+# CHECK-NEXT:  2      6     1.00                        vzip.8	q9, q8
+# CHECK-NEXT:  2      6     1.00                        vzip.16	q9, q8
+# CHECK-NEXT:  2      6     1.00                        vzip.32	q9, q8
 # CHECK-NEXT:  1      3     0.50                        vsub.i8	d16, d17, d16
 # CHECK-NEXT:  1      3     0.50                        vsub.i16	d16, d17, d16
 # CHECK-NEXT:  1      3     0.50                        vsub.i32	d16, d17, d16
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-thumb.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-thumb.s
index 44bf028dc122..f44aab3cd764 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-thumb.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-thumb.s
@@ -950,10 +950,10 @@
 # CHECK-NEXT:  1      2     1.00                        adds.w	r7, r3, r1, lsl #31
 # CHECK-NEXT:  1      2     1.00                        adds.w	r0, r3, r6, lsr #25
 # CHECK-NEXT:  1      2     1.00                        add.w	r4, r8, r1, ror #12
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r11, #-3270
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r11, #-826
+# CHECK-NEXT:  1      1     0.50                        adr.w	r11, #-3270
+# CHECK-NEXT:  1      1     0.50                        adr.w	r11, #-826
 # CHECK-NEXT:  1      1     0.50                        subw	r1, pc, #0
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r0, #1024
+# CHECK-NEXT:  1      1     0.50                        adr.w	r0, #1024
 # CHECK-NEXT:  1      1     0.50                        and	r2, r5, #1044480
 # CHECK-NEXT:  1      1     0.50                        ands	r3, r12, #15
 # CHECK-NEXT:  1      1     0.50                        and	r1, r1, #255
@@ -974,7 +974,7 @@
 # CHECK-NEXT:  1      1     0.50                        asr.w	r3, r4, r2
 # CHECK-NEXT:  1      1     0.50                        asr.w	r1, r1, r2
 # CHECK-NEXT:  1      2     1.00                        asrs.w	r3, r4, r8
-# CHECK-NEXT:  1      1     1.00                  U     bmi.w	#-183396
+# CHECK-NEXT:  1      1     1.00                        bmi.w	#-183396
 # CHECK-NEXT:  1      1     1.00                        b.w	#208962
 # CHECK-NEXT:  1      1     1.00                        b.w	#-16777216
 # CHECK-NEXT:  1      2     1.00                        bfc	r5, #3, #17
@@ -1002,9 +1002,9 @@
 # CHECK-NEXT:  2      3     1.00                  U     bxj	r5
 # CHECK-NEXT:  0      0     0.00                  U     it	ne
 # CHECK-NEXT:  2      3     1.00                  U     bxjne	r7
-# CHECK-NEXT:  1      1     1.00                  U     cbnz	r7, #6
-# CHECK-NEXT:  1      1     1.00                  U     cbnz	r7, #12
-# CHECK-NEXT:  1      1     1.00                  U     cbz	r4, #64
+# CHECK-NEXT:  1      1     1.00                        cbnz	r7, #6
+# CHECK-NEXT:  1      1     1.00                        cbnz	r7, #12
+# CHECK-NEXT:  1      1     1.00                        cbz	r4, #64
 # CHECK-NEXT:  1      1     1.00           *            strh	r6, [r5, #14]
 # CHECK-NEXT:  1      2     1.00                        asrs	r7, r2, #4
 # CHECK-NEXT:  1      1     1.00           *            strh	r6, [r7, #14]
@@ -1030,7 +1030,7 @@
 # CHECK-NEXT:  1      1     0.50                        adds	r7, r5, #4
 # CHECK-NEXT:  1      1     1.00           *            str	r6, [sp, #940]
 # CHECK-NEXT:  1      2     1.00                        asrs	r7, r5, #4
-# CHECK-NEXT:  1      1     0.50                  U     adr	r6, #940
+# CHECK-NEXT:  1      1     0.50                        adr	r6, #940
 # CHECK-NEXT:  1      2     1.00                        asrs	r7, r5, #4
 # CHECK-NEXT:  1      1     0.50                        cmp	r7, #182
 # CHECK-NEXT:  1      1     0.50                        cmp.w	r5, #65280
@@ -1450,8 +1450,8 @@
 # CHECK-NEXT:  1      1     0.50                        rsb.w	r2, r5, #1044480
 # CHECK-NEXT:  1      1     0.50                        rsbs.w	r3, r12, #15
 # CHECK-NEXT:  1      1     0.50                        rsb.w	r1, r1, #255
-# CHECK-NEXT:  1      1     0.50                  U     rsb	r4, r4, r8
-# CHECK-NEXT:  1      1     0.50                  U     rsb	r4, r9, r8
+# CHECK-NEXT:  1      1     0.50                        rsb	r4, r4, r8
+# CHECK-NEXT:  1      1     0.50                        rsb	r4, r9, r8
 # CHECK-NEXT:  1      2     1.00                        rsb	r1, r4, r8, asr #3
 # CHECK-NEXT:  1      2     1.00                        rsbs	r2, r1, r7, lsl #1
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd16	r3, r4, r8
@@ -1556,10 +1556,10 @@
 # CHECK-NEXT:  0      0     0.00                  U     ite	lo
 # CHECK-NEXT:  1      3     1.00                        smmlalo	r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmlarhs	r4, r3, r2, r1
-# CHECK-NEXT:  1      3     1.00                  U     smmls	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmls	r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmlsr	r4, r3, r2, r1
 # CHECK-NEXT:  0      0     0.00                  U     ite	lo
-# CHECK-NEXT:  1      3     1.00                  U     smmlslo	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmlslo	r1, r2, r3, r4
 # CHECK-NEXT:  1      3     1.00                        smmlsrhs	r4, r3, r2, r1
 # CHECK-NEXT:  1      2     1.00                        ssat	r9, #30, r0, asr #2
 # CHECK-NEXT:  2      1     1.00           *            str	r10, [r11], #0
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-int.s b/llvm/test/tools/llvm-mca/ARM/m4-int.s
index 1ede2c8ce53f..d2c765804818 100644
--- a/llvm/test/tools/llvm-mca/ARM/m4-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m4-int.s
@@ -455,18 +455,18 @@ yield
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00                        adc	r0, r1, #0
 # CHECK-NEXT:  1      1     1.00                        adcs	r0, r1, #0
-# CHECK-NEXT:  1      1     1.00                  U     adcs	r0, r1
+# CHECK-NEXT:  1      1     1.00                        adcs	r0, r1
 # CHECK-NEXT:  1      1     1.00                        adc.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        adcs.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        adc.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00                        adcs.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00                        add.w	r0, sp, #1
-# CHECK-NEXT:  1      1     1.00                  U     add.w	sp, sp, #1
+# CHECK-NEXT:  1      1     1.00                        add.w	sp, sp, #1
 # CHECK-NEXT:  1      1     1.00                        add.w	r0, sp, #1
 # CHECK-NEXT:  1      1     1.00                        adds.w	r0, sp, #1
 # CHECK-NEXT:  1      1     1.00                        addw	r0, sp, #1
-# CHECK-NEXT:  1      1     1.00                  U     add	r0, sp, r0
-# CHECK-NEXT:  1      1     1.00                  U     add	sp, r1
+# CHECK-NEXT:  1      1     1.00                        add	r0, sp, r0
+# CHECK-NEXT:  1      1     1.00                        add	sp, r1
 # CHECK-NEXT:  1      1     1.00                        add.w	r0, sp, r1
 # CHECK-NEXT:  1      1     1.00                        adds.w	r0, sp, r1
 # CHECK-NEXT:  1      1     1.00                        add.w	r0, sp, r1, lsl #1
@@ -482,9 +482,9 @@ yield
 # CHECK-NEXT:  1      1     1.00                        adds.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        add.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00                        adds.w	r0, r1, r2, lsl #1
-# CHECK-NEXT:  1      1     1.00                  U     adr.w	r0, #-6
-# CHECK-NEXT:  1      1     1.00                  U     adr.w	r8, #-6
-# CHECK-NEXT:  1      1     1.00                  U     adr.w	r0, #-6
+# CHECK-NEXT:  1      1     1.00                        adr.w	r0, #-6
+# CHECK-NEXT:  1      1     1.00                        adr.w	r8, #-6
+# CHECK-NEXT:  1      1     1.00                        adr.w	r0, #-6
 # CHECK-NEXT:  1      1     1.00                        and	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        ands	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        ands	r1, r0
@@ -517,7 +517,7 @@ yield
 # CHECK-NEXT:  1      1     1.00                        cmp	r0, #1
 # CHECK-NEXT:  1      1     1.00                        cmp.w	r0, #1
 # CHECK-NEXT:  1      1     1.00                        cmp	r0, r1
-# CHECK-NEXT:  1      1     1.00                  U     cmp	r0, r10
+# CHECK-NEXT:  1      1     1.00                        cmp	r0, r10
 # CHECK-NEXT:  1      1     1.00                        cmp.w	r0, r1
 # CHECK-NEXT:  1      1     1.00                        cmp.w	r0, r1, lsl #1
 # CHECK-NEXT:  1      1     1.00    *      *      U     dmb	sy
@@ -686,8 +686,8 @@ yield
 # CHECK-NEXT:  1      1     1.00                        rsbs	r0, r1, #0
 # CHECK-NEXT:  1      1     1.00                        rsb.w	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        rsbs.w	r0, r1, #1
-# CHECK-NEXT:  1      1     1.00                  U     rsb	r0, r1, r2
-# CHECK-NEXT:  1      1     1.00                  U     rsbs	r0, r1, r2
+# CHECK-NEXT:  1      1     1.00                        rsb	r0, r1, r2
+# CHECK-NEXT:  1      1     1.00                        rsbs	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        rsb	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00                        rsbs	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00    *      *      U     sadd16	r0, r1, r2
@@ -695,7 +695,7 @@ yield
 # CHECK-NEXT:  1      1     1.00    *      *      U     sasx	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        sbc	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        sbcs	r0, r1, #1
-# CHECK-NEXT:  1      1     1.00                  U     sbcs	r0, r1
+# CHECK-NEXT:  1      1     1.00                        sbcs	r0, r1
 # CHECK-NEXT:  1      1     1.00                        sbc.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        sbcs.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        sbc.w	r0, r1, r2, lsl #1
@@ -731,7 +731,7 @@ yield
 # CHECK-NEXT:  1      1     1.00                        smlsldx	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmla	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlar	r0, r1, r2, r3
-# CHECK-NEXT:  1      2     1.00                  U     smmls	r0, r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                        smmls	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlsr	r0, r1, r2, r3
 # CHECK-NEXT:  1      1     1.00                        smmul	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        smmulr	r0, r1, r2
@@ -795,7 +795,7 @@ yield
 # CHECK-NEXT:  1      1     1.00           *            strh.w	r0, [r1, r2, lsl #1]
 # CHECK-NEXT:  1      1     1.00           *            strht	r0, [r1, #1]
 # CHECK-NEXT:  1      1     1.00           *            strt	r0, [r1, #1]
-# CHECK-NEXT:  1      1     1.00                  U     sub	sp, #4
+# CHECK-NEXT:  1      1     1.00                        sub	sp, #4
 # CHECK-NEXT:  1      1     1.00                        sub.w	r0, sp, #1
 # CHECK-NEXT:  1      1     1.00                        subs.w	r0, sp, #1
 # CHECK-NEXT:  1      1     1.00                        subw	r0, sp, #1
diff --git a/llvm/test/tools/llvm-mca/ARM/m55-int.s b/llvm/test/tools/llvm-mca/ARM/m55-int.s
index 0810bf9aa320..4481b62b1969 100644
--- a/llvm/test/tools/llvm-mca/ARM/m55-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m55-int.s
@@ -487,18 +487,18 @@ yield
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00                        adc	r0, r1, #0
 # CHECK-NEXT:  1      1     1.00                        adcs	r0, r1, #0
-# CHECK-NEXT:  1      1     1.00                  U     adcs	r0, r1
+# CHECK-NEXT:  1      1     1.00                        adcs	r0, r1
 # CHECK-NEXT:  1      1     1.00                        adc.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        adcs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        adc.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        adcs.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, #1
-# CHECK-NEXT:  1      1     1.00                  U     add.w	sp, sp, #1
+# CHECK-NEXT:  1      1     1.00                        add.w	sp, sp, #1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        adds.w	r0, sp, #1
 # CHECK-NEXT:  1      1     1.00                        addw	r0, sp, #1
-# CHECK-NEXT:  1      1     1.00                  U     add	r0, sp, r0
-# CHECK-NEXT:  1      1     1.00                  U     add	sp, r1
+# CHECK-NEXT:  1      1     1.00                        add	r0, sp, r0
+# CHECK-NEXT:  1      1     1.00                        add	sp, r1
 # CHECK-NEXT:  1      1     1.00                        add.w	r0, sp, r1
 # CHECK-NEXT:  1      1     1.00                        adds.w	r0, sp, r1
 # CHECK-NEXT:  1      2     1.00                        add.w	r0, sp, r1, lsl #1
@@ -514,9 +514,9 @@ yield
 # CHECK-NEXT:  1      1     1.00                        adds.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        add.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        adds.w	r0, r1, r2, lsl #1
-# CHECK-NEXT:  1      1     1.00                  U     adr.w	r0, #-6
-# CHECK-NEXT:  1      1     1.00                  U     adr.w	r8, #-6
-# CHECK-NEXT:  1      1     1.00                  U     adr.w	r0, #-6
+# CHECK-NEXT:  1      1     1.00                        adr.w	r0, #-6
+# CHECK-NEXT:  1      1     1.00                        adr.w	r8, #-6
+# CHECK-NEXT:  1      1     1.00                        adr.w	r0, #-6
 # CHECK-NEXT:  1      1     1.00                        and	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        ands	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        ands	r1, r0
@@ -552,7 +552,7 @@ yield
 # CHECK-NEXT:  1      1     1.00                        cmp	r0, #1
 # CHECK-NEXT:  1      1     1.00                        cmp.w	r0, #1
 # CHECK-NEXT:  1      1     1.00                        cmp	r0, r1
-# CHECK-NEXT:  1      1     1.00                  U     cmp	r0, r10
+# CHECK-NEXT:  1      1     1.00                        cmp	r0, r10
 # CHECK-NEXT:  1      1     1.00                        cmp.w	r0, r1
 # CHECK-NEXT:  1      2     1.00                        cmp.w	r0, r1, lsl #1
 # CHECK-NEXT:  1      1     1.00                        csel	r1, r2, r3, eq
@@ -734,8 +734,8 @@ yield
 # CHECK-NEXT:  1      1     1.00                        rsbs	r0, r1, #0
 # CHECK-NEXT:  1      1     1.00                        rsb.w	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        rsbs.w	r0, r1, #1
-# CHECK-NEXT:  1      1     1.00                  U     rsb	r0, r1, r2
-# CHECK-NEXT:  1      1     1.00                  U     rsbs	r0, r1, r2
+# CHECK-NEXT:  1      1     1.00                        rsb	r0, r1, r2
+# CHECK-NEXT:  1      1     1.00                        rsbs	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        rsb	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        rsbs	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00    *      *      U     sadd16	r0, r1, r2
@@ -743,7 +743,7 @@ yield
 # CHECK-NEXT:  1      2     1.00    *      *      U     sasx	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        sbc	r0, r1, #1
 # CHECK-NEXT:  1      1     1.00                        sbcs	r0, r1, #1
-# CHECK-NEXT:  1      1     1.00                  U     sbcs	r0, r1
+# CHECK-NEXT:  1      1     1.00                        sbcs	r0, r1
 # CHECK-NEXT:  1      1     1.00                        sbc.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        sbcs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        sbc.w	r0, r1, r2, lsl #1
@@ -779,7 +779,7 @@ yield
 # CHECK-NEXT:  1      2     1.00                        smlsldx	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmla	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlar	r0, r1, r2, r3
-# CHECK-NEXT:  1      2     1.00                  U     smmls	r0, r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                        smmls	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlsr	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmul	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        smmulr	r0, r1, r2
@@ -855,7 +855,7 @@ yield
 # CHECK-NEXT:  1      1     1.00           *            strh.w	r0, [r1, r2, lsl #1]
 # CHECK-NEXT:  1      1     1.00           *            strht	r0, [r1, #1]
 # CHECK-NEXT:  1      1     1.00           *            strt	r0, [r1, #1]
-# CHECK-NEXT:  1      1     1.00                  U     sub	sp, #4
+# CHECK-NEXT:  1      1     1.00                        sub	sp, #4
 # CHECK-NEXT:  1      1     0.50                        sub.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        subs.w	r0, sp, #1
 # CHECK-NEXT:  1      1     1.00                        subw	r0, sp, #1
diff --git a/llvm/test/tools/llvm-mca/ARM/m7-int.s b/llvm/test/tools/llvm-mca/ARM/m7-int.s
index 9140b619a092..78cc679239f0 100644
--- a/llvm/test/tools/llvm-mca/ARM/m7-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m7-int.s
@@ -441,7 +441,7 @@ yield
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.50                        adc	r0, r1, #0
 # CHECK-NEXT:  1      1     0.50                        adcs	r0, r1, #0
-# CHECK-NEXT:  1      1     0.50                  U     adcs	r0, r1
+# CHECK-NEXT:  1      1     0.50                        adcs	r0, r1
 # CHECK-NEXT:  1      1     0.50                        adc.w	r0, r1, r2
 # CHECK-NEXT:  1      1     0.50                        adcs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        adc.w	r0, r1, r2, lsl #1
@@ -458,17 +458,17 @@ yield
 # CHECK-NEXT:  1      2     1.00                        add.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        adds.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, #1
-# CHECK-NEXT:  1      1     0.50                  U     add.w	sp, sp, #1
+# CHECK-NEXT:  1      1     0.50                        add.w	sp, sp, #1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        adds.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        addw	r0, sp, #1
-# CHECK-NEXT:  1      1     0.50                  U     add	r0, sp, r0
-# CHECK-NEXT:  1      1     0.50                  U     add	sp, r1
+# CHECK-NEXT:  1      1     0.50                        add	r0, sp, r0
+# CHECK-NEXT:  1      1     0.50                        add	sp, r1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, r1
 # CHECK-NEXT:  1      1     0.50                        adds.w	r0, sp, r1
 # CHECK-NEXT:  1      2     1.00                        add.w	r0, sp, r1, lsl #1
 # CHECK-NEXT:  1      2     1.00                        adds.w	r0, sp, r1, lsl #1
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r0, #-6
+# CHECK-NEXT:  1      1     0.50                        adr.w	r0, #-6
 # CHECK-NEXT:  1      1     0.50                        and	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        ands	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        ands	r1, r0
@@ -501,7 +501,7 @@ yield
 # CHECK-NEXT:  1      1     0.50                        cmp	r0, #1
 # CHECK-NEXT:  1      1     0.50                        cmp.w	r0, #1
 # CHECK-NEXT:  1      1     0.50                        cmp	r0, r1
-# CHECK-NEXT:  1      1     0.50                  U     cmp	r0, r10
+# CHECK-NEXT:  1      1     0.50                        cmp	r0, r10
 # CHECK-NEXT:  1      1     0.50                        cmp.w	r0, r1
 # CHECK-NEXT:  1      2     1.00                        cmp.w	r0, r1, lsl #1
 # CHECK-NEXT:  1      3     0.50    *      *      U     dmb	sy
@@ -664,8 +664,8 @@ yield
 # CHECK-NEXT:  1      1     0.50                        rsbs	r0, r1, #0
 # CHECK-NEXT:  1      1     0.50                        rsb.w	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        rsbs.w	r0, r1, #1
-# CHECK-NEXT:  1      1     0.50                  U     rsb	r0, r1, r2
-# CHECK-NEXT:  1      1     0.50                  U     rsbs	r0, r1, r2
+# CHECK-NEXT:  1      1     0.50                        rsb	r0, r1, r2
+# CHECK-NEXT:  1      1     0.50                        rsbs	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        rsb	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        rsbs	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00    *      *      U     sadd16	r0, r1, r2
@@ -673,7 +673,7 @@ yield
 # CHECK-NEXT:  1      1     1.00    *      *      U     sasx	r0, r1, r2
 # CHECK-NEXT:  1      1     0.50                        sbc	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        sbcs	r0, r1, #1
-# CHECK-NEXT:  1      1     0.50                  U     sbcs	r0, r1
+# CHECK-NEXT:  1      1     0.50                        sbcs	r0, r1
 # CHECK-NEXT:  1      1     0.50                        sbc.w	r0, r1, r2
 # CHECK-NEXT:  1      1     0.50                        sbcs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        sbc.w	r0, r1, r2, lsl #1
@@ -708,7 +708,7 @@ yield
 # CHECK-NEXT:  1      2     1.00                        smlsldx	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmla	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlar	r0, r1, r2, r3
-# CHECK-NEXT:  1      2     1.00                  U     smmls	r0, r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                        smmls	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlsr	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmul	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        smmulr	r0, r1, r2
@@ -781,7 +781,7 @@ yield
 # CHECK-NEXT:  1      1     0.50                        subs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        sub.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        subs.w	r0, r1, r2, lsl #1
-# CHECK-NEXT:  1      1     0.50                  U     sub	sp, #4
+# CHECK-NEXT:  1      1     0.50                        sub	sp, #4
 # CHECK-NEXT:  1      1     0.50                        sub.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        subs.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        subw	r0, sp, #1
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-int.s b/llvm/test/tools/llvm-mca/ARM/m85-int.s
index 4e49d6ecfedb..cb1f991371ea 100644
--- a/llvm/test/tools/llvm-mca/ARM/m85-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m85-int.s
@@ -509,18 +509,18 @@ yield.w
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.50                        adc	r0, r1, #0
 # CHECK-NEXT:  1      1     0.50                        adcs	r0, r1, #0
-# CHECK-NEXT:  1      1     0.50                  U     adcs	r0, r1
+# CHECK-NEXT:  1      1     0.50                        adcs	r0, r1
 # CHECK-NEXT:  1      2     1.00                        adc.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        adcs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        adc.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        adcs.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, #1
-# CHECK-NEXT:  1      1     0.50                  U     add.w	sp, sp, #1
+# CHECK-NEXT:  1      1     0.50                        add.w	sp, sp, #1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        adds.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        addw	r0, sp, #1
-# CHECK-NEXT:  1      1     0.50                  U     add	r0, sp, r0
-# CHECK-NEXT:  1      2     0.50                  U     add	sp, r1
+# CHECK-NEXT:  1      1     0.50                        add	r0, sp, r0
+# CHECK-NEXT:  1      2     0.50                        add	sp, r1
 # CHECK-NEXT:  1      1     0.50                        add.w	r0, sp, r1
 # CHECK-NEXT:  1      1     0.50                        adds.w	r0, sp, r1
 # CHECK-NEXT:  1      2     1.00                        add.w	r0, sp, r1, lsl #1
@@ -536,9 +536,9 @@ yield.w
 # CHECK-NEXT:  1      1     0.50                        adds.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        add.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        adds.w	r0, r1, r2, lsl #1
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r0, #-6
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r8, #-6
-# CHECK-NEXT:  1      1     0.50                  U     adr.w	r0, #-6
+# CHECK-NEXT:  1      1     0.50                        adr.w	r0, #-6
+# CHECK-NEXT:  1      1     0.50                        adr.w	r8, #-6
+# CHECK-NEXT:  1      1     0.50                        adr.w	r0, #-6
 # CHECK-NEXT:  1      1     0.50                        and	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        ands	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        ands	r1, r0
@@ -574,7 +574,7 @@ yield.w
 # CHECK-NEXT:  1      1     0.50                        cmp	r0, #1
 # CHECK-NEXT:  1      1     0.50                        cmp.w	r0, #1
 # CHECK-NEXT:  1      1     0.50                        cmp	r0, r1
-# CHECK-NEXT:  1      1     0.50                  U     cmp	r0, r10
+# CHECK-NEXT:  1      1     0.50                        cmp	r0, r10
 # CHECK-NEXT:  1      2     1.00                        cmp.w	r0, r1
 # CHECK-NEXT:  1      2     1.00                        cmp.w	r0, r1, lsl #1
 # CHECK-NEXT:  1      3     0.50    *      *      U     csdb
@@ -763,8 +763,8 @@ yield.w
 # CHECK-NEXT:  1      1     0.50                        rsbs	r0, r1, #0
 # CHECK-NEXT:  1      1     0.50                        rsb.w	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        rsbs.w	r0, r1, #1
-# CHECK-NEXT:  1      2     1.00                  U     rsb	r0, r1, r2
-# CHECK-NEXT:  1      2     1.00                  U     rsbs	r0, r1, r2
+# CHECK-NEXT:  1      2     1.00                        rsb	r0, r1, r2
+# CHECK-NEXT:  1      2     1.00                        rsbs	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        rsb	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      2     1.00                        rsbs	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00    *      *      U     sadd16	r0, r1, r2
@@ -772,7 +772,7 @@ yield.w
 # CHECK-NEXT:  1      1     1.00    *      *      U     sasx	r0, r1, r2
 # CHECK-NEXT:  1      1     0.50                        sbc	r0, r1, #1
 # CHECK-NEXT:  1      1     0.50                        sbcs	r0, r1, #1
-# CHECK-NEXT:  1      1     0.50                  U     sbcs	r0, r1
+# CHECK-NEXT:  1      1     0.50                        sbcs	r0, r1
 # CHECK-NEXT:  1      2     1.00                        sbc.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        sbcs.w	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        sbc.w	r0, r1, r2, lsl #1
@@ -808,7 +808,7 @@ yield.w
 # CHECK-NEXT:  1      2     1.00                        smlsldx	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmla	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlar	r0, r1, r2, r3
-# CHECK-NEXT:  1      2     1.00                  U     smmls	r0, r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                        smmls	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmlsr	r0, r1, r2, r3
 # CHECK-NEXT:  1      2     1.00                        smmul	r0, r1, r2
 # CHECK-NEXT:  1      2     1.00                        smmulr	r0, r1, r2
@@ -884,7 +884,7 @@ yield.w
 # CHECK-NEXT:  1      3     0.50           *            strh.w	r0, [r1, r2, lsl #1]
 # CHECK-NEXT:  1      3     0.50           *            strht	r0, [r1, #1]
 # CHECK-NEXT:  1      3     0.50           *            strt	r0, [r1, #1]
-# CHECK-NEXT:  1      2     0.50                  U     sub	sp, #4
+# CHECK-NEXT:  1      2     0.50                        sub	sp, #4
 # CHECK-NEXT:  1      1     0.50                        sub.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        subs.w	r0, sp, #1
 # CHECK-NEXT:  1      1     0.50                        subw	r0, sp, #1
diff --git a/llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s b/llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s
index fa3bbc061b8a..d68fffc92383 100644
--- a/llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s
+++ b/llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s
@@ -12,7 +12,7 @@ sub sp, #4
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      1     1.00                  U     sub	sp, #4
+# CHECK-NEXT:  1      1     1.00                        sub	sp, #4
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - M4Unit