From d7065e5df56054e71eef75b67463d4baa875c8fa Mon Sep 17 00:00:00 2001 From: Tobias Grosser Date: Mon, 24 Jul 2017 20:50:22 +0000 Subject: [PATCH] Move MemoryAccess::isStride* to isl++ llvm-svn: 308927 --- polly/include/polly/ScopInfo.h | 8 +-- polly/lib/Analysis/ScopInfo.cpp | 61 ++++++++++------------- polly/lib/CodeGen/BlockGenerators.cpp | 8 +-- polly/lib/Transform/ScheduleOptimizer.cpp | 6 +-- 4 files changed, 38 insertions(+), 45 deletions(-) diff --git a/polly/include/polly/ScopInfo.h b/polly/include/polly/ScopInfo.h index ac1154bcc9d8..ea7b09088e65 100644 --- a/polly/include/polly/ScopInfo.h +++ b/polly/include/polly/ScopInfo.h @@ -926,7 +926,7 @@ public: /// Get the stride of this memory access in the specified Schedule. Schedule /// is a map from the statement to a schedule where the innermost dimension is /// the dimension of the innermost loop containing the statement. - __isl_give isl_set *getStride(__isl_take const isl_map *Schedule) const; + isl::set getStride(isl::map Schedule) const; /// Get the FortranArrayDescriptor corresponding to this memory access if /// it exists, and nullptr otherwise. @@ -935,19 +935,19 @@ public: /// Is the stride of the access equal to a certain width? Schedule is a map /// from the statement to a schedule where the innermost dimension is the /// dimension of the innermost loop containing the statement. - bool isStrideX(__isl_take const isl_map *Schedule, int StrideWidth) const; + bool isStrideX(isl::map Schedule, int StrideWidth) const; /// Is consecutive memory accessed for a given statement instance set? /// Schedule is a map from the statement to a schedule where the innermost /// dimension is the dimension of the innermost loop containing the /// statement. - bool isStrideOne(__isl_take const isl_map *Schedule) const; + bool isStrideOne(isl::map Schedule) const; /// Is always the same memory accessed for a given statement instance set? /// Schedule is a map from the statement to a schedule where the innermost /// dimension is the dimension of the innermost loop containing the /// statement. - bool isStrideZero(__isl_take const isl_map *Schedule) const; + bool isStrideZero(isl::map Schedule) const; /// Return the kind when this access was first detected. MemoryKind getOriginalKind() const { diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp index ac1abba6414f..7eff057d6bf2 100644 --- a/polly/lib/Analysis/ScopInfo.cpp +++ b/polly/lib/Analysis/ScopInfo.cpp @@ -1102,70 +1102,63 @@ isl::pw_aff MemoryAccess::getPwAff(const SCEV *E) { // set[i0, i1, ..., iX] -> set[o0, o1, ..., oX] // : i0 = o0, i1 = o1, ..., i(X-1) = o(X-1), iX < oX // -static isl_map *getEqualAndLarger(__isl_take isl_space *setDomain) { - isl_space *Space = isl_space_map_from_set(setDomain); - isl_map *Map = isl_map_universe(Space); - unsigned lastDimension = isl_map_dim(Map, isl_dim_in) - 1; +static isl::map getEqualAndLarger(isl::space SetDomain) { + isl::space Space = SetDomain.map_from_set(); + isl::map Map = isl::map::universe(Space); + unsigned lastDimension = Map.dim(isl::dim::in) - 1; // Set all but the last dimension to be equal for the input and output // // input[i0, i1, ..., iX] -> output[o0, o1, ..., oX] // : i0 = o0, i1 = o1, ..., i(X-1) = o(X-1) for (unsigned i = 0; i < lastDimension; ++i) - Map = isl_map_equate(Map, isl_dim_in, i, isl_dim_out, i); + Map = Map.equate(isl::dim::in, i, isl::dim::out, i); // Set the last dimension of the input to be strict smaller than the // last dimension of the output. // // input[?,?,?,...,iX] -> output[?,?,?,...,oX] : iX < oX - Map = isl_map_order_lt(Map, isl_dim_in, lastDimension, isl_dim_out, - lastDimension); + Map = Map.order_lt(isl::dim::in, lastDimension, isl::dim::out, lastDimension); return Map; } -__isl_give isl_set * -MemoryAccess::getStride(__isl_take const isl_map *Schedule) const { - isl_map *S = const_cast(Schedule); - isl_map *AccessRelation = getAccessRelation().release(); - isl_space *Space = isl_space_range(isl_map_get_space(S)); - isl_map *NextScatt = getEqualAndLarger(Space); +isl::set MemoryAccess::getStride(isl::map Schedule) const { + isl::map AccessRelation = getAccessRelation(); + isl::space Space = Schedule.get_space().range(); + isl::map NextScatt = getEqualAndLarger(Space); - S = isl_map_reverse(S); - NextScatt = isl_map_lexmin(NextScatt); + Schedule = Schedule.reverse(); + NextScatt = NextScatt.lexmin(); - NextScatt = isl_map_apply_range(NextScatt, isl_map_copy(S)); - NextScatt = isl_map_apply_range(NextScatt, isl_map_copy(AccessRelation)); - NextScatt = isl_map_apply_domain(NextScatt, S); - NextScatt = isl_map_apply_domain(NextScatt, AccessRelation); + NextScatt = NextScatt.apply_range(Schedule); + NextScatt = NextScatt.apply_range(AccessRelation); + NextScatt = NextScatt.apply_domain(Schedule); + NextScatt = NextScatt.apply_domain(AccessRelation); - isl_set *Deltas = isl_map_deltas(NextScatt); + isl::set Deltas = NextScatt.deltas(); return Deltas; } -bool MemoryAccess::isStrideX(__isl_take const isl_map *Schedule, - int StrideWidth) const { - isl_set *Stride, *StrideX; +bool MemoryAccess::isStrideX(isl::map Schedule, int StrideWidth) const { + isl::set Stride, StrideX; bool IsStrideX; Stride = getStride(Schedule); - StrideX = isl_set_universe(isl_set_get_space(Stride)); - for (unsigned i = 0; i < isl_set_dim(StrideX, isl_dim_set) - 1; i++) - StrideX = isl_set_fix_si(StrideX, isl_dim_set, i, 0); - StrideX = isl_set_fix_si(StrideX, isl_dim_set, - isl_set_dim(StrideX, isl_dim_set) - 1, StrideWidth); - IsStrideX = isl_set_is_subset(Stride, StrideX); - - isl_set_free(StrideX); - isl_set_free(Stride); + StrideX = isl::set::universe(Stride.get_space()); + for (unsigned i = 0; i < StrideX.dim(isl::dim::set) - 1; i++) + StrideX = StrideX.fix_si(isl::dim::set, i, 0); + StrideX = StrideX.fix_si(isl::dim::set, StrideX.dim(isl::dim::set) - 1, + StrideWidth); + IsStrideX = Stride.is_subset(StrideX); return IsStrideX; } -bool MemoryAccess::isStrideZero(__isl_take const isl_map *Schedule) const { +bool MemoryAccess::isStrideZero(isl::map Schedule) const { return isStrideX(Schedule, 0); } -bool MemoryAccess::isStrideOne(__isl_take const isl_map *Schedule) const { +bool MemoryAccess::isStrideOne(isl::map Schedule) const { return isStrideX(Schedule, 1); } diff --git a/polly/lib/CodeGen/BlockGenerators.cpp b/polly/lib/CodeGen/BlockGenerators.cpp index f21ef374a900..21aa508b3862 100644 --- a/polly/lib/CodeGen/BlockGenerators.cpp +++ b/polly/lib/CodeGen/BlockGenerators.cpp @@ -1018,11 +1018,11 @@ void VectorBlockGenerator::generateLoad( extractScalarValues(Load, VectorMap, ScalarMaps); Value *NewLoad; - if (Access.isStrideZero(isl_map_copy(Schedule))) + if (Access.isStrideZero(isl::manage(isl_map_copy(Schedule)))) NewLoad = generateStrideZeroLoad(Stmt, Load, ScalarMaps[0], NewAccesses); - else if (Access.isStrideOne(isl_map_copy(Schedule))) + else if (Access.isStrideOne(isl::manage(isl_map_copy(Schedule)))) NewLoad = generateStrideOneLoad(Stmt, Load, ScalarMaps, NewAccesses); - else if (Access.isStrideX(isl_map_copy(Schedule), -1)) + else if (Access.isStrideX(isl::manage(isl_map_copy(Schedule)), -1)) NewLoad = generateStrideOneLoad(Stmt, Load, ScalarMaps, NewAccesses, true); else NewLoad = generateUnknownStrideLoad(Stmt, Load, ScalarMaps, NewAccesses); @@ -1073,7 +1073,7 @@ void VectorBlockGenerator::copyStore( // the data location. extractScalarValues(Store, VectorMap, ScalarMaps); - if (Access.isStrideOne(isl_map_copy(Schedule))) { + if (Access.isStrideOne(isl::manage(isl_map_copy(Schedule)))) { Type *VectorPtrType = getVectorPtrTy(Pointer, getVectorWidth()); Value *NewPointer = generateLocationAccessed(Stmt, Store, ScalarMaps[0], VLTS[0], NewAccesses); diff --git a/polly/lib/Transform/ScheduleOptimizer.cpp b/polly/lib/Transform/ScheduleOptimizer.cpp index 93a7afe97166..371250b8319a 100644 --- a/polly/lib/Transform/ScheduleOptimizer.cpp +++ b/polly/lib/Transform/ScheduleOptimizer.cpp @@ -745,9 +745,9 @@ static bool containsOnlyMatrMultAcc(__isl_keep isl_map *PartialSchedule, auto *MemAccessPtr = *MemA; if (MemAccessPtr->isLatestArrayKind() && MemAccessPtr != MMI.WriteToC && !isMatMulNonScalarReadAccess(MemAccessPtr, MMI) && - !(MemAccessPtr->isStrideZero(isl_map_copy(MapI)) && - MemAccessPtr->isStrideZero(isl_map_copy(MapJ)) && - MemAccessPtr->isStrideZero(isl_map_copy(MapK)))) { + !(MemAccessPtr->isStrideZero(isl::manage(isl_map_copy(MapI))) && + MemAccessPtr->isStrideZero(isl::manage(isl_map_copy(MapJ))) && + MemAccessPtr->isStrideZero(isl::manage(isl_map_copy(MapK))))) { isl_map_free(MapI); isl_map_free(MapJ); isl_map_free(MapK);