[CodeGen] MachineVerifier to check early-clobber constraint (#151421)
Currently MachineVerifier is missing verifying early-clobber operand constraint. The only other machine operand constraint - TiedTo is already verified.
This commit is contained in:
Abhay Kanhere
GitHub
parent
d6fdfe0a27
commit
d998f92a00
@ -2584,6 +2584,14 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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report("Extra explicit operand on non-variadic instruction", MO, MONum);
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}
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// Verify earlyClobber def operand
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if (MCID.getOperandConstraint(MONum, MCOI::EARLY_CLOBBER) != -1) {
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if (!MO->isReg())
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report("Early clobber must be a register", MI);
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if (!MO->isEarlyClobber())
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report("Missing earlyClobber flag", MI);
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}
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switch (MO->getType()) {
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case MachineOperand::MO_Register: {
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// Verify debug flag on debug instructions. Check this first because reg0
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@ -116,8 +116,14 @@ bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
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if (!DstRC || DstRC != SrcRC)
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return false;
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return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
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RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
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if (!RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) ||
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!RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
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return false;
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const MCInstrDesc &MCID = MI.getDesc();
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if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
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MI.getOperand(0).setIsEarlyClobber(true);
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}
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return true;
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}
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bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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@ -602,6 +608,7 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32(
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I.setDesc(TII.get(Opc));
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I.addOperand(*MF, MachineOperand::CreateImm(0));
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I.addImplicitDefUseOperands(*MF);
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I.getOperand(0).setIsEarlyClobber(true);
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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@ -3787,6 +3794,10 @@ bool AMDGPUInstructionSelector::selectSMFMACIntrin(MachineInstr &MI) const {
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MI.removeOperand(1); // Intrinsic ID
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MI.addOperand(VDst_In); // Readd VDst_In to the end
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MI.addImplicitDefUseOperands(*MI.getParent()->getParent());
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const MCInstrDesc &MCID = MI.getDesc();
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if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
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MI.getOperand(0).setIsEarlyClobber(true);
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}
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return true;
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}
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@ -27,11 +27,11 @@ define amdgpu_kernel void @set_inactive_imm_poison(ptr addrspace(1) %out) {
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GCN-NEXT: v_mov_b32_e32 v0, 1
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; GCN-NEXT: v_mov_b32_e32 v0, v0
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; GCN-NEXT: v_mov_b32_e32 v1, v0
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 1, i32 poison) #0
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%tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0)
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@ -68,12 +68,12 @@ define amdgpu_kernel void @set_inactive_imm_poison_64(ptr addrspace(1) %out) {
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GCN-NEXT: v_mov_b32_e32 v0, 1
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v0, v0
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; GCN-NEXT: v_mov_b32_e32 v1, v1
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; GCN-NEXT: v_mov_b32_e32 v2, v0
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; GCN-NEXT: v_mov_b32_e32 v3, v1
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: buffer_store_dwordx2 v[2:3], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tmp.0 = call i64 @llvm.amdgcn.set.inactive.i64(i64 1, i64 poison) #0
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%tmp = call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp.0)
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@ -165,10 +165,10 @@ define amdgpu_kernel void @v_mul_i64_zext_src0_src1(ptr addrspace(1) %out, ptr a
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
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; GFX10-NEXT: global_load_dword v2, v0, s[6:7]
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; GFX10-NEXT: global_load_dword v2, v0, s[2:3]
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; GFX10-NEXT: global_load_dword v3, v0, s[6:7]
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v1, v2, 0
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v2, v3, 0
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; GFX10-NEXT: v_mov_b32_e32 v2, 0
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; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX10-NEXT: s_endpgm
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@ -179,15 +179,15 @@ define amdgpu_kernel void @v_mul_i64_zext_src0_src1(ptr addrspace(1) %out, ptr a
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX11-NEXT: global_load_b32 v0, v0, s[4:5]
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; GFX11-NEXT: global_load_b32 v2, v0, s[2:3]
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; GFX11-NEXT: global_load_b32 v3, v0, s[4:5]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v1, v0, 0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v3, 0
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -2407,51 +2407,52 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
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; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
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; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v30, v31, 0
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; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v30, v18, 0
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; GISEL-NEXT: v_mul_lo_u32 v24, v30, v19
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; GISEL-NEXT: v_mul_lo_u32 v25, v29, v18
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; GISEL-NEXT: v_mul_lo_u32 v27, v30, v19
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; GISEL-NEXT: v_mul_lo_u32 v36, v29, v18
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; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v35, v20, 0
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v35, v2, 0
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; GISEL-NEXT: v_mul_lo_u32 v26, v35, v3
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; GISEL-NEXT: v_mul_lo_u32 v27, v34, v2
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; GISEL-NEXT: v_mul_lo_u32 v37, v35, v3
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; GISEL-NEXT: v_mul_lo_u32 v38, v34, v2
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; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v29, v32, v[14:15]
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; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v34, v21, v[22:23]
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; GISEL-NEXT: v_mov_b32_e32 v22, v19
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; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v31, v[2:3]
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; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v4, v20, v[14:15]
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; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v30, v32, v[1:2]
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; GISEL-NEXT: v_mov_b32_e32 v23, v14
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v35, v21, v[22:23]
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; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[6:7], v29, v31, v[1:2]
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; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], v3, v24, s[6:7]
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[6:7], v34, v20, v[22:23]
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; GISEL-NEXT: v_addc_u32_e64 v14, s[6:7], v15, v26, s[6:7]
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; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v25, vcc
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; GISEL-NEXT: v_mad_u64_u32 v[23:24], s[4:5], v10, v31, v[2:3]
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; GISEL-NEXT: v_mad_u64_u32 v[25:26], s[4:5], v4, v20, v[14:15]
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; GISEL-NEXT: v_mov_b32_e32 v2, v23
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; GISEL-NEXT: v_mad_u64_u32 v[14:15], vcc, v30, v32, v[1:2]
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; GISEL-NEXT: v_mov_b32_e32 v23, v25
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; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v35, v21, v[22:23]
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[6:7], v29, v31, v[14:15]
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; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], v24, v27, s[6:7]
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; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[6:7], v34, v20, v[1:2]
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; GISEL-NEXT: v_addc_u32_e64 v2, s[6:7], v26, v37, s[6:7]
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; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v3, v36, vcc
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; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v16, v0
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; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v17, v1, vcc
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; GISEL-NEXT: v_xor_b32_e32 v15, v0, v28
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; GISEL-NEXT: v_addc_u32_e64 v0, s[4:5], v14, v27, s[4:5]
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; GISEL-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v18
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; GISEL-NEXT: v_subb_u32_e64 v14, s[4:5], v13, v22, s[4:5]
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; GISEL-NEXT: v_xor_b32_e32 v16, v12, v33
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; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v10, v32, v[3:4]
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; GISEL-NEXT: v_xor_b32_e32 v1, v1, v28
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; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v4, v21, v[0:1]
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; GISEL-NEXT: v_xor_b32_e32 v14, v14, v33
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; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v11, v31, v[12:13]
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; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], v15, v28
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; GISEL-NEXT: v_subb_u32_e32 v16, vcc, v17, v22, vcc
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; GISEL-NEXT: v_xor_b32_e32 v19, v0, v28
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; GISEL-NEXT: v_addc_u32_e64 v0, s[4:5], v2, v38, s[4:5]
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; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v12, v18
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; GISEL-NEXT: v_subb_u32_e64 v14, s[4:5], v13, v14, s[4:5]
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; GISEL-NEXT: v_xor_b32_e32 v18, v2, v33
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; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v10, v32, v[1:2]
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; GISEL-NEXT: v_xor_b32_e32 v1, v16, v28
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; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v4, v21, v[0:1]
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; GISEL-NEXT: v_xor_b32_e32 v10, v14, v33
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; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v11, v31, v[2:3]
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; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], v19, v28
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; GISEL-NEXT: v_subb_u32_e64 v1, s[6:7], v1, v28, s[6:7]
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; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[8:9], v5, v20, v[3:4]
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; GISEL-NEXT: v_sub_i32_e64 v4, s[8:9], v16, v33
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; GISEL-NEXT: v_subb_u32_e64 v5, s[8:9], v14, v33, s[8:9]
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; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
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; GISEL-NEXT: v_subb_u32_e32 v8, vcc, v9, v10, vcc
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; GISEL-NEXT: v_xor_b32_e32 v2, v2, v28
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; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v23, s[4:5]
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; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc
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; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v5, v20, v[12:13]
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; GISEL-NEXT: v_sub_i32_e64 v4, s[8:9], v18, v33
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; GISEL-NEXT: v_subb_u32_e64 v5, s[8:9], v10, v33, s[8:9]
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; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v8, v23, vcc
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; GISEL-NEXT: v_subb_u32_e32 v8, vcc, v9, v16, vcc
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; GISEL-NEXT: v_xor_b32_e32 v3, v3, v28
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; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v15, s[4:5]
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; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v7, v2, vcc
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; GISEL-NEXT: v_xor_b32_e32 v6, v6, v33
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; GISEL-NEXT: v_xor_b32_e32 v7, v8, v28
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; GISEL-NEXT: v_xor_b32_e32 v8, v3, v33
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; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v2, v28, s[6:7]
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; GISEL-NEXT: v_xor_b32_e32 v8, v2, v33
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; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v3, v28, s[6:7]
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; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v7, v28, vcc
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; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v33, s[8:9]
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; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v8, v33, vcc
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@ -3216,36 +3217,38 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
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; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
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; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v8, v32, 0
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v8, v20, 0
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; GISEL-NEXT: v_mul_lo_u32 v28, v8, v21
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; GISEL-NEXT: v_mul_lo_u32 v29, v9, v20
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; GISEL-NEXT: v_mul_lo_u32 v34, v8, v21
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; GISEL-NEXT: v_mul_lo_u32 v35, v9, v20
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; GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v12, v24, 0
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; GISEL-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v12, v18, 0
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; GISEL-NEXT: v_mul_lo_u32 v30, v12, v19
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; GISEL-NEXT: v_mul_lo_u32 v31, v13, v18
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; GISEL-NEXT: v_mul_lo_u32 v36, v12, v19
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; GISEL-NEXT: v_mul_lo_u32 v37, v13, v18
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; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v9, v33, v[22:23]
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v13, v25, v[26:27]
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; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v10, v32, v[18:19]
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; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v14, v24, v[22:23]
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; GISEL-NEXT: v_mad_u64_u32 v[17:18], vcc, v8, v33, v[17:18]
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; GISEL-NEXT: v_mad_u64_u32 v[21:22], s[4:5], v12, v25, v[21:22]
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; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v9, v32, v[17:18]
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; GISEL-NEXT: v_addc_u32_e64 v17, s[6:7], v19, v28, s[6:7]
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; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v13, v24, v[21:22]
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; GISEL-NEXT: v_addc_u32_e64 v18, s[6:7], v23, v30, s[6:7]
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; GISEL-NEXT: v_addc_u32_e32 v17, vcc, v17, v29, vcc
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; GISEL-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v10, v32, v[18:19]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[28:29], s[4:5], v14, v24, v[22:23]
|
||||
; GISEL-NEXT: v_mov_b32_e32 v18, v26
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[30:31], vcc, v8, v33, v[17:18]
|
||||
; GISEL-NEXT: v_mov_b32_e32 v22, v28
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v12, v25, v[21:22]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[21:22], s[6:7], v9, v32, v[30:31]
|
||||
; GISEL-NEXT: v_addc_u32_e64 v12, s[6:7], v27, v34, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v13, v24, v[17:18]
|
||||
; GISEL-NEXT: v_addc_u32_e64 v13, s[6:7], v29, v36, s[6:7]
|
||||
; GISEL-NEXT: v_addc_u32_e32 v12, vcc, v12, v35, vcc
|
||||
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v16
|
||||
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
|
||||
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v18, v31, s[4:5]
|
||||
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v21, vcc
|
||||
; GISEL-NEXT: v_addc_u32_e64 v13, s[4:5], v13, v37, s[4:5]
|
||||
; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], v4, v20
|
||||
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v12, s[4:5]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v10, v33, v[17:18]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v14, v25, v[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v11, v32, v[16:17]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v15, v24, v[18:19]
|
||||
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v9, vcc
|
||||
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v10, vcc
|
||||
; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v13, s[4:5]
|
||||
; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v11, vcc
|
||||
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v8, s[4:5]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v10, v33, v[12:13]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v14, v25, v[13:14]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v11, v32, v[16:17]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v15, v24, v[18:19]
|
||||
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v22, vcc
|
||||
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v12, vcc
|
||||
; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v9, s[4:5]
|
||||
; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v10, vcc
|
||||
; GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
%shl = urem <2 x i128> %lhs, %rhs
|
||||
ret <2 x i128> %shl
|
||||
|
||||
@ -237,31 +237,31 @@ define i128 @fptosi_f64_to_i128(double %x) {
|
||||
; GISEL-NEXT: v_add_u32_e32 v7, 0xfffffbcd, v6
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v10, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v12, v9, 0
|
||||
; GISEL-NEXT: v_add_u32_e32 v6, 0xfffffb8d, v6
|
||||
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v7
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v11, v9, v[0:1]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v9, v[0:1]
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v10, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v10, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v10, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v11, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v14, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v12, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v10
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v12, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v13, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v11, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v13, v8, v[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v11, v10, s[10:11]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v14, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v5, v8, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr6
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr8
|
||||
@ -275,17 +275,18 @@ define i128 @fptosi_f64_to_i128(double %x) {
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v4, v8, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v5, v9, v[2:3]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v5, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v4, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[6:7], v5, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v4, s[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v6, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v6, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v7, v1, v5, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v6, v8, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[6:7], v7, v9, v[2:3]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v7, v9
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v4
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], vcc, v6, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v6, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[6:7], v7, v8, v[3:4]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v5, v6, s[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v10, vcc
|
||||
; GISEL-NEXT: .LBB0_6: ; %Flow1
|
||||
; GISEL-NEXT: s_or_b64 exec, exec, s[8:9]
|
||||
; GISEL-NEXT: .LBB0_7: ; %Flow2
|
||||
@ -604,31 +605,31 @@ define i128 @fptoui_f64_to_i128(double %x) {
|
||||
; GISEL-NEXT: v_add_u32_e32 v7, 0xfffffbcd, v6
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v10, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v12, v9, 0
|
||||
; GISEL-NEXT: v_add_u32_e32 v6, 0xfffffb8d, v6
|
||||
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v7
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v11, v9, v[0:1]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v9, v[0:1]
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v10, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v10, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v10, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v11, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v14, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v12, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v10
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v12, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v13, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v11, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v13, v8, v[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v11, v10, s[10:11]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v14, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v5, v8, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr6
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr8
|
||||
@ -642,17 +643,18 @@ define i128 @fptoui_f64_to_i128(double %x) {
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v4, v8, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v5, v9, v[2:3]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v5, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v4, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[6:7], v5, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v4, s[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v6, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v6, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v7, v1, v5, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v6, v8, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[6:7], v7, v9, v[2:3]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v7, v9
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v4
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], vcc, v6, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v6, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[6:7], v7, v8, v[3:4]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v5, v6, s[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v10, vcc
|
||||
; GISEL-NEXT: .LBB1_6: ; %Flow1
|
||||
; GISEL-NEXT: s_or_b64 exec, exec, s[8:9]
|
||||
; GISEL-NEXT: .LBB1_7: ; %Flow2
|
||||
@ -962,31 +964,31 @@ define i128 @fptosi_f32_to_i128(float %x) {
|
||||
; GISEL-NEXT: v_add_u32_e32 v7, 0xffffff6a, v6
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v10, v8, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v12, v8, 0
|
||||
; GISEL-NEXT: v_add_u32_e32 v6, 0xffffff2a, v6
|
||||
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v7
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v11, v8, v[0:1]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v8, v[0:1]
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v10, v9, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v10, v8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v10, v8, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v11, v8
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v14, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v9, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v12, v9, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v10
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v12, v8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v8, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v13, v8
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v11, v9, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v13, v9, v[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v11, v10, s[10:11]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v8, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v14, v8, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v9, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v5, v9, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr6
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr9
|
||||
@ -999,12 +1001,14 @@ define i128 @fptosi_f32_to_i128(float %x) {
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v9, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v8, 0
|
||||
; GISEL-NEXT: v_mul_lo_u32 v5, v4, v8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v4, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v6, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v6, v9, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v6, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v4, v1
|
||||
; GISEL-NEXT: v_mul_lo_u32 v7, v6, v8
|
||||
; GISEL-NEXT: v_mov_b32_e32 v5, v2
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v6, v8, v[4:5]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
|
||||
; GISEL-NEXT: .LBB2_6: ; %Flow1
|
||||
; GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; GISEL-NEXT: .LBB2_7: ; %Flow2
|
||||
@ -1314,31 +1318,31 @@ define i128 @fptoui_f32_to_i128(float %x) {
|
||||
; GISEL-NEXT: v_add_u32_e32 v7, 0xffffff6a, v6
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v10, v8, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v12, v8, 0
|
||||
; GISEL-NEXT: v_add_u32_e32 v6, 0xffffff2a, v6
|
||||
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v7
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[4:5]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v11, v8, v[0:1]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v8, v[0:1]
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v10, v9, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v10, v8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v10, v8, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v11, v8
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v14, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v9, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v12, v9, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v10
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v12, v8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v8, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v13, v8
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v11, v9, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v13, v9, v[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v11, v10, s[10:11]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v8, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v14, v8, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v9, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v5, v9, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr6
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr9
|
||||
@ -1351,12 +1355,14 @@ define i128 @fptoui_f32_to_i128(float %x) {
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v9, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v8, 0
|
||||
; GISEL-NEXT: v_mul_lo_u32 v5, v4, v8
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v4, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v6, v0, v4, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v6, v9, 0
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v6, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v4, v1
|
||||
; GISEL-NEXT: v_mul_lo_u32 v7, v6, v8
|
||||
; GISEL-NEXT: v_mov_b32_e32 v5, v2
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], vcc, v6, v8, v[4:5]
|
||||
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
|
||||
; GISEL-NEXT: .LBB3_6: ; %Flow1
|
||||
; GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; GISEL-NEXT: .LBB3_7: ; %Flow2
|
||||
@ -1702,31 +1708,31 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
|
||||
; GISEL-NEXT: v_add_u32_e32 v10, 0xffffff7a, v5
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v10, v[6:7]
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v10
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v11, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v12, v9, 0
|
||||
; GISEL-NEXT: v_add_u32_e32 v4, 0xffffff3a, v5
|
||||
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v10
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[6:7]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v4, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[0:1]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v9, v[0:1]
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v10, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v10, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v11, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v11, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v11, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v12, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v14, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v12, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v10
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v12, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v13, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v12, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v13, v8, v[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v11, v10, s[10:11]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v10, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v14, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v5, v8, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr5
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v8, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr8
|
||||
; GISEL-NEXT: .LBB6_4: ; %Flow
|
||||
@ -2050,31 +2056,31 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
|
||||
; GISEL-NEXT: v_add_u32_e32 v10, 0xffffff7a, v5
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v10, v[6:7]
|
||||
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v10
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v11, v9, 0
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v12, v9, 0
|
||||
; GISEL-NEXT: v_add_u32_e32 v4, 0xffffff3a, v5
|
||||
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v10
|
||||
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[6:7]
|
||||
; GISEL-NEXT: v_lshlrev_b64 v[4:5], v4, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[0:1]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v9, v[0:1]
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
|
||||
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v10
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v10, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v10, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v11, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v6
|
||||
; GISEL-NEXT: v_mul_lo_u32 v6, v11, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v11, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v12, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v14, v2, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v8, v[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v12, v8, 0
|
||||
; GISEL-NEXT: v_mov_b32_e32 v2, v10
|
||||
; GISEL-NEXT: v_mul_lo_u32 v10, v12, v9
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v9, v[1:2]
|
||||
; GISEL-NEXT: v_mul_lo_u32 v4, v13, v9
|
||||
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v12, v8, v[1:2]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v13, v8, v[6:7]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v11, v10, s[10:11]
|
||||
; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v10, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v14, v9, v[4:5]
|
||||
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v5, v8, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr5
|
||||
; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v8, v[6:7]
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
|
||||
; GISEL-NEXT: ; implicit-def: $vgpr8
|
||||
; GISEL-NEXT: .LBB7_4: ; %Flow
|
||||
|
||||
@ -5775,28 +5775,28 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
|
||||
; GFX7-GISEL-LABEL: clpeak_imad_pat_i64:
|
||||
; GFX7-GISEL: ; %bb.0: ; %entry
|
||||
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v8, vcc, v0, v6
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v2, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v9, vcc, v4, v7, vcc
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v6
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v2, v[6:7]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v6, 0
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v1, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v7, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v2, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v8, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v7, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v8
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v2, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v11, vcc, v6, v9, vcc
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v10, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v11, v2, v[7:8]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v6, vcc
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v1, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v8, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v7, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v10, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v8, v[4:5]
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-SDAG-LABEL: clpeak_imad_pat_i64:
|
||||
@ -5831,28 +5831,28 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
|
||||
; GFX8-GISEL-LABEL: clpeak_imad_pat_i64:
|
||||
; GFX8-GISEL: ; %bb.0: ; %entry
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v6, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v8, vcc, v0, v6
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v2, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v9, vcc, v4, v7, vcc
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v6
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v2, v[6:7]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v6, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v6, 0
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v7, vcc, 1, v5
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v1, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v7, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v2, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v8, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v7, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v8, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v10, vcc, v0, v8
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v2, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v11, vcc, v6, v9, vcc
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v10, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v11, v2, v[7:8]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v7, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v6, vcc
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v8, vcc, 1, v4
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v1, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v8, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v7, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v10, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v8, v[4:5]
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX900-SDAG-LABEL: clpeak_imad_pat_i64:
|
||||
@ -5883,28 +5883,28 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
|
||||
; GFX900-GISEL-LABEL: clpeak_imad_pat_i64:
|
||||
; GFX900-GISEL: ; %bb.0: ; %entry
|
||||
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v3, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, v0, v6
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v2, v[4:5]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v2, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, v4, v7, vcc
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v6
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v3, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v9, v2, v[6:7]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v4, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v6, 0
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v7, vcc, 1, v5
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v1, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v7, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v2, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, v[4:5]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v8, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v7, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v2, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v3, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, v0, v8
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v2, v[4:5]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v2, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, v6, v9, vcc
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v10, v3, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v11, v2, v[7:8]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 1, v4
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v1, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v8, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v9, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v7, v[5:6]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v10, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v8, v[4:5]
|
||||
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX90A-SDAG-LABEL: clpeak_imad_pat_i64:
|
||||
@ -5935,29 +5935,29 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
|
||||
; GFX90A-GISEL-LABEL: clpeak_imad_pat_i64:
|
||||
; GFX90A-GISEL: ; %bb.0: ; %entry
|
||||
; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v3, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v2, v[4:5]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v1, v1, v4
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, v0, v6
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v7, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v2, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, v3, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v2, v[6:7]
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v5, v5, v2
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v7, vcc, 1, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v0, 0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v5, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, v[0:1]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v4, v3, v0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v7, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v8, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, v[2:3]
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v3, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v2, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v2, v[4:5]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v1, v1, v6
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, v0, v8
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v10, vcc, v1, v9, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v3, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v2, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v2, v[6:7]
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v6, v5, v8
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 1, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v5, 0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v6, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v7, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v7, v[0:1]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v6, v3, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v9, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v8, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v8, v[4:5]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX90A-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -6408,52 +6408,52 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
; GFX7-GISEL-LABEL: clpeak_imad_pat_v2i64:
|
||||
; GFX7-GISEL: ; %bb.0: ; %entry
|
||||
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v12, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v13, vcc, 0, v1, vcc
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v2
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v4, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v6, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v5, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v1, vcc
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v16, vcc, 1, v2
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v14, v4, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v3, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v16, v6, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v14, v5, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v3
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v14, v7, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v4, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v3, vcc, v0, v12
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v15, v6, v[10:11]
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v16, vcc, v8, v13, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v4, 0
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v17, vcc, v2, v14
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v17, v6, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v11
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v3, v5, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v16, v7, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v15, v4, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v3, vcc, v0, v14
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v17, v6, v[10:11]
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v18, vcc, v12, v15, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v3, v4, 0
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v16, vcc, v2, v16
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v16, v6, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v10
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v5, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v14
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v18, vcc, v9, v15, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v17, v7, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v16, v4, v[11:12]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v18, v6, v[14:15]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v10, v11, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v8, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v16, v7, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v19, vcc, v8, v17, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v18, v4, v[10:11]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v19, v6, v[14:15]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v10, vcc, 1, v0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v12, vcc
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v12, vcc, 1, v2
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v5
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v6, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v12, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v16, v10, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v6
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v1, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v12, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v2, vcc, 0, v9, vcc
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v10
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v3, v11, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v7
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v13, v2, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v16, vcc, 1, v13
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v14, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v4, v12, v[2:3]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v16, 0
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v4, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v15, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v14, vcc, 1, v9
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v11, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v16, vcc
|
||||
; GFX7-GISEL-NEXT: v_add_i32_e32 v17, vcc, 1, v13
|
||||
; GFX7-GISEL-NEXT: v_addc_u32_e32 v18, vcc, 0, v3, vcc
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v14, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v12, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v17, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v4, v15, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v3
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v17, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v14, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v16, v[10:11]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v5, v18, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v7, v14, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v10, v17, v[11:12]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -6513,52 +6513,52 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
; GFX8-GISEL-LABEL: clpeak_imad_pat_v2i64:
|
||||
; GFX8-GISEL: ; %bb.0: ; %entry
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v12, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v13, vcc, 0, v1, vcc
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v14, vcc, 1, v2
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v4, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v6, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v5, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v14, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v1, vcc
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v16, vcc, 1, v2
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v14, v4, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v3, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v16, v6, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v14, v5, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v3
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v14, v7, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v4, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v3, vcc, v0, v12
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v15, v6, v[10:11]
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v16, vcc, v8, v13, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v4, 0
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v17, vcc, v2, v14
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v17, v6, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v11
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v3, v5, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v16, v7, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v15, v4, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v3, vcc, v0, v14
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v17, v6, v[10:11]
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v18, vcc, v12, v15, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v3, v4, 0
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v16, vcc, v2, v16
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v16, v6, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v10
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v5, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v14
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v18, vcc, v9, v15, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v17, v7, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v16, v4, v[11:12]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v18, v6, v[14:15]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v11, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v10, v11, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v8, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v16, v7, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v19, vcc, v8, v17, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v18, v4, v[10:11]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v19, v6, v[14:15]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v10, vcc, 1, v0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v12, vcc
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v12, vcc, 1, v2
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v5
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v6, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v12, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v16, v10, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v6
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v1, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v12, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v2, vcc, 0, v9, vcc
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v14, vcc, 1, v10
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v3, v11, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v7
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v13, v2, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v16, vcc, 1, v13
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v14, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v4, v12, v[2:3]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v16, 0
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v4, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v15, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v14, vcc, 1, v9
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v11, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v15, vcc, 0, v16, vcc
|
||||
; GFX8-GISEL-NEXT: v_add_u32_e32 v17, vcc, 1, v13
|
||||
; GFX8-GISEL-NEXT: v_addc_u32_e32 v18, vcc, 0, v3, vcc
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v14, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v12, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v17, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v4, v15, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v3
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v17, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v14, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v16, v[10:11]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v5, v18, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v7, v14, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v10, v17, v[11:12]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -6610,52 +6610,52 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
; GFX900-GISEL-LABEL: clpeak_imad_pat_v2i64:
|
||||
; GFX900-GISEL: ; %bb.0: ; %entry
|
||||
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 1, v2
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v4, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v6, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v5, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v1, vcc
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v16, vcc, 1, v2
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v14, v4, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v3, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v16, v6, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v14, v5, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v3
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v14, v7, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v4, v[8:9]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v3, vcc, v0, v12
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v15, v6, v[10:11]
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v16, vcc, v8, v13, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v4, 0
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v17, vcc, v2, v14
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v17, v6, 0
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v11
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v3, v5, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v16, v7, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v15, v4, v[8:9]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v3, vcc, v0, v14
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v17, v6, v[10:11]
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v18, vcc, v12, v15, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v3, v4, 0
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v16, vcc, v2, v16
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v16, v6, 0
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v10
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v5, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v14
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v18, vcc, v9, v15, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v17, v7, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v16, v4, v[11:12]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v18, v6, v[14:15]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v11, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v10, v11, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v8, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v16, v7, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v19, vcc, v8, v17, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v18, v4, v[10:11]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v19, v6, v[14:15]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, 1, v0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v10, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v12, vcc
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 1, v2
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, v5
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v6, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v12, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v8, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v16, v10, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, v6
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v1, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v12, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v9, vcc
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 1, v10
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v3, v11, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, v7
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v13, v2, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v16, vcc, 1, v13
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v14, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v4, v12, v[2:3]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v16, 0
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v4, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v15, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 1, v9
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v11, v[0:1]
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v16, vcc
|
||||
; GFX900-GISEL-NEXT: v_add_co_u32_e32 v17, vcc, 1, v13
|
||||
; GFX900-GISEL-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v3, vcc
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v14, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v3, v12, v[8:9]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v17, 0
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v4, v15, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v3
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v17, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v14, v[4:5]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v16, v[10:11]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v5, v18, v[1:2]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v7, v14, v[8:9]
|
||||
; GFX900-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v10, v17, v[11:12]
|
||||
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
@ -6707,54 +6707,54 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
; GFX90A-GISEL-LABEL: clpeak_imad_pat_v2i64:
|
||||
; GFX90A-GISEL: ; %bb.0: ; %entry
|
||||
; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 1, v2
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v3, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v5, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v4, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v11, v4, v[2:3]
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 1, v2
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v3, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v5, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v4, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v4, v[2:3]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v1, v1, v8
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v14, v7, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, v0, v12
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v15, v6, v[8:9]
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v16, vcc, v1, v13, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v3, v3, v10
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, v2, v14
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v12, v5, 0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, v3, v15, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v4, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v16, v4, v[10:11]
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v14, v7, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v9, v9, v12
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v14, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v15, v6, v[10:11]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v10, v5, v12
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v5, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v11, vcc, 1, v2
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v3, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v13, vcc, 1, v8
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v9, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v5, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v5, v[0:1]
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v12, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v15, vcc, 1, v4
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v8, v3, v6
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v4, v11, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v11, v[0:1]
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v10, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v9, v7, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v14, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v13, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v13, v[4:5]
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v16, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v7, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, v0, v10
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v6, v[8:9]
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v14, vcc, v1, v11, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v3, v3, v8
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, v2, v12
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v4, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v10, v5, 0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, v3, v13, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v14, v4, v[10:11]
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v12, v7, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v9, v9, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v6, v[10:11]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v5, v5, v6
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, 1, v0
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v1, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, 1, v2
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v3, vcc
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v0, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 1, v8
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v6, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v9, v6, v[0:1]
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v9, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v8, v3, v0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v11, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 1, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v4, v10, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v10, v[0:1]
|
||||
; GFX90A-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v5, vcc
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v7, v7, v0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v12, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v13, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v12, v[2:3]
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v15, 0
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v14, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v14, v[4:5]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v3, v3, v4
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v15, 0
|
||||
; GFX90A-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v15, v[4:5]
|
||||
; GFX90A-GISEL-NEXT: v_add_u32_e32 v3, v3, v6
|
||||
; GFX90A-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: clpeak_imad_pat_v2i64:
|
||||
|
||||
@ -781,16 +781,23 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v14, v38 :: v_dual_mov_b32 v15, v39
|
||||
; GISEL12-NEXT: s_wait_kmcnt 0x0
|
||||
; GISEL12-NEXT: s_swappc_b64 s[30:31], s[0:1]
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v24, v0 :: v_dual_mov_b32 v25, v1
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v26, v2 :: v_dual_mov_b32 v27, v3
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v29, v5
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v30, v6 :: v_dual_mov_b32 v31, v7
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v32, v8 :: v_dual_mov_b32 v33, v9
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v34, v10 :: v_dual_mov_b32 v35, v11
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v36, v12 :: v_dual_mov_b32 v37, v13
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v39, v15
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v40, v0 :: v_dual_mov_b32 v41, v1
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v42, v2 :: v_dual_mov_b32 v43, v3
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v44, v4 :: v_dual_mov_b32 v45, v5
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v46, v6 :: v_dual_mov_b32 v47, v7
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v49, v9
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v11
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v52, v12 :: v_dual_mov_b32 v53, v13
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v55, v15
|
||||
; GISEL12-NEXT: s_mov_b32 exec_lo, s9
|
||||
; GISEL12-NEXT: ; kill: def $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 killed $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 killed $exec
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v24, v40 :: v_dual_mov_b32 v25, v41
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v26, v42 :: v_dual_mov_b32 v27, v43
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v28, v44 :: v_dual_mov_b32 v29, v45
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v30, v46 :: v_dual_mov_b32 v31, v47
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v32, v48 :: v_dual_mov_b32 v33, v49
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v34, v50 :: v_dual_mov_b32 v35, v51
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v36, v52 :: v_dual_mov_b32 v37, v53
|
||||
; GISEL12-NEXT: v_dual_mov_b32 v38, v54 :: v_dual_mov_b32 v39, v55
|
||||
; GISEL12-NEXT: .LBB5_2: ; %tail
|
||||
; GISEL12-NEXT: s_wait_alu 0xfffe
|
||||
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
|
||||
@ -946,24 +953,39 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
|
||||
; GISEL10-NEXT: s_mov_b64 s[2:3], s[50:51]
|
||||
; GISEL10-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GISEL10-NEXT: s_swappc_b64 s[30:31], s[12:13]
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v24, v0
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v25, v1
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v26, v2
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v27, v3
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v28, v4
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v29, v5
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v30, v6
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v31, v7
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v32, v8
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v33, v9
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v34, v10
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v35, v11
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v36, v12
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v37, v13
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v38, v14
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v39, v15
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v40, v0
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v41, v1
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v42, v2
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v43, v3
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v44, v4
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v45, v5
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v46, v6
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v47, v7
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v48, v8
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v49, v9
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v50, v10
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v51, v11
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v52, v12
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v53, v13
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v54, v14
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v55, v15
|
||||
; GISEL10-NEXT: s_mov_b32 exec_lo, s9
|
||||
; GISEL10-NEXT: ; kill: def $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 killed $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 killed $exec
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v24, v40
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v25, v41
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v26, v42
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v27, v43
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v28, v44
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v29, v45
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v30, v46
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v31, v47
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v32, v48
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v33, v49
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v34, v50
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v35, v51
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v36, v52
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v37, v53
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v38, v54
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v39, v55
|
||||
; GISEL10-NEXT: .LBB5_2: ; %tail
|
||||
; GISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s4
|
||||
; GISEL10-NEXT: v_mov_b32_e32 v8, v24
|
||||
|
||||
@ -2481,10 +2481,11 @@ define i64 @test_vector_reduce_mul_v2i64(<2 x i64> %v) {
|
||||
; GFX7-GISEL: ; %bb.0: ; %entry
|
||||
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, v0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v5, v1
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v5, v2
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v6, v1
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v5, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v4, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v6, v5, v[7:8]
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-SDAG-LABEL: test_vector_reduce_mul_v2i64:
|
||||
@ -2502,10 +2503,11 @@ define i64 @test_vector_reduce_mul_v2i64(<2 x i64> %v) {
|
||||
; GFX8-GISEL: ; %bb.0: ; %entry
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, v0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, v1
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, v2
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v6, v1
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v5, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v4, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v6, v5, v[7:8]
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX9-SDAG-LABEL: test_vector_reduce_mul_v2i64:
|
||||
@ -2524,8 +2526,8 @@ define i64 @test_vector_reduce_mul_v2i64(<2 x i64> %v) {
|
||||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, v1
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v4, v3, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v4, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v5, v2, v[6:7]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v5, v2, v[6:7]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v8
|
||||
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: test_vector_reduce_mul_v2i64:
|
||||
@ -2626,9 +2628,9 @@ define i64 @test_vector_reduce_mul_v3i64(<3 x i64> %v) {
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v8
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v3, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v4, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v2, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v7, v5, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, v4, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v2, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v7, v5, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v10, v4, v[8:9]
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-SDAG-LABEL: test_vector_reduce_mul_v3i64:
|
||||
@ -2654,9 +2656,9 @@ define i64 @test_vector_reduce_mul_v3i64(<3 x i64> %v) {
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v8
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v3, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v4, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v2, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v7, v5, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, v4, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v2, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v7, v5, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v10, v4, v[8:9]
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX9-SDAG-LABEL: test_vector_reduce_mul_v3i64:
|
||||
@ -2677,12 +2679,12 @@ define i64 @test_vector_reduce_mul_v3i64(<3 x i64> %v) {
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v0, v3, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v0, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v2, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v7, v7, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v1, v2, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v8, v7, v10
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v6, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v6, v4, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v7, v4, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v8, v4, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v6
|
||||
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: test_vector_reduce_mul_v3i64:
|
||||
@ -2816,10 +2818,10 @@ define i64 @test_vector_reduce_mul_v4i64(<4 x i64> %v) {
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v12
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v2, v7, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v9, v11, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v6, v[15:16]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v8, v4, v[13:14]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v2, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v11, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v3, v6, v[15:16]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v4, v[13:14]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v17, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v11, v[3:4]
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-SDAG-LABEL: test_vector_reduce_mul_v4i64:
|
||||
@ -2853,10 +2855,10 @@ define i64 @test_vector_reduce_mul_v4i64(<4 x i64> %v) {
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v12
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v2, v7, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v9, v11, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v6, v[15:16]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v8, v4, v[13:14]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v2, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v11, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v3, v6, v[15:16]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v4, v[13:14]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v9, v17, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v11, v[3:4]
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX9-SDAG-LABEL: test_vector_reduce_mul_v4i64:
|
||||
@ -2881,16 +2883,16 @@ define i64 @test_vector_reduce_mul_v4i64(<4 x i64> %v) {
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v0, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v0, v4, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v4, v[10:11]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v9, v9, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v1, v4, v[10:11]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v7, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, v6, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v3, v6, v[0:1]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v2, v5, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v8, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v3, v6, v[0:1]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v5, v10
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v9, v9, v12
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v8, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v8, v4, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v9, v4, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v9, v4, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v6
|
||||
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: test_vector_reduce_mul_v4i64:
|
||||
@ -3068,31 +3070,29 @@ define i64 @test_vector_reduce_mul_v8i64(<8 x i64> %v) {
|
||||
; GFX7-GISEL: ; %bb.0: ; %entry
|
||||
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v4, v12, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[19:20], s[4:5], v0, v8, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v4, v13, v[17:18]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v12, v[17:18]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v19, v16, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v5, v13
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v13, v20
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v0, v9, v[13:14]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v19, v4, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v0, v8, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v4, v13, v[17:18]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v5, v12, v[18:19]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v20, v16, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v20, v22, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v5, v21
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[19:20], s[4:5], v6, v14, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v1, v8, v[17:18]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v2, v10, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v0, v9, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v20
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v15, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v6, v18
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v2, v11, v[6:7]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v14, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v17, v19, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v10, v[20:21]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v7
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v17, v0, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v6, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v19, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v8, v16, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v12, v2, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v6, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[21:22], s[4:5], v1, v8, v[17:18]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v6, v15, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v10, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v2, v11, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v7, v14, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v0, v19, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v3, v10, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v2, v8
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v0, v1, v[2:3]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v7, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v19, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v21, v16, v[12:13]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v4, v2, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v7, v[8:9]
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-SDAG-LABEL: test_vector_reduce_mul_v8i64:
|
||||
@ -3139,31 +3139,29 @@ define i64 @test_vector_reduce_mul_v8i64(<8 x i64> %v) {
|
||||
; GFX8-GISEL: ; %bb.0: ; %entry
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v4, v12, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[19:20], s[4:5], v0, v8, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v4, v13, v[17:18]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v12, v[17:18]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v19, v16, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, v13
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v13, v20
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v0, v9, v[13:14]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v19, v4, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v0, v8, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v4, v13, v[17:18]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v5, v12, v[18:19]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v20, v16, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v20, v22, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, v21
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[19:20], s[4:5], v6, v14, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v1, v8, v[17:18]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v2, v10, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v0, v9, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v20
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v15, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v6, v18
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v2, v11, v[6:7]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v14, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v17, v19, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v10, v[20:21]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v7
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v17, v0, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v6, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v19, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v8, v16, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v12, v2, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v6, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[21:22], s[4:5], v1, v8, v[17:18]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v6, v15, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v10, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v2, v11, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v7, v14, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v0, v19, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v3, v10, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, v8
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v0, v1, v[2:3]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v7, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v19, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v21, v16, v[12:13]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v4, v2, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v7, v[8:9]
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX9-SDAG-LABEL: test_vector_reduce_mul_v8i64:
|
||||
@ -3204,32 +3202,32 @@ define i64 @test_vector_reduce_mul_v8i64(<8 x i64> %v) {
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v0, v9, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v0, v8, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v8, v[18:19]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[0:1], v1, v8, v[18:19]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v2, v11, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v17, v17, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v10, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, v10, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v3, v10, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v4, v13, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v10, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v10, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v12, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v5, v12, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v3, v4
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v5, v12, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v6, v15, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v18, v1, v18
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v3, v10
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v6, v14, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v7, v14, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v7, v14, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v17, v17, v20
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v5, v10
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v16, v1, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v5, v6
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v17, v2, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v0, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v16, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v17, v2, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v7, v7, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, v4, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v10, v4, v[0:1]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v18, v4, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v3, v3, v0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v10, v7, v10
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v6, v3, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v6, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v7, v2, v[4:5]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v10, v2, v[4:5]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v6
|
||||
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: test_vector_reduce_mul_v8i64:
|
||||
@ -3550,63 +3548,63 @@ define i64 @test_vector_reduce_mul_v16i64(<16 x i64> %v) {
|
||||
; GFX7-GISEL: ; %bb.0: ; %entry
|
||||
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[31:32], s[4:5], v8, v24, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[4:5], v8, v25, v[32:33]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v9, v24, v[32:33]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v0, v16, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[4:5], v24, v31, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v9, v33
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v24, v8, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v24, v25
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v0, v17, v[24:25]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v16, v[24:25]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v18, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v31, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[33:34], s[4:5], v8, v25, v[32:33]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[35:36], s[4:5], v9, v24, v[33:34]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v16, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v8, v31, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[4:5], v8, v35, v[25:26]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v8, v9
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[34:35], s[4:5], v0, v17, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v1, v16, v[34:35]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v26, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v10, v27, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v11, v26, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v16, v0, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v11
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v9, v[1:2]
|
||||
; GFX7-GISEL-NEXT: buffer_load_dword v9, off, s[0:3], s32
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v17
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, v19, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v18, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v8, v31, v[32:33]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v27, v[1:2]
|
||||
; GFX7-GISEL-NEXT: buffer_load_dword v27, off, s[0:3], s32
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[31:32], s[4:5], v2, v18, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[33:34], s[4:5], v11, v26, v[8:9]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v31, v0, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v9
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v31, v33, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v32
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[25:26], s[4:5], v2, v19, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v18, v[25:26]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v28, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v1, v0, v[24:25]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v4, v20, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v1, v0, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v4, v20, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v29, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v17, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, v18
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v13, v28, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v21, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v12, v29, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v9, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v13, v28, v[18:19]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, v10
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v12
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v14, v30, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v20, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v17, v0, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, v13
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v6, v22, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v2, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, v18
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v4, v21, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v14, v30, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v9, v0, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v20, v[12:13]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v4
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v22, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v0, v2, v[18:19]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v4, v3, 0
|
||||
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v14, v9, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v17, v12, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v15, v30, v[4:5]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v23, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v2, v14
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v17, v1, v[2:3]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v7, v22, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v32, v11, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v12, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v13, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v32, v0, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v10, v1, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v16, v13, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v11, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v9, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v14, v27, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v2, v5
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v15, v30, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v23, v[2:3]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, v13
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v0, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v22, v[9:10]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v24, v11, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v0, v3, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v8, v12, 0
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v10
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v24, v20, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v8, v1, v[0:1]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v9, v3, 0
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v17, v12, v[13:14]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v16, v11, v[5:6]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v7, v[1:2]
|
||||
; GFX7-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v12, v3, v[4:5]
|
||||
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-SDAG-LABEL: test_vector_reduce_mul_v16i64:
|
||||
@ -3695,63 +3693,63 @@ define i64 @test_vector_reduce_mul_v16i64(<16 x i64> %v) {
|
||||
; GFX8-GISEL: ; %bb.0: ; %entry
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[31:32], s[4:5], v8, v24, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[4:5], v8, v25, v[32:33]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v9, v24, v[32:33]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v0, v16, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[4:5], v24, v31, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v9, v33
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v24, v8, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v24, v25
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v0, v17, v[24:25]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v16, v[24:25]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v18, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v31, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[33:34], s[4:5], v8, v25, v[32:33]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[35:36], s[4:5], v9, v24, v[33:34]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v16, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v8, v31, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[4:5], v8, v35, v[25:26]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v8, v9
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[34:35], s[4:5], v0, v17, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v1, v16, v[34:35]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v26, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v10, v27, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v11, v26, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v16, v0, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v11
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v9, v[1:2]
|
||||
; GFX8-GISEL-NEXT: buffer_load_dword v9, off, s[0:3], s32
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v17
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, v19, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v18, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v8, v31, v[32:33]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v27, v[1:2]
|
||||
; GFX8-GISEL-NEXT: buffer_load_dword v27, off, s[0:3], s32
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[31:32], s[4:5], v2, v18, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[33:34], s[4:5], v11, v26, v[8:9]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v31, v0, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v9
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v31, v33, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v32
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[25:26], s[4:5], v2, v19, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v18, v[25:26]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v28, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v1, v0, v[24:25]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v4, v20, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v1, v0, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v4, v20, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v29, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v17, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, v18
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v13, v28, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v21, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v12, v29, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v9, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v13, v28, v[18:19]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, v10
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v12
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v14, v30, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v20, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v17, v0, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, v13
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v6, v22, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v3, v2, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, v18
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v4, v21, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v14, v30, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v9, v0, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v20, v[12:13]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v4
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v6, v22, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v0, v2, v[18:19]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v4, v3, 0
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v14, v9, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v17, v12, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v15, v30, v[4:5]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v23, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, v14
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v17, v1, v[2:3]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v7, v22, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v32, v11, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v3, v12, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v13, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v32, v0, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v10, v1, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v2, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v16, v13, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v8, v11, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, v9, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[3:4]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v14, v27, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, v5
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v15, v30, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v6, v23, v[2:3]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, v13
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v4, v0, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v22, v[9:10]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v24, v11, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v0, v3, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v8, v12, 0
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v10
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v24, v20, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v8, v1, v[0:1]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v9, v3, 0
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v17, v12, v[13:14]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v16, v11, v[5:6]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v9, v7, v[1:2]
|
||||
; GFX8-GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v12, v3, v[4:5]
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX9-SDAG-LABEL: test_vector_reduce_mul_v16i64:
|
||||
@ -3827,65 +3825,65 @@ define i64 @test_vector_reduce_mul_v16i64(<16 x i64> %v) {
|
||||
; GFX9-GISEL-NEXT: scratch_load_dword v31, off, s32
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[34:35], s[0:1], v0, v17, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[32:33], s[0:1], v0, v16, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v16, v[34:35]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[36:37], s[0:1], v1, v16, v[34:35]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v2, v19, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v33, v33, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v18, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, v18, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[34:35], s[0:1], v3, v18, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v4, v21, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v18, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v18, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v20, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v5, v20, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v5, v20, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v6, v23, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v19, v3, v4
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v20, v3, v18
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v6, v22, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v7, v22, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v7, v22, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v8, v25, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v20, v5, v6
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v21, v5, v18
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v8, v24, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v9, v24, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v9, v24, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v10, v27, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v7, v8
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v34, v1, v34
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v7, v18
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v10, v26, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v11, v26, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v11, v26, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v12, v29, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v3, v9, v10
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v3, v9, v18
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v12, v28, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v13, v28, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v11, v12
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v13, v28, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v33, v33, v36
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v11, v18
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v14, v30, 0
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v14, v31, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[0:1], v15, v30, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v15, v30, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v32, v1, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v9, v13, v14
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v11, v13, v18
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v33, v6, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v0, v3, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[14:15], s[0:1], v32, v6, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v33, v6, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v11, v15, v6
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v0, v8, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v3, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v18, v8, v[0:1]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v7, v7, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v34, v8, v[16:17]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v2, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v13, v15, v18
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v15, v7, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v10, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v19, v10, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v20, v10, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v4, v11, 0
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v12, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v4, v9, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v20, v12, v[4:5]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v14, v1, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v21, v12, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v3, v3, v4
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v14, v1, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v14, v0, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v11, v0, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v5, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v13, v0, v[8:9]
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v6, v3, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v6, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v7, v2, v[0:1]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v2, v9, v0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v2, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v15, v2, v[0:1]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v10, v5, v10
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v5, v9, v6
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v5, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v4, v8, 0
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v5, v8, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v2
|
||||
; GFX9-GISEL-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v10, v8, v[2:3]
|
||||
; GFX9-GISEL-NEXT: v_add_u32_e32 v1, v1, v4
|
||||
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: test_vector_reduce_mul_v16i64:
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user