[AArch64] Initial Ampere1B scheduling model (#81341)
The Ampere1B core is enabled with a new scheduling/pipeline model, as it
provides significant updates over the Ampere1 core; it reduces latencies
on many instructions, has some micro-ops reassigned between the XY and X
units, and provides modelling for the instructions added since Ampere1
and Ampere1A.
As this is the first model implementing the CSSC instructions, we update
the UnsupportedFeatures on all other models (that have CompleteModel
set).
Testcases are added under llvm-mca: these showed the FullFP16 feature
missing, so we are adding it in as part of this commit.
This *adds tests and additional fixes* compared to the reverted #81338.
This commit is contained in:
Philipp Tomsich
GitHub
parent
43c7eb5d7b
commit
dd1897c6cb
@ -837,6 +837,7 @@ include "AArch64SchedA64FX.td"
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include "AArch64SchedThunderX3T110.td"
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include "AArch64SchedTSV110.td"
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include "AArch64SchedAmpere1.td"
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include "AArch64SchedAmpere1B.td"
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include "AArch64SchedNeoverseN1.td"
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include "AArch64SchedNeoverseN2.td"
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include "AArch64SchedNeoverseV1.td"
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@ -1555,7 +1556,7 @@ def ProcessorFeatures {
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FeatureMTE, FeatureSSBS, FeatureRandGen,
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FeatureSB, FeatureSM4, FeatureSHA2,
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FeatureSHA3, FeatureAES, FeatureCSSC,
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FeatureWFxT];
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FeatureWFxT, FeatureFullFP16];
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// ETE and TRBE are future architecture extensions. We temporarily enable them
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// by default for users targeting generic AArch64. The extensions do not
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@ -1723,7 +1724,7 @@ def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
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def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
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[TuneAmpere1A]>;
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def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
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def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B,
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[TuneAmpere1B]>;
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//===----------------------------------------------------------------------===//
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@ -29,7 +29,7 @@ def CortexA53Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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@ -34,7 +34,7 @@ def CortexA57Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -22,7 +22,8 @@ def A64FXModel : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
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[HasMTE, HasMatMulInt8, HasBF16,
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HasPAuth, HasPAuthLR, HasCPA]);
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HasPAuth, HasPAuthLR, HasCPA,
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HasCSSC]);
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let FullInstRWOverlapCheck = 0;
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}
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1149
llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
Normal file
1149
llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
Normal file
File diff suppressed because it is too large
Load Diff
@ -21,7 +21,7 @@ def CycloneModel : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -27,7 +27,7 @@ def ExynosM3Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -27,7 +27,7 @@ def ExynosM4Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -27,7 +27,7 @@ def ExynosM5Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -26,7 +26,7 @@ def FalkorModel : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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// FIXME: Remove when all errors have been fixed.
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let FullInstRWOverlapCheck = 0;
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}
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@ -30,7 +30,7 @@ def KryoModel : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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// FIXME: Remove when all errors have been fixed.
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let FullInstRWOverlapCheck = 0;
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}
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@ -25,7 +25,7 @@ def NeoverseN1Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(PAUnsupported.F,
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SMEUnsupported.F,
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SVEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
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let CompleteModel = 1;
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list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
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[HasSVE2p1, HasPAuthLR, HasCPA]);
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[HasSVE2p1, HasPAuthLR, HasCPA, HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -28,7 +28,8 @@ def NeoverseV1Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
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SMEUnsupported.F,
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[HasMTE, HasCPA]);
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[HasMTE, HasCPA,
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HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -22,7 +22,8 @@ def NeoverseV2Model : SchedMachineModel {
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let CompleteModel = 1;
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list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
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[HasSVE2p1, HasCPA]);
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[HasSVE2p1, HasCPA,
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HasCSSC]);
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}
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//===----------------------------------------------------------------------===//
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@ -27,7 +27,7 @@ def TSV110Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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}
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// Define each kind of processor resource and number available on the TSV110,
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@ -28,7 +28,7 @@ def ThunderXT8XModel : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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// FIXME: Remove when all errors have been fixed.
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let FullInstRWOverlapCheck = 0;
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}
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@ -28,7 +28,7 @@ def ThunderX2T99Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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// FIXME: Remove when all errors have been fixed.
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let FullInstRWOverlapCheck = 0;
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}
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@ -27,7 +27,7 @@ def ThunderX3T110Model : SchedMachineModel {
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F,
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SMEUnsupported.F,
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[HasMTE]);
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[HasMTE, HasCSSC]);
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// FIXME: Remove when all errors have been fixed.
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let FullInstRWOverlapCheck = 0;
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}
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,76 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=aarch64 -mcpu=ampere1b -instruction-tables < %s | FileCheck %s
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abs w1, w2
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abs x2, x3
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cnt w3, w4
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cnt x4, x5
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ctz w5, w6
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ctz x6, x7
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smax w7, w8, w9
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smax x8, x9, x10
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umax w9, w10, w11
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umax x10, x11, x12
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smin w11, w12, w13
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smin w12, w13, w14
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umin w13, w14, w15
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umin x14, x15, x16
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 1 0.25 abs w1, w2
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# CHECK-NEXT: 1 1 0.25 abs x2, x3
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# CHECK-NEXT: 1 3 1.00 cnt w3, w4
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# CHECK-NEXT: 1 3 1.00 cnt x4, x5
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# CHECK-NEXT: 1 1 0.50 ctz w5, w6
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# CHECK-NEXT: 1 1 0.50 ctz x6, x7
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# CHECK-NEXT: 2 1 0.50 smax w7, w8, w9
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# CHECK-NEXT: 2 1 0.50 smax x8, x9, x10
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# CHECK-NEXT: 2 1 0.50 umax w9, w10, w11
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# CHECK-NEXT: 2 1 0.50 umax x10, x11, x12
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# CHECK-NEXT: 2 1 0.50 smin w11, w12, w13
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# CHECK-NEXT: 2 1 0.50 smin w12, w13, w14
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# CHECK-NEXT: 2 1 0.50 umin w13, w14, w15
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# CHECK-NEXT: 2 1 0.50 umin x14, x15, x16
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - Ampere1BUnitA
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# CHECK-NEXT: [0.1] - Ampere1BUnitA
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# CHECK-NEXT: [1.0] - Ampere1BUnitB
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# CHECK-NEXT: [1.1] - Ampere1BUnitB
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# CHECK-NEXT: [2] - Ampere1BUnitBS
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# CHECK-NEXT: [3.0] - Ampere1BUnitL
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# CHECK-NEXT: [3.1] - Ampere1BUnitL
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# CHECK-NEXT: [4.0] - Ampere1BUnitS
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# CHECK-NEXT: [4.1] - Ampere1BUnitS
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# CHECK-NEXT: [5] - Ampere1BUnitX
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# CHECK-NEXT: [6] - Ampere1BUnitY
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# CHECK-NEXT: [7] - Ampere1BUnitZ
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7]
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# CHECK-NEXT: 6.50 6.50 3.50 3.50 2.00 - - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7] Instructions:
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# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - abs w1, w2
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# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - abs x2, x3
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# CHECK-NEXT: - - - - 1.00 - - - - - - - cnt w3, w4
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# CHECK-NEXT: - - - - 1.00 - - - - - - - cnt x4, x5
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# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ctz w5, w6
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# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ctz x6, x7
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smax w7, w8, w9
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smax x8, x9, x10
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umax w9, w10, w11
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umax x10, x11, x12
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smin w11, w12, w13
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smin w12, w13, w14
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umin w13, w14, w15
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# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umin x14, x15, x16
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@ -0,0 +1,349 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=aarch64 -mcpu=ampere1b -instruction-tables < %s | FileCheck %s
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irg x0, x1
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irg sp, x1
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irg x0, sp
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irg x0, x1, x2
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irg sp, x1, x2
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addg x0, x1, #0, #1
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addg sp, x2, #32, #3
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addg x0, sp, #64, #5
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addg x3, x4, #1008, #6
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addg x5, x6, #112, #15
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subg x0, x1, #0, #1
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subg sp, x2, #32, #3
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subg x0, sp, #64, #5
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subg x3, x4, #1008, #6
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subg x5, x6, #112, #15
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gmi x0, x1, x2
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gmi x3, sp, x4
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gmi xzr, x0, x30
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gmi x30, x0, xzr
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subp x0, x1, x2
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subps x0, x1, x2
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subp x0, sp, sp
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subps x0, sp, sp
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subps xzr, x0, x1
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subps xzr, sp, sp
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stg x0, [x1, #-4096]
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stg x1, [x2, #4080]
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stg x2, [sp, #16]
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stg x3, [x1]
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stg sp, [x1]
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stzg x0, [x1, #-4096]
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stzg x1, [x2, #4080]
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stzg x2, [sp, #16]
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stzg x3, [x1]
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stzg sp, [x1]
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stg x0, [x1, #-4096]!
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stg x1, [x2, #4080]!
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stg x2, [sp, #16]!
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stg sp, [sp, #16]!
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stzg x0, [x1, #-4096]!
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stzg x1, [x2, #4080]!
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stzg x2, [sp, #16]!
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stzg sp, [sp, #16]!
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stg x0, [x1], #-4096
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stg x1, [x2], #4080
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stg x2, [sp], #16
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stg sp, [sp], #16
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stzg x0, [x1], #-4096
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stzg x1, [x2], #4080
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stzg x2, [sp], #16
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stzg sp, [sp], #16
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st2g x0, [x1, #-4096]
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st2g x1, [x2, #4080]
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st2g x2, [sp, #16]
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st2g x3, [x1]
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st2g sp, [x1]
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stz2g x0, [x1, #-4096]
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stz2g x1, [x2, #4080]
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stz2g x2, [sp, #16]
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stz2g x3, [x1]
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stz2g sp, [x1]
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st2g x0, [x1, #-4096]!
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st2g x1, [x2, #4080]!
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st2g x2, [sp, #16]!
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st2g sp, [sp, #16]!
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stz2g x0, [x1, #-4096]!
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stz2g x1, [x2, #4080]!
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stz2g x2, [sp, #16]!
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stz2g sp, [sp, #16]!
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st2g x0, [x1], #-4096
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st2g x1, [x2], #4080
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st2g x2, [sp], #16
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st2g sp, [sp], #16
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stz2g x0, [x1], #-4096
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stz2g x1, [x2], #4080
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stz2g x2, [sp], #16
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stz2g sp, [sp], #16
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stgp x0, x1, [x2, #-1024]
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stgp x0, x1, [x2, #1008]
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stgp x0, x1, [sp, #16]
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stgp xzr, x1, [x2, #16]
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stgp x0, xzr, [x2, #16]
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stgp x0, xzr, [x2]
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stgp x0, x1, [x2, #-1024]!
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stgp x0, x1, [x2, #1008]!
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stgp x0, x1, [sp, #16]!
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stgp xzr, x1, [x2, #16]!
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stgp x0, xzr, [x2, #16]!
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stgp x0, x1, [x2], #-1024
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stgp x0, x1, [x2], #1008
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stgp x0, x1, [sp], #16
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stgp xzr, x1, [x2], #16
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stgp x0, xzr, [x2], #16
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ldg x0, [x1]
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ldg x2, [sp, #-4096]
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ldg x3, [x4, #4080]
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ldgm x0, [x1]
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ldgm x1, [sp]
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ldgm xzr, [x2]
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stgm x0, [x1]
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stgm x1, [sp]
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stgm xzr, [x2]
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stzgm x0, [x1]
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stzgm x1, [sp]
|
||||
stzgm xzr, [x2]
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 2 1 1.00 U irg x0, x1
|
||||
# CHECK-NEXT: 2 1 1.00 U irg sp, x1
|
||||
# CHECK-NEXT: 2 1 1.00 U irg x0, sp
|
||||
# CHECK-NEXT: 2 1 1.00 U irg x0, x1, x2
|
||||
# CHECK-NEXT: 2 1 1.00 U irg sp, x1, x2
|
||||
# CHECK-NEXT: 1 1 0.50 addg x0, x1, #0, #1
|
||||
# CHECK-NEXT: 1 1 0.50 addg sp, x2, #32, #3
|
||||
# CHECK-NEXT: 1 1 0.50 addg x0, sp, #64, #5
|
||||
# CHECK-NEXT: 1 1 0.50 addg x3, x4, #1008, #6
|
||||
# CHECK-NEXT: 1 1 0.50 addg x5, x6, #112, #15
|
||||
# CHECK-NEXT: 1 1 0.50 U subg x0, x1, #0, #1
|
||||
# CHECK-NEXT: 1 1 0.50 U subg sp, x2, #32, #3
|
||||
# CHECK-NEXT: 1 1 0.50 U subg x0, sp, #64, #5
|
||||
# CHECK-NEXT: 1 1 0.50 U subg x3, x4, #1008, #6
|
||||
# CHECK-NEXT: 1 1 0.50 U subg x5, x6, #112, #15
|
||||
# CHECK-NEXT: 1 1 0.25 gmi x0, x1, x2
|
||||
# CHECK-NEXT: 1 1 0.25 gmi x3, sp, x4
|
||||
# CHECK-NEXT: 1 1 0.25 gmi xzr, x0, x30
|
||||
# CHECK-NEXT: 1 1 0.25 gmi x30, x0, xzr
|
||||
# CHECK-NEXT: 1 1 0.25 subp x0, x1, x2
|
||||
# CHECK-NEXT: 1 1 0.25 U subps x0, x1, x2
|
||||
# CHECK-NEXT: 1 1 0.25 subp x0, sp, sp
|
||||
# CHECK-NEXT: 1 1 0.25 U subps x0, sp, sp
|
||||
# CHECK-NEXT: 1 1 0.25 U subps xzr, x0, x1
|
||||
# CHECK-NEXT: 1 1 0.25 U subps xzr, sp, sp
|
||||
# CHECK-NEXT: 1 1 0.50 * stg x0, [x1, #-4096]
|
||||
# CHECK-NEXT: 1 1 0.50 * stg x1, [x2, #4080]
|
||||
# CHECK-NEXT: 1 1 0.50 * stg x2, [sp, #16]
|
||||
# CHECK-NEXT: 1 1 0.50 * stg x3, [x1]
|
||||
# CHECK-NEXT: 1 1 0.50 * stg sp, [x1]
|
||||
# CHECK-NEXT: 1 1 0.50 * stzg x0, [x1, #-4096]
|
||||
# CHECK-NEXT: 1 1 0.50 * stzg x1, [x2, #4080]
|
||||
# CHECK-NEXT: 1 1 0.50 * stzg x2, [sp, #16]
|
||||
# CHECK-NEXT: 1 1 0.50 * stzg x3, [x1]
|
||||
# CHECK-NEXT: 1 1 0.50 * stzg sp, [x1]
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg x1, [x2, #4080]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg x2, [sp, #16]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg sp, [sp, #16]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg x1, [x2, #4080]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg x2, [sp, #16]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg sp, [sp, #16]!
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg x0, [x1], #-4096
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg x1, [x2], #4080
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg x2, [sp], #16
|
||||
# CHECK-NEXT: 1 1 0.50 * U stg sp, [sp], #16
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg x0, [x1], #-4096
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg x1, [x2], #4080
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg x2, [sp], #16
|
||||
# CHECK-NEXT: 1 1 0.50 * U stzg sp, [sp], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * st2g x0, [x1, #-4096]
|
||||
# CHECK-NEXT: 2 1 1.00 * st2g x1, [x2, #4080]
|
||||
# CHECK-NEXT: 2 1 1.00 * st2g x2, [sp, #16]
|
||||
# CHECK-NEXT: 2 1 1.00 * st2g x3, [x1]
|
||||
# CHECK-NEXT: 2 1 1.00 * st2g sp, [x1]
|
||||
# CHECK-NEXT: 2 1 1.00 * stz2g x0, [x1, #-4096]
|
||||
# CHECK-NEXT: 2 1 1.00 * stz2g x1, [x2, #4080]
|
||||
# CHECK-NEXT: 2 1 1.00 * stz2g x2, [sp, #16]
|
||||
# CHECK-NEXT: 2 1 1.00 * stz2g x3, [x1]
|
||||
# CHECK-NEXT: 2 1 1.00 * stz2g sp, [x1]
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g x1, [x2, #4080]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g x2, [sp, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g sp, [sp, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g x1, [x2, #4080]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g x2, [sp, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g sp, [sp, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g x0, [x1], #-4096
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g x1, [x2], #4080
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g x2, [sp], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * U st2g sp, [sp], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g x0, [x1], #-4096
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g x1, [x2], #4080
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g x2, [sp], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * U stz2g sp, [sp], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #-1024]
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #1008]
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [sp, #16]
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp xzr, x1, [x2, #16]
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2, #16]
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2]
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #-1024]!
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #1008]!
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [sp, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp xzr, x1, [x2, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2, #16]!
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2], #-1024
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2], #1008
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [sp], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp xzr, x1, [x2], #16
|
||||
# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2], #16
|
||||
# CHECK-NEXT: 2 4 0.50 * ldg x0, [x1]
|
||||
# CHECK-NEXT: 2 4 0.50 * ldg x2, [sp, #-4096]
|
||||
# CHECK-NEXT: 2 4 0.50 * ldg x3, [x4, #4080]
|
||||
# CHECK-NEXT: 2 4 0.50 * U ldgm x0, [x1]
|
||||
# CHECK-NEXT: 2 4 0.50 * U ldgm x1, [sp]
|
||||
# CHECK-NEXT: 2 4 0.50 * U ldgm xzr, [x2]
|
||||
# CHECK-NEXT: 1 1 0.50 U stgm x0, [x1]
|
||||
# CHECK-NEXT: 1 1 0.50 U stgm x1, [sp]
|
||||
# CHECK-NEXT: 1 1 0.50 U stgm xzr, [x2]
|
||||
# CHECK-NEXT: 1 1 0.50 U stzgm x0, [x1]
|
||||
# CHECK-NEXT: 1 1 0.50 U stzgm x1, [sp]
|
||||
# CHECK-NEXT: 1 1 0.50 U stzgm xzr, [x2]
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - Ampere1BUnitA
|
||||
# CHECK-NEXT: [0.1] - Ampere1BUnitA
|
||||
# CHECK-NEXT: [1.0] - Ampere1BUnitB
|
||||
# CHECK-NEXT: [1.1] - Ampere1BUnitB
|
||||
# CHECK-NEXT: [2] - Ampere1BUnitBS
|
||||
# CHECK-NEXT: [3.0] - Ampere1BUnitL
|
||||
# CHECK-NEXT: [3.1] - Ampere1BUnitL
|
||||
# CHECK-NEXT: [4.0] - Ampere1BUnitS
|
||||
# CHECK-NEXT: [4.1] - Ampere1BUnitS
|
||||
# CHECK-NEXT: [5] - Ampere1BUnitX
|
||||
# CHECK-NEXT: [6] - Ampere1BUnitY
|
||||
# CHECK-NEXT: [7] - Ampere1BUnitZ
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7]
|
||||
# CHECK-NEXT: 2.50 2.50 13.00 13.00 5.00 3.00 3.00 58.00 58.00 - - -
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7] Instructions:
|
||||
# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg x0, x1
|
||||
# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg sp, x1
|
||||
# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg x0, sp
|
||||
# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg x0, x1, x2
|
||||
# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg sp, x1, x2
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x0, x1, #0, #1
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg sp, x2, #32, #3
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x0, sp, #64, #5
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x3, x4, #1008, #6
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x5, x6, #112, #15
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x0, x1, #0, #1
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg sp, x2, #32, #3
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x0, sp, #64, #5
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x3, x4, #1008, #6
|
||||
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x5, x6, #112, #15
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi x0, x1, x2
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi x3, sp, x4
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi xzr, x0, x30
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi x30, x0, xzr
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subp x0, x1, x2
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps x0, x1, x2
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subp x0, sp, sp
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps x0, sp, sp
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps xzr, x0, x1
|
||||
# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps xzr, sp, sp
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x0, [x1, #-4096]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x1, [x2, #4080]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x2, [sp, #16]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x3, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg sp, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x0, [x1, #-4096]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x1, [x2, #4080]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x2, [sp, #16]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x3, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg sp, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x1, [x2, #4080]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x2, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg sp, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x1, [x2, #4080]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x2, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg sp, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x0, [x1], #-4096
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x1, [x2], #4080
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x2, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg sp, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x0, [x1], #-4096
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x1, [x2], #4080
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x2, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg sp, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x0, [x1, #-4096]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x1, [x2, #4080]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x2, [sp, #16]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x3, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g sp, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x0, [x1, #-4096]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x1, [x2, #4080]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x2, [sp, #16]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x3, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g sp, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x1, [x2, #4080]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x2, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g sp, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x0, [x1, #-4096]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x1, [x2, #4080]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x2, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g sp, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x0, [x1], #-4096
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x1, [x2], #4080
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x2, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g sp, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x0, [x1], #-4096
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x1, [x2], #4080
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x2, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g sp, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #-1024]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #1008]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [sp, #16]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp xzr, x1, [x2, #16]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2, #16]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2]
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #-1024]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #1008]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [sp, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp xzr, x1, [x2, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2, #16]!
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2], #-1024
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2], #1008
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [sp], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp xzr, x1, [x2], #16
|
||||
# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2], #16
|
||||
# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldg x0, [x1]
|
||||
# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldg x2, [sp, #-4096]
|
||||
# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldg x3, [x4, #4080]
|
||||
# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldgm x0, [x1]
|
||||
# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldgm x1, [sp]
|
||||
# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldgm xzr, [x2]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stgm x0, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stgm x1, [sp]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stgm xzr, [x2]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzgm x0, [x1]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzgm x1, [sp]
|
||||
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzgm xzr, [x2]
|
||||
3235
llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
Normal file
3235
llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,31 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -march=aarch64 -mcpu=ampere1b -resource-pressure=false < %s | FileCheck %s
|
||||
|
||||
add w0, w1, w2, lsl #0
|
||||
sub x3, x4, x5, lsl #1
|
||||
adds x6, x7, x8, lsr #2
|
||||
subs x9, x10, x11, asr #3
|
||||
|
||||
# CHECK: Iterations: 100
|
||||
# CHECK-NEXT: Instructions: 400
|
||||
# CHECK-NEXT: Total Cycles: 156
|
||||
# CHECK-NEXT: Total uOps: 600
|
||||
|
||||
# CHECK: Dispatch Width: 12
|
||||
# CHECK-NEXT: uOps Per Cycle: 3.85
|
||||
# CHECK-NEXT: IPC: 2.56
|
||||
# CHECK-NEXT: Block RThroughput: 1.0
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 1 1 0.25 add w0, w1, w2
|
||||
# CHECK-NEXT: 1 1 0.25 sub x3, x4, x5, lsl #1
|
||||
# CHECK-NEXT: 2 2 0.50 adds x6, x7, x8, lsr #2
|
||||
# CHECK-NEXT: 2 2 0.50 subs x9, x10, x11, asr #3
|
||||
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Reference in New Issue
Block a user