[AMDGPU] Handle s_setreg_imm32_b32 targeting MODE register (#174681)
On certain hardware, this instruction clobbers VGPR MSB `bits[12:19]`, so we need to restore the current mode. Fixes SWDEV-571581.
This commit is contained in:
Shilei Tian
GitHub
parent
ac508575ed
commit
df3629dc0c
@ -1264,6 +1264,12 @@ def Feature1024AddressableVGPRs : SubtargetFeature<"1024-addressable-vgprs",
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"Has 1024 addressable VGPRs"
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>;
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def FeatureSetregVGPRMSBFixup : SubtargetFeature<"setreg-vgpr-msb-fixup",
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"HasSetregVGPRMSBFixup",
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"true",
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"S_SETREG to MODE clobbers VGPR MSB bits, requires fixup"
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>;
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def FeatureWaitXcnt : SubtargetFeature<"wait-xcnt",
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"HasWaitXcnt",
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"true",
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@ -2223,7 +2229,8 @@ def FeatureISAVersion12_50_Common : FeatureSet<
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def FeatureISAVersion12_50 : FeatureSet<
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!listconcat(FeatureISAVersion12_50_Common.Features,
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[FeatureAddressableLocalMemorySize327680])>;
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[FeatureAddressableLocalMemorySize327680,
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FeatureSetregVGPRMSBFixup])>;
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def FeatureISAVersion12_51 : FeatureSet<
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!listconcat(FeatureISAVersion12_50_Common.Features,
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@ -44,8 +44,11 @@
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "llvm/ADT/PackedVector.h"
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#include "llvm/ADT/bit.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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@ -63,6 +66,9 @@ class AMDGPULowerVGPREncoding {
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using ModeType = PackedVector<unsigned, BitsPerField,
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std::bitset<BitsPerField * NumFields>>;
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static constexpr unsigned VGPRMSBShift =
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llvm::countr_zero_constexpr<unsigned>(AMDGPU::Hwreg::DST_VGPR_MSB);
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class ModeTy : public ModeType {
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public:
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// bitset constructor will set all bits to zero
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@ -143,6 +149,16 @@ private:
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/// instruction to encourage more coissuing.
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MachineBasicBlock::instr_iterator
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handleCoissue(MachineBasicBlock::instr_iterator I);
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/// Handle S_SETREG_IMM32_B32 targeting MODE register. On certain hardware,
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/// this instruction clobbers VGPR MSB bits[12:19], so we need to restore
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/// the current mode. \returns true if the instruction was modified or a
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/// new one was inserted.
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bool handleSetregMode(MachineInstr &MI);
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/// Update bits[12:19] of the imm operand in S_SETREG_IMM32_B32 to contain
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/// the VGPR MSB mode value. \returns true if the immediate was changed.
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bool updateSetregModeImm(MachineInstr &MI, int64_t ModeValue);
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};
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bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
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@ -160,12 +176,19 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
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CurrentMode |= NewMode;
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CurrentMask |= Mask;
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MachineOperand &Op = MostRecentModeSet->getOperand(0);
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// Update MostRecentModeSet with the new mode. It can be either
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// S_SET_VGPR_MSB or S_SETREG_IMM32_B32 (with Size <= 12).
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if (MostRecentModeSet->getOpcode() == AMDGPU::S_SET_VGPR_MSB) {
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MachineOperand &Op = MostRecentModeSet->getOperand(0);
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// Carry old mode bits from the existing instruction.
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int64_t OldModeBits = Op.getImm() & (ModeMask << ModeWidth);
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Op.setImm(CurrentMode | OldModeBits);
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} else {
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assert(MostRecentModeSet->getOpcode() == AMDGPU::S_SETREG_IMM32_B32 &&
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"unexpected MostRecentModeSet opcode");
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updateSetregModeImm(*MostRecentModeSet, CurrentMode);
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}
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// Carry old mode bits from the existing instruction.
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int64_t OldModeBits = Op.getImm() & (ModeMask << ModeWidth);
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Op.setImm(CurrentMode | OldModeBits);
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return true;
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}
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@ -315,6 +338,82 @@ AMDGPULowerVGPREncoding::handleCoissue(MachineBasicBlock::instr_iterator I) {
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return Prev;
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}
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/// Convert mode value from S_SET_VGPR_MSB format to MODE register format.
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/// S_SET_VGPR_MSB uses: (src0[0-1], src1[2-3], src2[4-5], dst[6-7])
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/// MODE register uses: (dst[0-1], src0[2-3], src1[4-5], src2[6-7])
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/// This is a left rotation by 2 bits on an 8-bit value.
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static int64_t convertModeToSetregFormat(int64_t Mode) {
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assert(isUInt<8>(Mode) && "Mode expected to be 8-bit");
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return llvm::rotl<uint8_t>(static_cast<uint8_t>(Mode), /*R=*/2);
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}
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bool AMDGPULowerVGPREncoding::updateSetregModeImm(MachineInstr &MI,
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int64_t ModeValue) {
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assert(MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32);
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// Convert from S_SET_VGPR_MSB format to MODE register format
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int64_t SetregMode = convertModeToSetregFormat(ModeValue);
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MachineOperand *ImmOp = TII->getNamedOperand(MI, AMDGPU::OpName::imm);
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int64_t OldImm = ImmOp->getImm();
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int64_t NewImm =
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(OldImm & ~AMDGPU::Hwreg::VGPR_MSB_MASK) | (SetregMode << VGPRMSBShift);
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ImmOp->setImm(NewImm);
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return NewImm != OldImm;
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}
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bool AMDGPULowerVGPREncoding::handleSetregMode(MachineInstr &MI) {
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using namespace AMDGPU::Hwreg;
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assert(MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 &&
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"only S_SETREG_IMM32_B32 needs to be handled");
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MachineOperand *SIMM16Op = TII->getNamedOperand(MI, AMDGPU::OpName::simm16);
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assert(SIMM16Op && "SIMM16Op must be present");
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auto [HwRegId, Offset, Size] = HwregEncoding::decode(SIMM16Op->getImm());
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(void)Offset;
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if (HwRegId != ID_MODE)
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return false;
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int64_t ModeValue = static_cast<int64_t>(CurrentMode);
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// Case 1: Size <= 12 - the original instruction uses imm32[0:Size-1], so
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// imm32[12:19] is unused. Safe to set imm32[12:19] to the correct VGPR
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// MSBs.
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if (Size <= VGPRMSBShift) {
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// This instruction now acts as MostRecentModeSet so it can be updated if
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// CurrentMode changes via piggybacking.
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MostRecentModeSet = &MI;
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return updateSetregModeImm(MI, ModeValue);
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}
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// Case 2: Size > 12 - the original instruction uses bits beyond 11, so we
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// cannot arbitrarily modify imm32[12:19]. Check if it already matches VGPR
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// MSBs. Note: imm32[12:19] is in MODE register format, while ModeValue is
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// in S_SET_VGPR_MSB format, so we need to convert before comparing.
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MachineOperand *ImmOp = TII->getNamedOperand(MI, AMDGPU::OpName::imm);
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assert(ImmOp && "ImmOp must be present");
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int64_t ImmBits12To19 = (ImmOp->getImm() & VGPR_MSB_MASK) >> VGPRMSBShift;
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int64_t SetregModeValue = convertModeToSetregFormat(ModeValue);
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if (ImmBits12To19 == SetregModeValue) {
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// Already correct, but we must invalidate MostRecentModeSet because this
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// instruction will overwrite mode[12:19]. We can't update this instruction
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// via piggybacking (bits[12:19] are meaningful), so if CurrentMode changes,
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// a new s_set_vgpr_msb will be inserted after this instruction.
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MostRecentModeSet = nullptr;
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return false;
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}
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// imm32[12:19] doesn't match VGPR MSBs - insert s_set_vgpr_msb after
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// the original instruction to restore the correct value.
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MachineBasicBlock::iterator InsertPt = std::next(MI.getIterator());
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MostRecentModeSet = BuildMI(*MBB, InsertPt, MI.getDebugLoc(),
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TII->get(AMDGPU::S_SET_VGPR_MSB))
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.addImm(ModeValue);
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return true;
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}
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bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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if (!ST.has1024AddressableVGPRs())
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@ -359,6 +458,12 @@ bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
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continue;
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}
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if (MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 &&
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ST.hasSetregVGPRMSBFixup()) {
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Changed |= handleSetregMode(MI);
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continue;
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}
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Changed |= runOnMachineInstr(MI);
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if (ClauseRemaining)
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@ -244,6 +244,7 @@ protected:
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bool HasRestrictedSOffset = false;
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bool Has64BitLiterals = false;
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bool Has1024AddressableVGPRs = false;
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bool HasSetregVGPRMSBFixup = false;
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bool HasBitOp3Insts = false;
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bool HasTanhInsts = false;
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bool HasTensorCvtLutInsts = false;
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@ -1445,6 +1446,8 @@ public:
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bool has1024AddressableVGPRs() const { return Has1024AddressableVGPRs; }
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bool hasSetregVGPRMSBFixup() const { return HasSetregVGPRMSBFixup; }
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bool hasMinimum3Maximum3PKF16() const {
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return HasMinimum3Maximum3PKF16;
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}
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244
llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
Normal file
244
llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
Normal file
@ -0,0 +1,244 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
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---
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# Case 1a: Size < 12 (size=4), imm32[12:19]=0
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# S_SET_VGPR_MSB format: (src0_msb[0-1], src1_msb[2-3], src2_msb[4-5], dst_msb[6-7])
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# MODE register format: (dst_msb[0-1], src0_msb[2-3], src1_msb[4-5], src2_msb[6-7])
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# vgpr256/257 (both MSB=1): S_SET_VGPR_MSB mode = (1 << 0) | (1 << 6) = 65
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# MODE register mode = (1 << 0) | (1 << 2) = 5
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# New setreg imm = 0x5 | (5 << 12) = 0x5005 = 20485
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name: setreg_size_lt_12
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_size_lt_12
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
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S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 1b: Size == 12 (boundary), imm32[12:19]=0
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# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
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# New setreg imm = 0xABC | (5 << 12) = 0x5ABC = 23228
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name: setreg_size_eq_12
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_size_eq_12
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 22529, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=12, offset=0, hwreg=MODE: simm16 = 0x5801 = 22529
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S_SETREG_IMM32_B32 2748, 22529, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 1c: Size <= 12 with existing non-zero bits in imm32[12:19]
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# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
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# imm32 = 0x23005 (bits 12:19 = 0x23), result = 0x5005 = 20485 (bits 12:19 replaced with 5)
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name: setreg_size_lt_12_nonzero_upper
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_size_lt_12_nonzero_upper
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
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; imm32 = 0x23005 = 143365 (bits 12:19 = 0x23)
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S_SETREG_IMM32_B32 143365, 6145, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 2: Size > 12 (size=16), imm32[12:19] already matches VGPR MSBs
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# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
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# imm32 = 0x5ABC = 23228 (bits 12:19 = 5), no modification needed
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name: setreg_size_gt_12_match
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_size_gt_12_match
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=16, offset=0, hwreg=MODE: simm16 = 0x7801 = 30721
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; imm32 = 0x5ABC = 23228 (bits 12:19 = 5 = MODE register mode for vgpr256/257)
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S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 3: Size > 12 (size=16), imm32[12:19] doesn't match VGPR MSBs
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# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
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# imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23 != 5), must insert s_set_vgpr_msb after
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name: setreg_size_gt_12_mismatch
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_size_gt_12_mismatch
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=16, offset=0, hwreg=MODE: simm16 = 0x7801 = 30721
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; imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23 != 5)
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S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 4: Non-MODE hwreg should not be modified
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# This uses ID_STATUS=2 instead of ID_MODE=1
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# vgpr256/257: S_SET_VGPR_MSB mode = 65
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name: setreg_non_mode_hwreg
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_non_mode_hwreg
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 5, 6146, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=4, offset=0, hwreg=STATUS(2): simm16 = 2 | (0 << 6) | (3 << 11) = 0x1802 = 6146
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S_SETREG_IMM32_B32 5, 6146, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 5: Size <= 12 but VGPR MSBs already present (no change needed)
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# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
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# imm32 = 0x5005 = 20485 (bits 12:19 = 5 = MODE register mode)
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name: setreg_size_lt_12_already_correct
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_size_lt_12_already_correct
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
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; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
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; imm32 = 0x5005 = 20485 (bits 12:19 = 5 = MODE register mode)
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S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 6: Different VGPR MSB value (using different high VGPRs)
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# vgpr512/513 (both MSB=2): S_SET_VGPR_MSB mode = (2 << 0) | (2 << 6) = 130
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# MODE register mode = (2 << 0) | (2 << 2) = 10
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# New setreg imm = 0x5 | (10 << 12) = 0xA005 = 40965
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name: setreg_different_vgpr_msb
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_different_vgpr_msb
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||||
; CHECK: S_SET_VGPR_MSB 130, implicit-def $mode
|
||||
; CHECK-NEXT: $vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
|
||||
; CHECK-NEXT: S_SETREG_IMM32_B32 40965, 6145, implicit-def $mode, implicit $mode
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
$vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
|
||||
; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
|
||||
S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
# Case 7: Piggybacking successfully updates s_setreg_imm32_b32 (Size <= 12)
|
||||
# First VGPR (V_MOV vgpr256, vgpr257): S_SET_VGPR_MSB mode = 65, MODE register mode = 5
|
||||
# Second VGPR (V_ADD_U32 vgpr256, vgpr257, vgpr512):
|
||||
# S_SET_VGPR_MSB mode = (1 << 0) | (2 << 2) | (1 << 6) = 73 (src0=1, src1=2, dst=1)
|
||||
# MODE register mode = (1 << 0) | (1 << 2) | (2 << 4) = 37 (dst=1, src0=1, src1=2)
|
||||
# Piggybacking updates setreg imm32[12:19] from 5 to 37.
|
||||
# Final setreg imm = 5 | (37 << 12) = 151557
|
||||
name: setreg_size_le_12_piggyback_superset
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: setreg_size_le_12_piggyback_superset
|
||||
; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
|
||||
; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
|
||||
; CHECK-NEXT: S_SETREG_IMM32_B32 151557, 6145, implicit-def $mode, implicit $mode
|
||||
; CHECK-NEXT: $vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
|
||||
; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
|
||||
S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
|
||||
; Second instruction uses same dst/src0 (MSB=1) but adds src1 (MSB=2)
|
||||
$vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
# Case 8: s_setreg_imm32_b32 (Size <= 12) followed by VGPR with different mode bits
|
||||
# First VGPR (V_MOV vgpr256, vgpr0): S_SET_VGPR_MSB mode = 64, MODE register mode = 1
|
||||
# Second VGPR (V_MOV vgpr256, vgpr256): S_SET_VGPR_MSB mode = 65, MODE register mode = 5
|
||||
# Setreg gets MODE mode = 1 from first VGPR. Second VGPR needs different src0 bits,
|
||||
# so a new S_SET_VGPR_MSB is inserted. The new S_SET_VGPR_MSB has mode = 65 | (64 << 8) = 16449.
|
||||
name: setreg_size_le_12_then_different_vgpr
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
|
||||
; CHECK-LABEL: name: setreg_size_le_12_then_different_vgpr
|
||||
; CHECK: liveins: $vgpr0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: S_SET_VGPR_MSB 64, implicit-def $mode
|
||||
; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr0, implicit $exec
|
||||
; CHECK-NEXT: S_SETREG_IMM32_B32 4101, 6145, implicit-def $mode, implicit $mode
|
||||
; CHECK-NEXT: S_SET_VGPR_MSB 16449, implicit-def $mode
|
||||
; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr256, implicit $exec
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
$vgpr256 = V_MOV_B32_e32 $vgpr0, implicit $exec
|
||||
; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
|
||||
S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
|
||||
$vgpr256 = V_MOV_B32_e32 $vgpr256, implicit $exec
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
# Case 9: After s_setreg_imm32_b32 (Size > 12, matching), new s_set_vgpr_msb needed
|
||||
# First VGPR (vgpr256/257): S_SET_VGPR_MSB mode = 65, MODE register mode = 5
|
||||
# Setreg has size=16 with imm32[12:19]=5 (matches MODE register mode).
|
||||
# handleSetregMode sets MostRecentModeSet = nullptr (can't piggyback on Size > 12).
|
||||
# Second VGPR (vgpr512/513): S_SET_VGPR_MSB mode = 130, MODE register mode = 10
|
||||
# Since MostRecentModeSet = nullptr, a new s_set_vgpr_msb is inserted.
|
||||
# New s_set_vgpr_msb imm = NewMode | (OldMode << 8) = 130 | (65 << 8) = 16770
|
||||
name: setreg_size_gt_12_match_then_different_vgpr
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: setreg_size_gt_12_match_then_different_vgpr
|
||||
; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
|
||||
; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
|
||||
; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
|
||||
; CHECK-NEXT: S_SET_VGPR_MSB 16770, implicit-def $mode
|
||||
; CHECK-NEXT: $vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
$vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
|
||||
; size=16, offset=0, hwreg=MODE: simm16 = 0x7801 = 30721
|
||||
; imm32 = 0x5ABC = 23228 (bits 12:19 = 5 = MODE register mode, matches!)
|
||||
S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
|
||||
$vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
|
||||
S_ENDPGM 0
|
||||
...
|
||||
Loading…
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Reference in New Issue
Block a user