[mlir][AMDGPU] Add PermlaneSwapOp (#154345)
- Add PermlaneSwapOp that lowers to `rocdl.permlane16.swap` and `rocdl.permlane32.swap` --------- Co-authored-by: Jakub Kuderski <kubakuderski@gmail.com>
This commit is contained in:
Tim Gymnich
GitHub
parent
fc62990657
commit
e20fa4f412
@ -656,6 +656,48 @@ def AMDGPU_SwizzleBitModeOp : AMDGPU_Op<"swizzle_bitmode",
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}];
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}
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def AMDGPU_PermlaneSwapOp : AMDGPU_Op<"permlane_swap", [Pure, AllTypesMatch<["result", "src"]>]> {
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let summary = "AMDGPU permlane swap op";
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let description = [{
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High-level wrapper on `rocdl.permlane{16,32}.swap` variants for permutations
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on rows of lanes in a subgroup.
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Supports arbitrary int/float/vector types, which will be repacked to i32 and
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one or more `rocdl.permlane_swap` ops during lowering.
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Supported lane permutations:
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- Swap the data between odd and even rows of 16 lanes
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- Swap the data between the first 32 lanes and the last 32 lanes
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Example:
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```mlir
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%0 = amdgpu.permlane %src 16 : f16
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%1 = amdgpu.permlane %src 32 { fetch_inactive = true, bound_ctrl = true } : f16
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```
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Operands:
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* `$src`: Vector register to permute across lanes of the subgroup.
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* `$row_length`: The length of a row to permute in number of lanes (valid values are 16 and 32).
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* `$fetch_inactive`: Optional. Used to dertermine behavior of a fetch from a disabled lane.
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`fetch_inactive = false`: If the source lane is disabled, use `bound_ctrl` to determine the source value.
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`fetch_inactive = true`: If the source lane is disabled, fetch the source value anyway (ignoring `bound_ctrl`).
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* `$bound_ctrl`: Optional. Used to determine what a thread should do if its source operand is from
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a disabled lane: use the value zero, or disable the write.
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`bound_ctrl = false`: Do not write when source is from a disabled lane
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`bound_ctrl = true`: Use zero as input if source is from a disabled lane
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Note: Lowering is only supported on gfx950 and up.
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}];
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let arguments = (ins AnyIntegerOrFloatOr1DVector:$src,
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I32Attr:$row_length,
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DefaultValuedAttr<BoolAttr, "false">:$fetch_inactive,
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DefaultValuedAttr<BoolAttr, "false">:$bound_ctrl);
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let results = (outs AnyIntegerOrFloatOr1DVector:$result);
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let assemblyFormat = [{
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$src $row_length attr-dict `:` type($result)
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}];
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let hasVerifier = 1;
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}
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def AMDGPU_LDSBarrierOp : AMDGPU_Op<"lds_barrier"> {
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let summary = "Barrier that includes a wait for LDS memory operations.";
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let description = [{
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@ -14,6 +14,7 @@
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#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h"
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#include "mlir/Dialect/AMDGPU/Utils/Chipset.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
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#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/TypeUtilities.h"
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@ -1876,6 +1877,54 @@ struct AMDGPUSwizzleBitModeLowering
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}
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};
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struct AMDGPUPermlaneLowering : public ConvertOpToLLVMPattern<PermlaneSwapOp> {
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using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
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AMDGPUPermlaneLowering(const LLVMTypeConverter &converter, Chipset chipset)
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: ConvertOpToLLVMPattern<PermlaneSwapOp>(converter), chipset(chipset) {}
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Chipset chipset;
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LogicalResult
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matchAndRewrite(PermlaneSwapOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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if (chipset < kGfx950)
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return op->emitOpError("permlane_swap is only supported on gfx950+");
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Location loc = op.getLoc();
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Type i32 = rewriter.getI32Type();
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Value src = adaptor.getSrc();
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unsigned row_length = op.getRowLength();
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bool fi = op.getFetchInactive();
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bool boundctrl = op.getBoundCtrl();
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SmallVector<Value> decomposed =
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LLVM::decomposeValue(rewriter, loc, src, i32);
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SmallVector<Value> permuted;
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for (Value v : decomposed) {
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Value res;
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Type i32pair = LLVM::LLVMStructType::getLiteral(
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rewriter.getContext(), {v.getType(), v.getType()});
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if (row_length == 16)
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res = ROCDL::Permlane16SwapOp::create(rewriter, loc, i32pair, v, v, fi,
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boundctrl);
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else if (row_length == 32)
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res = ROCDL::Permlane32SwapOp::create(rewriter, loc, i32pair, v, v, fi,
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boundctrl);
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else
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llvm_unreachable("unsupported row length");
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Value vdstNew = LLVM::ExtractValueOp::create(rewriter, loc, res, {0});
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permuted.emplace_back(vdstNew);
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}
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Value result = LLVM::composeValue(rewriter, loc, permuted, src.getType());
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rewriter.replaceOp(op, result);
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return success();
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}
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};
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struct ConvertAMDGPUToROCDLPass
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: public impl::ConvertAMDGPUToROCDLPassBase<ConvertAMDGPUToROCDLPass> {
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using Base::Base;
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@ -1944,6 +1993,6 @@ void mlir::populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
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WMMAOpLowering, ExtPackedFp8OpLowering, ScaledExtPackedOpLowering,
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PackedScaledTruncOpLowering, PackedTrunc2xFp8OpLowering,
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PackedStochRoundFp8OpLowering, GatherToLDSOpLowering,
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TransposeLoadOpLowering>(converter, chipset);
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TransposeLoadOpLowering, AMDGPUPermlaneLowering>(converter, chipset);
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patterns.add<AMDGPUSwizzleBitModeLowering>(converter);
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}
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@ -510,6 +510,18 @@ LogicalResult DPPOp::verify() {
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return success();
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}
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//===----------------------------------------------------------------------===//
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// PermlaneSwapOp
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//===----------------------------------------------------------------------===//
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LogicalResult PermlaneSwapOp::verify() {
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unsigned rowLength = getRowLength();
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if (rowLength != 16 && rowLength != 32)
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return emitOpError("row_length attribute must either be 16 or 32.");
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return success();
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}
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//===----------------------------------------------------------------------===//
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// GatherToLDSOp
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//===----------------------------------------------------------------------===//
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163
mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir
Normal file
163
mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir
Normal file
@ -0,0 +1,163 @@
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// RUN: mlir-opt --convert-amdgpu-to-rocdl=chipset=gfx950 --canonicalize %s | FileCheck %s
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// CHECK-LABEL: func @test_permlane16_i32
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// CHECK-SAME: (%[[ARG0:.*]]: i32)
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func.func @test_permlane16_i32(%arg0 : i32) -> i32 {
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// CHECK: %[[PERM:.*]] = rocdl.permlane16.swap %[[ARG0]], %[[ARG0]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: return %[[RES]] : i32
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%0 = amdgpu.permlane_swap %arg0 16 : i32
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return %0 : i32
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}
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// CHECK-LABEL: func @test_permlane16_i32_optional_attr
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// CHECK-SAME: (%[[ARG0:.*]]: i32)
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func.func @test_permlane16_i32_optional_attr(%arg0 : i32) -> i32 {
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// CHECK: %[[PERM:.*]] = rocdl.permlane16.swap %[[ARG0]], %[[ARG0]], true, true : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: return %[[RES]] : i32
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%0 = amdgpu.permlane_swap %arg0 16 { fetch_inactive = true, bound_ctrl = true } : i32
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return %0 : i32
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}
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// CHECK-LABEL: func @test_permlane32_i32
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// CHECK-SAME: (%[[ARG0:.*]]: i32)
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func.func @test_permlane32_i32(%arg0 : i32) -> i32 {
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// CHECK: %[[PERM:.*]] = rocdl.permlane32.swap %[[ARG0]], %[[ARG0]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: return %[[RES]] : i32
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%0 = amdgpu.permlane_swap %arg0 32 : i32
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return %0 : i32
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}
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// CHECK-LABEL: func @test_permlane16_f32
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// CHECK-SAME: (%[[ARG0:.*]]: f32)
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func.func @test_permlane16_f32(%arg0 : f32) -> f32 {
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// CHECK: %[[CAST:.*]] = llvm.bitcast %[[ARG0]] : f32 to i32
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// CHECK: %[[PERM:.*]] = rocdl.permlane16.swap %[[CAST]], %[[CAST]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[RES_CAST:.*]] = llvm.bitcast %[[RES]] : i32 to f32
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// CHECK: return %[[RES_CAST]] : f32
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%0 = amdgpu.permlane_swap %arg0 16 : f32
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return %0 : f32
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}
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// CHECK-LABEL: func @test_permlane32_f32
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// CHECK-SAME: (%[[ARG0:.*]]: f32)
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func.func @test_permlane32_f32(%arg0 : f32) -> f32 {
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// CHECK: %[[CAST:.*]] = llvm.bitcast %[[ARG0]] : f32 to i32
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// CHECK: %[[PERM:.*]] = rocdl.permlane32.swap %[[CAST]], %[[CAST]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[RES_CAST:.*]] = llvm.bitcast %[[RES]] : i32 to f32
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// CHECK: return %[[RES_CAST]] : f32
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%0 = amdgpu.permlane_swap %arg0 32 : f32
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return %0 : f32
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}
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// CHECK-LABEL: func @test_permlane16_f16
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// CHECK-SAME: (%[[ARG0:.*]]: f16)
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func.func @test_permlane16_f16(%arg0 : f16) -> f16 {
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// CHECK: %[[CAST:.*]] = llvm.bitcast %[[ARG0]] : f16 to i16
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// CHECK: %[[ZEXT:.*]] = llvm.zext %[[CAST]] : i16 to i32
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// CHECK: %[[PERM:.*]] = rocdl.permlane16.swap %[[ZEXT]], %[[ZEXT]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[TRUNC:.*]] = llvm.trunc %[[RES]] : i32 to i16
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// CHECK: %[[RES_CAST:.*]] = llvm.bitcast %[[TRUNC]] : i16 to f16
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// CHECK: return %[[RES_CAST]] : f16
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%0 = amdgpu.permlane_swap %arg0 16 : f16
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return %0 : f16
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}
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// CHECK-LABEL: func @test_permlane32_f16
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// CHECK-SAME: (%[[ARG0:.*]]: f16)
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func.func @test_permlane32_f16(%arg0 : f16) -> f16 {
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// CHECK: %[[CAST:.*]] = llvm.bitcast %[[ARG0]] : f16 to i16
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// CHECK: %[[ZEXT:.*]] = llvm.zext %[[CAST]] : i16 to i32
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// CHECK: %[[PERM:.*]] = rocdl.permlane32.swap %[[ZEXT]], %[[ZEXT]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[RES:.*]] = llvm.extractvalue %[[PERM]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[TRUNC:.*]] = llvm.trunc %[[RES]] : i32 to i16
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// CHECK: %[[RES_CAST:.*]] = llvm.bitcast %[[TRUNC]] : i16 to f16
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// CHECK: return %[[RES_CAST]] : f16
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%0 = amdgpu.permlane_swap %arg0 32 : f16
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return %0 : f16
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}
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// CHECK-LABEL: func @test_permlane16_2xi32
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// CHECK-SAME: (%[[ARG0:.*]]: vector<2xi32>)
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func.func @test_permlane16_2xi32(%arg0 : vector<2xi32>) -> vector<2xi32> {
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// CHECK-DAG: %[[POISON:.*]] = llvm.mlir.poison : vector<2xi32>
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// CHECK-DAG: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK-DAG: %[[C0:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: %[[ELEM0:.*]] = llvm.extractelement %[[ARG0]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[ELEM1:.*]] = llvm.extractelement %[[ARG0]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: %[[PERM0_TUPLE:.*]] = rocdl.permlane16.swap %[[ELEM0]], %[[ELEM0]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM0:.*]] = llvm.extractvalue %[[PERM0_TUPLE]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[PERM1_TUPLE:.*]] = rocdl.permlane16.swap %[[ELEM1]], %[[ELEM1]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM1:.*]] = llvm.extractvalue %[[PERM1_TUPLE]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[VEC_INSERT0:.*]] = llvm.insertelement %[[PERM0]], %[[POISON]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[VEC_INSERT1:.*]] = llvm.insertelement %[[PERM1]], %[[VEC_INSERT0]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: return %[[VEC_INSERT1]] : vector<2xi32>
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%0 = amdgpu.permlane_swap %arg0 16 : vector<2xi32>
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return %0 : vector<2xi32>
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}
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// CHECK-LABEL: func @test_permlane32_2xi32
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// CHECK-SAME: (%[[ARG0:.*]]: vector<2xi32>)
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func.func @test_permlane32_2xi32(%arg0 : vector<2xi32>) -> vector<2xi32> {
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// CHECK-DAG: %[[POISON:.*]] = llvm.mlir.poison : vector<2xi32>
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// CHECK-DAG: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK-DAG: %[[C0:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: %[[ELEM0:.*]] = llvm.extractelement %[[ARG0]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[ELEM1:.*]] = llvm.extractelement %[[ARG0]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: %[[PERM0_TUPLE:.*]] = rocdl.permlane32.swap %[[ELEM0]], %[[ELEM0]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM0:.*]] = llvm.extractvalue %[[PERM0_TUPLE]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[PERM1_TUPLE:.*]] = rocdl.permlane32.swap %[[ELEM1]], %[[ELEM1]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM1:.*]] = llvm.extractvalue %[[PERM1_TUPLE]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[VEC_INSERT0:.*]] = llvm.insertelement %[[PERM0]], %[[POISON]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[VEC_INSERT1:.*]] = llvm.insertelement %[[PERM1]], %[[VEC_INSERT0]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: return %[[VEC_INSERT1]] : vector<2xi32>
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%0 = amdgpu.permlane_swap %arg0 32 : vector<2xi32>
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return %0 : vector<2xi32>
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}
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// CHECK-LABEL: func @test_permlane16_4xf16
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// CHECK-SAME: (%[[ARG0:.*]]: vector<4xf16>)
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func.func @test_permlane16_4xf16(%arg0 : vector<4xf16>) -> vector<4xf16> {
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// CHECK-DAG: %[[POISON:.*]] = llvm.mlir.poison : vector<2xi32>
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// CHECK-DAG: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK-DAG: %[[C0:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: %[[CAST1:.*]] = llvm.bitcast %[[ARG0]] : vector<4xf16> to vector<2xi32>
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// CHECK: %[[ELEM0:.*]] = llvm.extractelement %[[CAST1]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[ELEM1:.*]] = llvm.extractelement %[[CAST1]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: %[[PERM0_TUPLE:.*]] = rocdl.permlane16.swap %[[ELEM0]], %[[ELEM0]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM0:.*]] = llvm.extractvalue %[[PERM0_TUPLE]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[PERM1_TUPLE:.*]] = rocdl.permlane16.swap %[[ELEM1]], %[[ELEM1]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM1:.*]] = llvm.extractvalue %[[PERM1_TUPLE]][0] : !llvm.struct<(i32, i32)>
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// CHECK: %[[VEC_INSERT0:.*]] = llvm.insertelement %[[PERM0]], %[[POISON]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[VEC_INSERT1:.*]] = llvm.insertelement %[[PERM1]], %[[VEC_INSERT0]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: %[[CAST2:.*]] = llvm.bitcast %[[VEC_INSERT1]] : vector<2xi32> to vector<4xf16>
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// CHECK: return %[[CAST2]] : vector<4xf16>
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%0 = amdgpu.permlane_swap %arg0 16 : vector<4xf16>
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return %0 : vector<4xf16>
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}
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// CHECK-LABEL: func @test_permlane32_4xf16
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// CHECK-SAME: (%[[ARG0:.*]]: vector<4xf16>)
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func.func @test_permlane32_4xf16(%arg0 : vector<4xf16>) -> vector<4xf16> {
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// CHECK-DAG: %[[POISON:.*]] = llvm.mlir.poison : vector<2xi32>
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// CHECK-DAG: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK-DAG: %[[C0:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: %[[CAST1:.*]] = llvm.bitcast %[[ARG0]] : vector<4xf16> to vector<2xi32>
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// CHECK: %[[ELEM0:.*]] = llvm.extractelement %[[CAST1]][%[[C0]] : i32] : vector<2xi32>
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// CHECK: %[[ELEM1:.*]] = llvm.extractelement %[[CAST1]][%[[C1]] : i32] : vector<2xi32>
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// CHECK: %[[PERM0_TUPLE:.*]] = rocdl.permlane32.swap %[[ELEM0]], %[[ELEM0]], false, false : (i32, i32) -> <(i32, i32)>
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// CHECK: %[[PERM0:.*]] = llvm.extractvalue %[[PERM0_TUPLE]][0] : !llvm.struct<(i32, i32)>
|
||||
// CHECK: %[[PERM1_TUPLE:.*]] = rocdl.permlane32.swap %[[ELEM1]], %[[ELEM1]], false, false : (i32, i32) -> <(i32, i32)>
|
||||
// CHECK: %[[PERM1:.*]] = llvm.extractvalue %[[PERM1_TUPLE]][0] : !llvm.struct<(i32, i32)>
|
||||
// CHECK: %[[VEC_INSERT0:.*]] = llvm.insertelement %[[PERM0]], %[[POISON]][%[[C0]] : i32] : vector<2xi32>
|
||||
// CHECK: %[[VEC_INSERT1:.*]] = llvm.insertelement %[[PERM1]], %[[VEC_INSERT0]][%[[C1]] : i32] : vector<2xi32>
|
||||
// CHECK: %[[CAST2:.*]] = llvm.bitcast %[[VEC_INSERT1]] : vector<2xi32> to vector<4xf16>
|
||||
// CHECK: return %[[CAST2]] : vector<4xf16>
|
||||
%0 = amdgpu.permlane_swap %arg0 32 : vector<4xf16>
|
||||
return %0 : vector<4xf16>
|
||||
}
|
||||
@ -524,6 +524,20 @@ func.func @swizzle_bitmode(%arg0 : f32) -> f32 {
|
||||
func.return %0 : f32
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @permlane16_swap
|
||||
func.func @permlane16_swap(%arg0 : f32) -> f32 {
|
||||
// CHECK: amdgpu.permlane_swap
|
||||
%0 = amdgpu.permlane_swap %arg0 16 : f32
|
||||
func.return %0 : f32
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @permlane32_swap
|
||||
func.func @permlane32_swap(%arg0 : f32) -> f32 {
|
||||
// CHECK: amdgpu.permlane_swap
|
||||
%0 = amdgpu.permlane_swap %arg0 32 : f32
|
||||
func.return %0 : f32
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @scaled_mfma
|
||||
func.func @scaled_mfma(%arg0 : f8E8M0FNU, %arg1 : vector<32xf6E2M3FN>, %arg2 : vector<16xf32>) -> vector<16xf32> {
|
||||
// CHECK: amdgpu.scaled_mfma
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user